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Change subject: soc/intel/skylake: Drop EXCLUDE_NATIVE_SD_INTERFACE
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
Can somebody check why this was added? CB:12946, BUG=chrome-os-partner:48190
The commit speaks of "a list under device view". I was guessing some odd
tool that ignores PCI enumeration?
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Change subject: soc/intel/cannonlake/include: Drop unused code
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/intel/cannonlake/include: Drop unused code
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Patch Set 2:
(1 comment)
File src/soc/intel/cannonlake/include/soc/systemagent.h:
https://review.coreboot.org/c/coreboot/+/52775/comment/84906f6c_b0557a07
PS2, Line 47: IPUVTBAR
> It's dead code anyway and it seems nobody cared about it until now.
Sure. If it's wrong, we should still fix it :)
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Change subject: soc/amd/common: Add placeholder GPIO macro, PAD_UNCHANGED
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52763/comment/ec791e2a_7c8bd4f8
PS1, Line 9: GPIOs can only be updated in gpio_configure_pads_with_override() if they
: are present in the base table. If they are not there, the override
: does not work. This allows them to be in the base table so that they can
: be overridden without changing the existing configuration.
> I totally agree with the sentiment, and I had a patch that updated the behavior previously, but the […]
https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/…
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Change subject: mb/siemens/chili: Replace `def_bool` with `bool`
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Change subject: mb/kontron/bsl6: Replace `def_bool` with `bool`
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Change subject: mb/clevo/{kbl-u,cml-u}: Replace `def_bool` with `bool`
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Change subject: soc/intel/cannonlake: Clean up root port structs
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