coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

1 participants
6048 discussions

Change in coreboot[master]: vendorcode: add code for cezanne psp_verstage
by Martin Roth (Code Review) 02 May '21

02 May '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52750 ) Change subject: vendorcode: add code for cezanne psp_verstage ...................................................................... vendorcode: add code for cezanne psp_verstage These are mostly copied from picasso code with exception for bl_syscall_public.h. For some SVCs svc number and/or prototype has been changed. Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: I6b431fdbf34fca2747833980ae53c06244905f93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52750 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- A src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_end.S A src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_header.inc A src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_startup.S A src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_errorcodes_public.h A src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h 5 files changed, 435 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_end.S b/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_end.S new file mode 100644 index 0000000..40ea411 --- /dev/null +++ b/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_end.S @@ -0,0 +1,44 @@ +/***************************************************************************** + * + * Copyright (c) 2019, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +.arm +.global LastBytes +.section PSP_FOOTER_DATA, "ad", %note +.balign 64 + +// Note: this is used for determining the size of the binary. It is 64 byte aligned and 64 byte +// in size so that the binary size is multiple of 64 bytes. +// +LastBytes: + .byte 0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99 + .byte 0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99 + .byte 0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99 + .byte 0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99 + +.end diff --git a/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_header.inc b/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_header.inc new file mode 100644 index 0000000..35c906a --- /dev/null +++ b/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_header.inc @@ -0,0 +1,64 @@ +/***************************************************************************** + * + * Copyright (c) 2019, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +.global LastBytes + +#define BL_UAPP_START_ADDRESS 0x00036000 +#define SIZE_OF_THIS_HEADER 256 +#define SIZE_OF_PSP_END 64 +#define IMAGE_SIZE LastBytes + SIZE_OF_PSP_END - BL_UAPP_START_ADDRESS - SIZE_OF_THIS_HEADER + +#define IMAGE_VERSION 0x01,0x00,0x00,0x00 +#define FW_TYPE 0x52 + + + // 256 byte binary header + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 // nonce + .byte 0x00,0x00,0x00,0x00 // header version + .word IMAGE_SIZE + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte IMAGE_VERSION + .byte 0x00,0x00,0x00,0x00 // APU Family ID + .byte 0x00,0x01,0x00,0x00 // Load Address + .byte 0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte FW_TYPE + .byte 0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 diff --git a/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_startup.S b/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_startup.S new file mode 100644 index 0000000..f5f1e18e --- /dev/null +++ b/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_startup.S @@ -0,0 +1,71 @@ +/***************************************************************************** + * + * Copyright (c) 2019, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#include <arch/asm.h> +#include <bl_uapp/bl_errorcodes_public.h> + + .global Main + .global _psp_vs_start + + .global PSP_VERSTAGE_STACK_END + +.arm +.text +.section "PSP_HEADER_DATA", "aw", %note + +//============================================================================== +// First 256 bytes of the binary image contain the header. +// Executable code starts from offset 0x100. +//============================================================================== +#include "bl_uapp_header.inc" + +//============================================================================== +// This is entry point to the binary which is called by main Boot Loader. +//============================================================================== + +ENTRY(_psp_vs_start) + + ldr sp, =PSP_VERSTAGE_STACK_END // stack pointer + + // Return value contains Virtual Address of mapped stack + // + ldr lr, =ShouldNotBeReached // return address + + ldr r2, =Main // pass control to verstage main function + blx r2 + +// This point should not be reached. The Main() function should return +// to main BL using Svc_Exit(). +// +ShouldNotBeReached: + mov r0, #BL_ERR_GENERIC // Returned from Main + svc #0x0 // SVC_EXIT + +ENDPROC(_psp_vs_start) +.end diff --git a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_errorcodes_public.h b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_errorcodes_public.h new file mode 100644 index 0000000..4fa9a33 --- /dev/null +++ b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_errorcodes_public.h @@ -0,0 +1,37 @@ +/***************************************************************************** + * + * Copyright (c) 2020, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ + +#ifndef BL_ERRORCODES_PUBLIC_H +#define BL_ERRORCODES_PUBLIC_H + +/* Bootloader Return Codes, Error only (0x00 through 0x9F) */ +#define BL_OK 0x00 // General - Success +#define BL_ERR_GENERIC 0x01 // Generic Error Code + +#endif /* BL_ERRORCODES_PUBLIC_H */ diff --git a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h new file mode 100644 index 0000000..25a15e6 --- /dev/null +++ b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h @@ -0,0 +1,219 @@ +/***************************************************************************** + * + * Copyright (c) 2020, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _BL_SYSCALL_PUBLIC_H_ +#define _BL_SYSCALL_PUBLIC_H_ + +#include <stdint.h> + +#define SVC_EXIT 0x00 +#define SVC_ENTER 0x02 +#define SVC_DEBUG_PRINT 0x06 +#define SVC_DEBUG_PRINT_EX 0x1A +#define SVC_GET_BOOT_MODE 0x1C +#define SVC_GET_SPI_INFO 0x60 +#define SVC_MAP_SPIROM_DEVICE 0x61 +#define SVC_UNMAP_SPIROM_DEVICE 0x62 +#define SVC_MAP_FCH_IO_DEVICE 0x63 +#define SVC_UNMAP_FCH_IO_DEVICE 0x64 +#define SVC_UPDATE_PSP_BIOS_DIR 0x65 +#define SVC_COPY_DATA_FROM_UAPP 0x66 + +enum psp_boot_mode { + PSP_BOOT_MODE_S0 = 0x0, + PSP_BOOT_MODE_S0i3_RESUME = 0x1, + PSP_BOOT_MODE_S3_RESUME = 0x2, + PSP_BOOT_MODE_S4 = 0x3, + PSP_BOOT_MODE_S5_COLD = 0x4, + PSP_BOOT_MODE_S5_WARM = 0x5, +}; + +enum fch_io_device { + FCH_IO_DEVICE_SPI, + FCH_IO_DEVICE_I2C, + FCH_IO_DEVICE_GPIO, + FCH_IO_DEVICE_ESPI, + FCH_IO_DEVICE_IOMUX, + FCH_IO_DEVICE_MISC, + FCH_IO_DEVICE_AOAC, + FCH_IO_DEVICE_IOPORT, + + FCH_IO_DEVICE_END, +}; + +enum fch_i2c_controller_id { + FCH_I2C_CONTROLLER_ID_0 = 0, + FCH_I2C_CONTROLLER_ID_1 = 1, + FCH_I2C_CONTROLLER_ID_2 = 2, + FCH_I2C_CONTROLLER_ID_3 = 3, + FCH_I2C_CONTROLLER_ID_MAX, +}; + +struct spirom_info { + void *SpiBiosSysHubBase; + void *SpiBiosSmnBase; + uint32_t SpiBiosSize; +}; + +/* + * Exit to the main Boot Loader. This does not return back to user application. + * + * Parameters: + * status - either Ok or error code defined by AGESA + */ +void svc_exit(uint32_t status); + +/* Print debug message into serial console. + * + * Parameters: + * string - null-terminated string + */ +void svc_debug_print(const char *string); + +/* Print 4 DWORD values in hex to serial console + * + * Parameters: + * dword0...dword3 - 32-bit DWORD to print + */ +void svc_debug_print_ex(uint32_t dword0, + uint32_t dword1, uint32_t dword2, uint32_t dword3); + +/* Description - Returns the current boot mode from the enum psp_boot_mode found in + * bl_public.h. + * + * Inputs - boot_mode - Output parameter passed in R0 + * + * Outputs - The boot mode in boot_mode. + * See Return Values. + * + * Return Values - BL_OK + * BL_ERR_NULL_PTR + * Other BL_ERRORs lofted up from called functions + */ +uint32_t svc_get_boot_mode(uint32_t *boot_mode); + +/* Add delay in micro seconds + * + * Parameters: + * delay - required delay value in microseconds + * + * Return value: NONE + */ +void svc_delay_in_usec(uint32_t delay); + +/* Get the SPI-ROM information + * + * Parameters: + * spi_rom_iInfo - SPI-ROM information + * + * Return value: BL_OK or error code + */ +uint32_t svc_get_spi_rom_info(struct spirom_info *spi_rom_info); + +/* Map the FCH IO device register space (SPI/I2C/GPIO/eSPI/etc...) + * + * Parameters: + * io_device - ID for respective FCH IO controller register space to be mapped + * arg1 - Based on IODevice ID, interpretation of this argument changes. + * arg2 - Based on IODevice ID, interpretation of this argument changes. + * io_device_axi_addr - AXI address for respective FCH IO device register space + * + * Return value: BL_OK or error code + */ +uint32_t svc_map_fch_dev(enum fch_io_device io_device, + uint32_t arg1, uint32_t arg2, void **io_device_axi_addr); + +/* Unmap the FCH IO device register space mapped earlier using Svc_MapFchIODevice() + * + * Parameters: + * io_device - ID for respective FCH IO controller register space to be unmapped + * io_device_addr - AXI address for respective FCH IO device register space + * + * Return value: BL_OK or error code + */ +uint32_t svc_unmap_fch_dev(enum fch_io_device io_device, + void *io_device_axi_addr); + +/* Map the SPIROM FLASH device address space + * + * Parameters: + * SpiRomAddr - Address in SPIROM tobe mapped (SMN based) + * size - Size to be mapped + * pSpiRomAddrAxi - Mapped address in AXI space + * + * Return value: BL_OK or error code + */ +uint32_t svc_map_spi_rom(void *spi_rom_addr, + uint32_t size, void **spi_rom_axi_addr); + +/* Unmap the SPIROM FLASH device address space mapped earlier using Svc_MapSpiRomDevice() + * + * Parameters: + * pSpiRomAddrAxi - Address in AXI address space previously mapped + * + * Return value: BL_OK or error code + */ +uint32_t svc_unmap_spi_rom(void *spi_rom_addr); + +/* Updates the offset at which PSP or BIOS Directory can be found in the + * SPI flash + * + * Parameters: + * psp_dir_offset - [in/out] Offset at which PSP Directory can be + * found in the SPI Flash. Same pointer is used + * to return the offset in case of GET operation + * bios_dir_offset - [in/out] Offset at which BIOS Directory can be + * found in the SPI Flash. Same pointer is used + * to return the offset in case of GET operation + * + * Return value: BL_OK or error code + */ +uint32_t svc_update_psp_bios_dir(uint32_t *psp_dir_offset, + uint32_t *bios_dir_offset); + +/* Copies the data that is shared by verstage to the PSP BL owned memory + * + * Parameters: + * address - Address in UAPP controlled/owned memory + * size - Total size of memory to copy (max 16Kbytes) + */ +uint32_t svc_save_uapp_data(void *address, uint32_t size); + +/* + * Write postcode to Port-80 + * + * Parameters: + * postcode - Postcode value to be written on port-80h + */ +uint32_t svc_write_postcode(uint32_t postcode); + +/* C entry point for the Bootloader Userspace Application */ +void Main(void); + +#endif /* _BL_SYSCALL__PUBLIC_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b431fdbf34fca2747833980ae53c06244905f93 Gerrit-Change-Number: 52750 Gerrit-PatchSet: 2 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: vendorcode: add code for cezanne psp_verstage
by Martin Roth (Code Review) 02 May '21

02 May '21

Attention is currently required from: Kangheui Won. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52750 ) Change subject: vendorcode: add code for cezanne psp_verstage ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b431fdbf34fca2747833980ae53c06244905f93 Gerrit-Change-Number: 52750 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Comment-Date: Sun, 02 May 2021 18:22:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/common: Add placeholder GPIO macro, PAD_UNCHANGED
by Martin Roth (Code Review) 02 May '21

02 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52763 ) Change subject: soc/amd/common: Add placeholder GPIO macro, PAD_UNCHANGED ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52763/comment/622bff94_76b2061a PS1, Line 9: GPIOs can only be updated in gpio_configure_pads_with_override() if they : are present in the base table. If they are not there, the override : does not work. This allows them to be in the base table so that they can : be overridden without changing the existing configuration. > What's the level of effort required to fix this behavior? I would rather fix it then introduce anoth […] I totally agree with the sentiment, and I had a patch that updated the behavior previously, but the current behavior matches the behavior in Intel ChromeOS platforms, so I wasn't allowed to "fix" it. -- To view, visit https://review.coreboot.org/c/coreboot/+/52763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e5e7b7d30f2c89fa1db375ddba394e6914d97b9 Gerrit-Change-Number: 52763 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 02 May 2021 18:13:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/skylake: Drop EXCLUDE_NATIVE_SD_INTERFACE
by Felix Singer (Code Review) 02 May '21

02 May '21

Attention is currently required from: Nico Huber, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52789 to look at the new patch set (#5). Change subject: soc/intel/skylake: Drop EXCLUDE_NATIVE_SD_INTERFACE ...................................................................... soc/intel/skylake: Drop EXCLUDE_NATIVE_SD_INTERFACE EXCLUDE_NATIVE_SD_INTERFACE is used to exclude some ACPI code which is specific for its internal SD card controller, while ACPI code for other unused controllers is still included. Since this option doesn't do anything useful, drop it. Change-Id: Id07f59b5252cf3862724d6ff3d7c54d51ccfd9a6 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/google/fizz/Kconfig M src/mainboard/google/glados/Kconfig.name M src/mainboard/google/poppy/Kconfig M src/mainboard/kontron/bsl6/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/acpi/scs.asl 6 files changed, 0 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/52789/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/52789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id07f59b5252cf3862724d6ff3d7c54d51ccfd9a6 Gerrit-Change-Number: 52789 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/skylake: Drop EXCLUDE_NATIVE_SD_INTERFACE
by Felix Singer (Code Review) 02 May '21

02 May '21

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52789 ) Change subject: soc/intel/skylake: Drop EXCLUDE_NATIVE_SD_INTERFACE ...................................................................... Patch Set 4: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/52789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id07f59b5252cf3862724d6ff3d7c54d51ccfd9a6 Gerrit-Change-Number: 52789 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sun, 02 May 2021 17:38:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/cannonlake: Rename `SOC_INTEL_COMETLAKE`
by Felix Singer (Code Review) 02 May '21

02 May '21

Felix Singer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52776 ) Change subject: soc/intel/cannonlake: Rename `SOC_INTEL_COMETLAKE` ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/52776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I993f96f032c3b76a464474c83fee4442968be152 Gerrit-Change-Number: 52776 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: soc/intel/skylake: Add Kconfig option for LGA1151v2
by Angel Pons (Code Review) 02 May '21

02 May '21

Attention is currently required from: Timofey Komarov. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52692 ) Change subject: soc/intel/skylake: Add Kconfig option for LGA1151v2 ...................................................................... Patch Set 13: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52692/comment/ae1f4c14_4fcc2dd6 PS13, Line 25: Abmer Meh, just noticed a typo: A*mb*er It's too late now, though 😭 -- To view, visit https://review.coreboot.org/c/coreboot/+/52692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b6b9c676da55088cb5a12a218ea58d349ee440c Gerrit-Change-Number: 52692 Gerrit-PatchSet: 13 Gerrit-Owner: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Comment-Date: Sun, 02 May 2021 16:24:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in libgfxinit[master]: dp aux: Handle partially acked multi-byte I2C writes
by Angel Pons (Code Review) 02 May '21

02 May '21

Attention is currently required from: Nico Huber. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/52826 ) Change subject: dp aux: Handle partially acked multi-byte I2C writes ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: Didn't break anything on Purism Librem Mini v1: https://paste.flashrom.org/view.php?id=3470 -- To view, visit https://review.coreboot.org/c/libgfxinit/+/52826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I794dc1587f56b81539d1d4796f754644172f89b7 Gerrit-Change-Number: 52826 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Sun, 02 May 2021 16:07:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in libgfxinit[master]: Add support to switch LSPCON modes
by Angel Pons (Code Review) 02 May '21

02 May '21

Attention is currently required from: Nico Huber, Martin Roth, Matt DeVillier. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/51133 ) Change subject: Add support to switch LSPCON modes ...................................................................... Patch Set 11: Verified+1 (1 comment) Patchset: PS11: Proven with spark-discovery-gpl-2017 -- To view, visit https://review.coreboot.org/c/libgfxinit/+/51133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Idfa9bdff47a6591000cd5092d64a4cd4f8dbdc8d Gerrit-Change-Number: 51133 Gerrit-PatchSet: 11 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Sun, 02 May 2021 15:52:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in libgfxinit[master]: Add support to switch LSPCON modes
by Angel Pons (Code Review) 02 May '21

02 May '21

Attention is currently required from: Nico Huber, Martin Roth, Matt DeVillier. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/51133 ) Change subject: Add support to switch LSPCON modes ...................................................................... Patch Set 10: (1 comment) File common/hw-gfx-dp_dual_mode.adb: https://review.coreboot.org/c/libgfxinit/+/51133/comment/97f7f33a_0eb53409 PS7, Line 118: Time.M_Delay (1); > The loop below could be written like […] Done -- To view, visit https://review.coreboot.org/c/libgfxinit/+/51133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Idfa9bdff47a6591000cd5092d64a4cd4f8dbdc8d Gerrit-Change-Number: 51133 Gerrit-PatchSet: 10 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Sun, 02 May 2021 15:51:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2021