coreboot-gerrit May 2021

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Change in coreboot[master]: soc/intel/skylake: Clean up root port structs
by Felix Singer (Code Review) 03 May '21

03 May '21

Felix Singer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52627 ) Change subject: soc/intel/skylake: Clean up root port structs ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/52627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d5155356bd302ef938c76eb60688276fec67502 Gerrit-Change-Number: 52627 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/cannonlake/include: Drop unused code
by Felix Singer (Code Review) 03 May '21

03 May '21

Attention is currently required from: Michael Niewöhner, Patrick Rudolph. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52775 ) Change subject: soc/intel/cannonlake/include: Drop unused code ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/cannonlake/include/soc/systemagent.h: https://review.coreboot.org/c/coreboot/+/52775/comment/7ad06f38_00bbe229 PS2, Line 47: IPUVTBAR > hmm, I'm surprised that this isn't needed for CFL,CML since they do have an IPU device It's dead code anyway and it seems nobody cared about it until now. -- To view, visit https://review.coreboot.org/c/coreboot/+/52775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21689d1eae6952a80c98096443e7506a1466c07e Gerrit-Change-Number: 52775 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 02 May 2021 19:49:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Drop EXCLUDE_NATIVE_SD_INTERFACE
by Michael Niewöhner (Code Review) 03 May '21

03 May '21

Attention is currently required from: Felix Singer, Nico Huber, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52789 ) Change subject: soc/intel/skylake: Drop EXCLUDE_NATIVE_SD_INTERFACE ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id07f59b5252cf3862724d6ff3d7c54d51ccfd9a6 Gerrit-Change-Number: 52789 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 02 May 2021 19:46:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Allow enable/disable ME via CMOS
by Star Labs (Code Review) 03 May '21

03 May '21

Attention is currently required from: Star Labs, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52800 to look at the new patch set (#4). Change subject: soc/intel: Allow enable/disable ME via CMOS ...................................................................... soc/intel: Allow enable/disable ME via CMOS Add ME_STATE_BY_CMOS, that will disable the Intel ME. Message is only sent if me_state is set to 1. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20 --- M src/soc/intel/cannonlake/me.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h M src/soc/intel/skylake/me.c M src/soc/intel/tigerlake/me.c 5 files changed, 45 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/52800/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/52800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20 Gerrit-Change-Number: 52800 Gerrit-PatchSet: 4 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Star Labs <admin(a)starlabs.systems> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: Remove useless help texts
by Michael Niewöhner (Code Review) 03 May '21

03 May '21

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52786 ) Change subject: soc/intel/skylake: Remove useless help texts ...................................................................... soc/intel/skylake: Remove useless help texts Remove useless help texts since they don't add any more value. Change-Id: Iabcaec1bc8abe2c4628105752e49247e946fcfe7 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52786 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/skylake/Kconfig 1 file changed, 0 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index bd4c13e..3f02974 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -4,14 +4,10 @@ config SOC_INTEL_SKYLAKE bool select SOC_INTEL_COMMON_SKYLAKE_BASE - help - Intel Skylake support config SOC_INTEL_KABYLAKE bool select SOC_INTEL_COMMON_SKYLAKE_BASE - help - Intel Kabylake support config SOC_INTEL_SKYLAKE_LGA1151_V2 bool @@ -184,8 +180,6 @@ config SKYLAKE_SOC_PCH_H bool default n - help - Choose this option if you have a PCH-H chipset. config NHLT_DMIC_1CH bool -- To view, visit https://review.coreboot.org/c/coreboot/+/52786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabcaec1bc8abe2c4628105752e49247e946fcfe7 Gerrit-Change-Number: 52786 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/skylake: Remove useless help texts
by Michael Niewöhner (Code Review) 03 May '21

03 May '21

Attention is currently required from: Felix Singer, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52786 ) Change subject: soc/intel/skylake: Remove useless help texts ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabcaec1bc8abe2c4628105752e49247e946fcfe7 Gerrit-Change-Number: 52786 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 02 May 2021 19:43:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Remove useless help texts
by Michael Niewöhner (Code Review) 03 May '21

03 May '21

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52777 ) Change subject: soc/intel/cannonlake: Remove useless help texts ...................................................................... soc/intel/cannonlake: Remove useless help texts Remove useless help texts since they don't add any more value. Change-Id: Id8a15681a98ceb648814662545f5a3bf0f14b95c Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52777 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 0 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 65277f2..8c6cd53 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -7,8 +7,6 @@ select FSP_USES_CB_STACK select HAVE_INTEL_FSP_REPO select SOC_INTEL_CONFIGURE_DDI_A_4_LANES - help - Intel Coffeelake support config SOC_INTEL_WHISKEYLAKE bool @@ -16,8 +14,6 @@ select FSP_USES_CB_STACK select HAVE_INTEL_FSP_REPO select SOC_INTEL_CONFIGURE_DDI_A_4_LANES - help - Intel Whiskeylake support config SOC_INTEL_COMETLAKE bool @@ -25,8 +21,6 @@ select FSP_USES_CB_STACK select HAVE_INTEL_FSP_REPO select SOC_INTEL_CONFIGURE_DDI_A_4_LANES - help - Intel Cometlake support config SOC_INTEL_COMETLAKE_1 bool @@ -46,8 +40,6 @@ config SOC_INTEL_CANNONLAKE_PCH_H bool - help - Choose this option if you have a PCH-H chipset. if SOC_INTEL_CANNONLAKE_BASE -- To view, visit https://review.coreboot.org/c/coreboot/+/52777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8a15681a98ceb648814662545f5a3bf0f14b95c Gerrit-Change-Number: 52777 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/cannonlake: Remove useless help texts
by Michael Niewöhner (Code Review) 03 May '21

03 May '21

Attention is currently required from: Felix Singer, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52777 ) Change subject: soc/intel/cannonlake: Remove useless help texts ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8a15681a98ceb648814662545f5a3bf0f14b95c Gerrit-Change-Number: 52777 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 02 May 2021 19:42:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake/include: Drop unused code
by Michael Niewöhner (Code Review) 03 May '21

03 May '21

Attention is currently required from: Felix Singer, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52775 ) Change subject: soc/intel/cannonlake/include: Drop unused code ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/cannonlake/include/soc/systemagent.h: https://review.coreboot.org/c/coreboot/+/52775/comment/dba234c5_207a1a88 PS2, Line 47: IPUVTBAR hmm, I'm surprised that this isn't needed for CFL,CML since they do have an IPU device -- To view, visit https://review.coreboot.org/c/coreboot/+/52775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21689d1eae6952a80c98096443e7506a1466c07e Gerrit-Change-Number: 52775 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 02 May 2021 19:42:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: add verstage files
by Martin Roth (Code Review) 03 May '21

03 May '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52752 ) Change subject: soc/amd/cezanne: add verstage files ...................................................................... soc/amd/cezanne: add verstage files Add support for psp_verstage compilation. Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Iac48c92a787adabfdaec96b6e8d2e24708d7e652 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52752 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/include/soc/psp_verstage_addr.h A src/soc/amd/cezanne/psp_verstage/Makefile.inc A src/soc/amd/cezanne/psp_verstage/stub.c A src/soc/amd/cezanne/psp_verstage/svc.c A src/soc/amd/cezanne/psp_verstage/svc.h M src/soc/amd/common/psp_verstage/Makefile.inc 7 files changed, 264 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index f5cbcae..e51a616 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -5,6 +5,8 @@ subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr +subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage + # Beware that all-y also adds the compilation unit to verstage on PSP all-y += config.c all-y += aoac.c @@ -130,6 +132,18 @@ APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) +ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +# type = 0x6B - PSP Shared memory location +ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) +PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) +PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map) +endif + +# type = 0x52 - PSP Bootloader Userspace Application (verstage) +PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) +PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) +endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK + # Helper function to return a value with given bit set # Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. set-bit=$(call int-shift-left, 1 $(call _toint,$1)) @@ -143,6 +157,9 @@ add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) +OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) +OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) + OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) @@ -152,6 +169,8 @@ OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) +OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) +OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) @@ -178,6 +197,8 @@ --combo-capable \ $(OPT_TOKEN_UNLOCK) \ $(OPT_WHITELIST_FILE) \ + $(OPT_PSP_SHAREDMEM_BASE) \ + $(OPT_PSP_SHAREDMEM_SIZE) \ $(OPT_EFS_SPI_READ_MODE) \ $(OPT_EFS_SPI_SPEED) \ $(OPT_EFS_SPI_MICRON_FLAG) \ @@ -186,10 +207,13 @@ --flashsize $(CONFIG_ROM_SIZE) $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ + $(PSP_VERSTAGE_FILE) \ + $(PSP_VERSTAGE_SIG_FILE) \ $$(PSP_APCB_FILES) \ $(DEP_FILES) \ $(AMDFWTOOL) \ - $(obj)/fmap_config.h + $(obj)/fmap_config.h \ + $(objcbfs)/bootblock.elf # this target also creates the .map file $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" @@ -197,6 +221,8 @@ $(AMDFW_COMMON_ARGS) \ $(OPT_APOB_NV_SIZE) \ $(OPT_APOB_NV_BASE) \ + $(OPT_VERSTAGE_FILE) \ + $(OPT_VERSTAGE_SIG_FILE) \ --location $(shell printf "%#x" $(CEZANNE_FWM_POSITION)) \ --multilevel \ --output $@ diff --git a/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h b/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h new file mode 100644 index 0000000..bdc46cb --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_CEZANNE_PSP_VERSTAGE_ADDR_H +#define AMD_CEZANNE_PSP_VERSTAGE_ADDR_H + +/* + * Start of available space is 0x36000 and this is where the + * header for the user app (verstage) must be mapped. + * Size is 0x14000 bytes + */ +#define PSP_SRAM_START 0x36000 +#define PSP_SRAM_SIZE (80K) +#define VERSTAGE_START PSP_SRAM_START + +/* + * The top of the stack must be 4k aligned, so set the bottom as 4k aligned + * and make the size a multiple of 4k + */ + +#define PSP_VERSTAGE_STACK_START 0x49000 +#define PSP_VERSTAGE_STACK_SIZE (4K) + +#endif /* AMD_CEZANNE_PSP_VERSTAGE_ADDR_H */ diff --git a/src/soc/amd/cezanne/psp_verstage/Makefile.inc b/src/soc/amd/cezanne/psp_verstage/Makefile.inc new file mode 100644 index 0000000..8f268ca --- /dev/null +++ b/src/soc/amd/cezanne/psp_verstage/Makefile.inc @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-only + +verstage-generic-ccopts += -I$(src)/soc/amd/cezanne/psp_verstage/include +verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/cezanne/include + +verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include + +subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage + +verstage-y += svc.c +verstage-y += stub.c + +verstage-y += $(top)/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_startup.S +verstage-y += $(top)/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_end.S + +$(obj)/psp_verstage.bin: $(objcbfs)/verstage.elf + $(OBJCOPY_verstage) -O binary $^ $@ diff --git a/src/soc/amd/cezanne/psp_verstage/stub.c b/src/soc/amd/cezanne/psp_verstage/stub.c new file mode 100644 index 0000000..b3ec704 --- /dev/null +++ b/src/soc/amd/cezanne/psp_verstage/stub.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* This file contains stub for not-yet-implemented svc in cezanne PSP. + * So this file will and should be removed eventually when psp_verstage works + * correctly in cezanne. + */ + +#include <bl_uapp/bl_syscall_public.h> +#include <console/console.h> +#include <psp_verstage.h> +#include <reset.h> +#include <timer.h> + +uint32_t svc_write_postcode(uint32_t postcode) +{ + return 0; +} + +static uint64_t tmp_timer_value = 0; +void timer_monotonic_get(struct mono_time *mt) +{ + mt->microseconds = tmp_timer_value / 1000; + tmp_timer_value++; +} + +void do_board_reset(void) +{ + printk(BIOS_ERR, "Reset not implemented yet.\n"); + while (1) + ; +} diff --git a/src/soc/amd/cezanne/psp_verstage/svc.c b/src/soc/amd/cezanne/psp_verstage/svc.c new file mode 100644 index 0000000..3d10c22 --- /dev/null +++ b/src/soc/amd/cezanne/psp_verstage/svc.c @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "svc.h" + +#include <assert.h> +#include <bl_uapp/bl_syscall_public.h> +#include <psp_verstage.h> +#include <stddef.h> + +void svc_exit(uint32_t status) +{ + uint32_t unused = 0; + SVC_CALL0(SVC_EXIT, unused); +} + +void svc_debug_print(const char *string) +{ + uint32_t unused = 0; + SVC_CALL1(SVC_DEBUG_PRINT, (uint32_t)string, unused); +} + +void svc_debug_print_ex(uint32_t dword0, + uint32_t dword1, uint32_t dword2, uint32_t dword3) +{ + uint32_t unused = 0; + SVC_CALL4(SVC_DEBUG_PRINT_EX, dword0, dword1, dword2, dword3, unused); +} + +uint32_t svc_get_boot_mode(uint32_t *boot_mode) +{ + uint32_t retval = 0; + SVC_CALL1(SVC_GET_BOOT_MODE, boot_mode, retval); + return retval; +} + +void svc_delay_in_usec(uint32_t delay) +{ + uint32_t i; + for (i = 0; i < delay * 1000; i++) + asm volatile ("nop"); +} + +uint32_t svc_get_spi_rom_info(struct spirom_info *spi_rom_info) +{ + uint32_t retval = 0; + SVC_CALL1(SVC_GET_SPI_INFO, (uint32_t)spi_rom_info, retval); + return retval; +} + +uint32_t svc_map_fch_dev(enum fch_io_device io_device, + uint32_t arg1, uint32_t arg2, void **io_device_axi_addr) +{ + uint32_t retval = 0; + assert(io_device < FCH_IO_DEVICE_END); + SVC_CALL4(SVC_MAP_FCH_IO_DEVICE, io_device, arg1, arg2, + (uint32_t)io_device_axi_addr, retval); + return retval; +} + +uint32_t svc_unmap_fch_dev(enum fch_io_device io_device, void *io_device_axi_addr) +{ + uint32_t retval = 0; + assert(io_device < FCH_IO_DEVICE_END); + SVC_CALL2(SVC_UNMAP_FCH_IO_DEVICE, (uint32_t)io_device, + (uint32_t)io_device_axi_addr, retval); + return retval; +} + +uint32_t svc_map_spi_rom(void *spi_rom_addr, + uint32_t size, void **spi_rom_axi_addr) +{ + uint32_t retval = 0; + SVC_CALL3(SVC_MAP_SPIROM_DEVICE, spi_rom_addr, size, + (uint32_t)spi_rom_axi_addr, retval); + return retval; +} + +uint32_t svc_unmap_spi_rom(void *spi_rom_addr) +{ + uint32_t retval = 0; + SVC_CALL1(SVC_UNMAP_SPIROM_DEVICE, (uint32_t)spi_rom_addr, retval); + return retval; +} + +uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset) +{ + return svc_update_psp_bios_dir(psp_dir_offset, bios_dir_offset); +} + +uint32_t svc_update_psp_bios_dir(uint32_t *psp_dir_offset, + uint32_t *bios_dir_offset) +{ + uint32_t retval = 0; + SVC_CALL2(SVC_UPDATE_PSP_BIOS_DIR, (uint32_t)psp_dir_offset, + (uint32_t)bios_dir_offset, retval); + return retval; +} + +uint32_t save_uapp_data(void *address, uint32_t size) +{ + return svc_save_uapp_data(address, size); +} + +uint32_t svc_save_uapp_data(void *address, uint32_t size) +{ + uint32_t retval = 0; + SVC_CALL2(SVC_COPY_DATA_FROM_UAPP, (uint32_t)address, size, retval); + return retval; +} diff --git a/src/soc/amd/cezanne/psp_verstage/svc.h b/src/soc/amd/cezanne/psp_verstage/svc.h new file mode 100644 index 0000000..e44948e0 --- /dev/null +++ b/src/soc/amd/cezanne/psp_verstage/svc.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef PSP_VERSTAGE_SVC_H +#define PSP_VERSTAGE_SVC_H + +#define SVC_CALL4(SVC_ID, R0, R1, R2, R3, Ret) \ + __asm__ __volatile__ ( \ + "mov r0, %[reg0]\n\t" \ + "mov r1, %[reg1]\n\t" \ + "mov r2, %[reg2]\n\t" \ + "mov r3, %[reg3]\n\t" \ + "svc %[id]\n\t" \ + "mov %[result], r0\n\t" \ + : [result] "=r" (Ret) /* output */ \ + : [id] "i" (SVC_ID), [reg0] "r" (R0), [reg1] "r" (R1), [reg2] "r" (R2), \ + [reg3] "r" (R3) /* input(s) */ \ + : "r0", "r1", "r2", "r3", "memory", "cc" /* list of clobbered registers */) + +#define SVC_CALL3(SVC_ID, R0, R1, R2, Ret) \ + __asm__ __volatile__ ( \ + "mov r0, %[reg0]\n\t" \ + "mov r1, %[reg1]\n\t" \ + "mov r2, %[reg2]\n\t" \ + "svc %[id]\n\t" \ + "mov %[result], r0\n\t" \ + : [result] "=r" (Ret) /* output */ \ + : [id] "i" (SVC_ID), [reg0] "r" (R0), [reg1] "r" (R1), [reg2] "r" (R2) \ + : "r0", "r1", "r2", "memory", "cc" /* list of clobbered registers */) + +#define SVC_CALL2(SVC_ID, R0, R1, Ret) \ + __asm__ __volatile__ ( \ + "mov r0, %[reg0]\n\t" \ + "mov r1, %[reg1]\n\t" \ + "svc %[id]\n\t" \ + "mov %[result], r0\n\t" \ + : [result] "=r" (Ret) /* output */ \ + : [id] "i" (SVC_ID), [reg0] "r" (R0), [reg1] "r" (R1)/* input(s) */ \ + : "r0", "r1", "memory", "cc" /* list of clobbered registers */) + +#define SVC_CALL1(SVC_ID, R0, Ret) \ + __asm__ __volatile__ ( \ + "mov r0, %[reg0]\n\t" \ + "svc %[id]\n\t" \ + "mov %[result], r0\n\t" \ + : [result] "=r" (Ret) /* output */ \ + : [id] "i" (SVC_ID), [reg0] "r" (R0) /* input(s) */ \ + : "r0", "memory", "cc" /* list of clobbered registers */) + +#define SVC_CALL0(SVC_ID, Ret) \ + __asm__ __volatile__ ( \ + "svc %[id]\n\t" \ + "mov %[result], r0\n\t" \ + : [result] "=r" (Ret) /* output */ \ + : [id] "I" (SVC_ID) /* input(s) */ \ + : "memory", "cc" /* list of clobbered registers */) + +#endif /* PSP_VERSTAGE_SVC_H */ diff --git a/src/soc/amd/common/psp_verstage/Makefile.inc b/src/soc/amd/common/psp_verstage/Makefile.inc index 406d28b..a913a5b 100644 --- a/src/soc/amd/common/psp_verstage/Makefile.inc +++ b/src/soc/amd/common/psp_verstage/Makefile.inc @@ -1,7 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include -verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/picasso/include verstage-generic-ccopts += -D__USER_SPACE__ CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/2lib/include/ -- To view, visit https://review.coreboot.org/c/coreboot/+/52752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac48c92a787adabfdaec96b6e8d2e24708d7e652 Gerrit-Change-Number: 52752 Gerrit-PatchSet: 2 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit May 2021