coreboot-gerrit May 2021

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Change in coreboot[master]: mb/google/octopus/variant/phaser: add audio codec into SSFC support f...
by Kevin Chang (Code Review) 10 May '21

10 May '21

Attention is currently required from: Henry Sun, Paul Menzel, Marco Chen. Kevin Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52878 ) Change subject: mb/google/octopus/variant/phaser: add audio codec into SSFC support for Phaser ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52878/comment/d891e6ea_3b3199da PS6, Line 10: > Please mention that GPIO 137 is used. Update in patchset 7. -- To view, visit https://review.coreboot.org/c/coreboot/+/52878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I202f71f57ad2db84fb90b52f9ffd7a1fd05494a3 Gerrit-Change-Number: 52878 Gerrit-PatchSet: 7 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tiffany Li <tiffany.li(a)lcfc.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marco Chen <marcochen(a)chromium.org> Gerrit-Comment-Date: Mon, 10 May 2021 02:11:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/octopus/variant/phaser: add audio codec into SSFC support f...
by Kevin Chang (Code Review) 10 May '21

10 May '21

Attention is currently required from: Kevin Chang, Henry Sun, Marco Chen. Hello build bot (Jenkins), Henry Sun, Marco Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52878 to look at the new patch set (#7). Change subject: mb/google/octopus/variant/phaser: add audio codec into SSFC support for Phaser ...................................................................... mb/google/octopus/variant/phaser: add audio codec into SSFC support for Phaser Add audio codec module RT5682I in project and define GPIO_137 for audio codec IRQ using. BUG=b:182221327 BRANCH=octopus TEST=adjust SSFC value of CBI to select RT5682I or DA7219 then check whether device tree is updated correspondingly by disabling unselected one. Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Change-Id: I202f71f57ad2db84fb90b52f9ffd7a1fd05494a3 --- M src/mainboard/google/octopus/Kconfig.name M src/mainboard/google/octopus/variants/phaser/gpio.c M src/mainboard/google/octopus/variants/phaser/overridetree.cb 3 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/52878/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/52878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I202f71f57ad2db84fb90b52f9ffd7a1fd05494a3 Gerrit-Change-Number: 52878 Gerrit-PatchSet: 7 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tiffany Li <tiffany.li(a)lcfc.corp-partner.google.com> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Marco Chen <marcochen(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8195: enable ARM64_USE_ARM_TRUSTED_FIRMWARE
by Hung-Te Lin (Code Review) 10 May '21

10 May '21

Attention is currently required from: Rex-BC Chen. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53898 ) Change subject: soc/mediatek/mt8195: enable ARM64_USE_ARM_TRUSTED_FIRMWARE ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: before atf upstream is updated, can you temporarily remove this from review tree so we can have the rest changes getting merged first? -- To view, visit https://review.coreboot.org/c/coreboot/+/53898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1ef29894fa3a6022574c3874dee62617133b12c Gerrit-Change-Number: 53898 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Mon, 10 May 2021 02:00:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Add RTC driver
by Hung-Te Lin (Code Review) 10 May '21

10 May '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53897 ) Change subject: soc/mediatek/mt8195: Add RTC driver ...................................................................... soc/mediatek/mt8195: Add RTC driver Both mt8192 and mt8195 use MT659P RTC. Move mt8192/rtc.c to common folder and rename to rtc_mt6359p.c. Signed-off-by: Yuchen Huang <yuchen.huang(a)mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: I73ea90512228a659657f2019249e7142c673e68e Reviewed-on: https://review.coreboot.org/c/coreboot/+/53897 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/cherry/mainboard.c M src/mainboard/google/cherry/romstage.c R src/soc/mediatek/common/rtc_mt6359p.c M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/include/soc/pll.h A src/soc/mediatek/mt8195/include/soc/rtc.h A src/soc/mediatek/mt8195/include/soc/usb.h A src/soc/mediatek/mt8195/usb.c 9 files changed, 263 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/cherry/mainboard.c b/src/mainboard/google/cherry/mainboard.c index 37d3d1c6..5015531 100644 --- a/src/mainboard/google/cherry/mainboard.c +++ b/src/mainboard/google/cherry/mainboard.c @@ -10,6 +10,7 @@ #include <soc/i2c.h> #include <soc/mt6360.h> #include <soc/regulator.h> +#include <soc/usb.h> DEFINE_BITFIELD(MSDC0_DRV, 29, 0) DEFINE_BITFIELD(MSDC1_DRV, 17, 0) @@ -105,6 +106,7 @@ { configure_emmc(); configure_sdcard(); + setup_usb_host(); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/cherry/romstage.c b/src/mainboard/google/cherry/romstage.c index f4bb1ca..cdb2681 100644 --- a/src/mainboard/google/cherry/romstage.c +++ b/src/mainboard/google/cherry/romstage.c @@ -5,6 +5,7 @@ #include <soc/mt6315.h> #include <soc/mt6359p.h> #include <soc/pmif.h> +#include <soc/rtc.h> void platform_romstage_main(void) { @@ -12,4 +13,5 @@ mt6359p_init(); mt6315_init(); clk_buf_init(); + rtc_boot(); } diff --git a/src/soc/mediatek/mt8192/rtc.c b/src/soc/mediatek/common/rtc_mt6359p.c similarity index 100% rename from src/soc/mediatek/mt8192/rtc.c rename to src/soc/mediatek/common/rtc_mt6359p.c diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 484cfb8..2439417 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -38,7 +38,7 @@ romstage-y += ../common/pmif.c ../common/pmif_clk.c pmif_clk.c romstage-y += ../common/pmif_spi.c pmif_spi.c romstage-y += ../common/pmif_spmi.c pmif_spmi.c -romstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c +romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c romstage-y += ../common/mt6315.c mt6315.c romstage-y += ../common/mt6359p.c mt6359p.c @@ -57,7 +57,7 @@ ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += ../common/pmif.c -ramstage-y += ../common/rtc.c rtc.c +ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c ramstage-y += soc.c ramstage-y += spm.c ramstage-y += sspm.c diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index cc855b2..514acbd 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -35,6 +35,7 @@ romstage-y += ../common/pmif_spmi.c pmif_spmi.c romstage-y += ../common/mt6315.c mt6315.c romstage-y += ../common/mt6359p.c mt6359p.c +romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c ramstage-y += emi.c ramstage-y += ../common/flash_controller.c @@ -46,6 +47,7 @@ ramstage-y += soc.c ramstage-y += ../common/timer.c timer.c ramstage-y += ../common/uart.c +ramstage-y += ../common/usb.c usb.c ramstage-y += ../common/wdt.c ramstage-y += mt6360.c diff --git a/src/soc/mediatek/mt8195/include/soc/pll.h b/src/soc/mediatek/mt8195/include/soc/pll.h index 60fcbd9..cc133c8 100644 --- a/src/soc/mediatek/mt8195/include/soc/pll.h +++ b/src/soc/mediatek/mt8195/include/soc/pll.h @@ -168,6 +168,7 @@ }; check_member(mtk_topckgen_regs, clk_cfg_0, 0x0020); +check_member(mtk_topckgen_regs, clk_cfg_11_clr, 0x00ac); check_member(mtk_topckgen_regs, clk_extck_reg, 0x0204); check_member(mtk_topckgen_regs, clk26cali_0, 0x0218); check_member(mtk_topckgen_regs, clk_misc_cfg_0, 0x022c); diff --git a/src/soc/mediatek/mt8195/include/soc/rtc.h b/src/soc/mediatek/mt8195/include/soc/rtc.h new file mode 100644 index 0000000..9084731 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/rtc.h @@ -0,0 +1,218 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8195_RTC_H +#define SOC_MEDIATEK_MT8195_RTC_H + +#include <soc/pmif.h> +#include <stdbool.h> + +/* RTC registers */ +enum { + RTC_BBPU = 0x0588, + RTC_IRQ_STA = 0x058A, + RTC_IRQ_EN = 0x058C, + RTC_CII_EN = 0x058E, +}; + +enum { + RTC_TC_SEC = 0x0592, + RTC_TC_MIN = 0x0594, + RTC_TC_HOU = 0x0596, + RTC_TC_DOM = 0x0598, + RTC_TC_DOW = 0x059A, + RTC_TC_MTH = 0x059C, + RTC_TC_YEA = 0x059E, +}; + +enum { + RTC_AL_SEC = 0x05A0, + RTC_AL_MIN = 0x05A2, + RTC_AL_HOU = 0x05A4, + RTC_AL_DOM = 0x05A6, + RTC_AL_DOW = 0x05A8, + RTC_AL_MTH = 0x05AA, + RTC_AL_YEA = 0x05AC, + RTC_AL_MASK = 0x0590, +}; + +enum { + RTC_OSC32CON = 0x05AE, + RTC_CON = 0x05C4, + RTC_WRTGR = 0x05C2, +}; + +enum { + RTC_POWERKEY1 = 0x05B0, + RTC_POWERKEY2 = 0x05B2, +}; + +enum { + RTC_PDN1 = 0x05B4, + RTC_PDN2 = 0x05B6, + RTC_SPAR0 = 0x05B8, + RTC_SPAR1 = 0x05BA, + RTC_PROT = 0x05BC, + RTC_DIFF = 0x05BE, + RTC_CALI = 0x05C0, +}; + +enum { + RTC_BBPU_ENABLE_ALARM = 1U << 0, + RTC_BBPU_SPAR_SW = 1U << 1, + RTC_BBPU_RESET_SPAR = 1U << 2, + RTC_BBPU_RESET_ALARM = 1U << 3, + RTC_BBPU_CLRPKY = 1U << 4, + RTC_BBPU_RELOAD = 1U << 5, + RTC_BBPU_CBUSY = 1U << 6, + RTC_CBUSY_TIMEOUT_US = 1000000, +}; + +enum { + RTC_CON_VBAT_LPSTA_RAW = 1U << 0, + RTC_CON_EOSC32_LPEN = 1U << 1, + RTC_CON_XOSC32_LPEN = 1U << 2, + RTC_CON_LPRST = 1U << 3, + RTC_CON_CDBO = 1U << 4, + RTC_CON_F32KOB = 1U << 5, + RTC_CON_GPO = 1U << 6, + RTC_CON_GOE = 1U << 7, + RTC_CON_GSR = 1U << 8, + RTC_CON_GSMT = 1U << 9, + RTC_CON_GPEN = 1U << 10, + RTC_CON_GPU = 1U << 11, + RTC_CON_GE4 = 1U << 12, + RTC_CON_GE8 = 1U << 13, + RTC_CON_GPI = 1U << 14, + RTC_CON_LPSTA_RAW = 1U << 15, +}; + +enum { + RTC_XOSCCALI_MASK = 0x1F << 0, + RTC_XOSC32_ENB = 1U << 5, + RTC_EMB_HW_MODE = 0U << 6, + RTC_EMB_K_EOSC32_MODE = 1U << 6, + RTC_EMB_SW_DCXO_MODE = 2U << 6, + RTC_EMB_SW_EOSC32_MODE = 3U << 6, + RTC_EMBCK_SEL_MODE_MASK = 3U << 6, + RTC_EMBCK_SRC_SEL = 1U << 8, + RTC_EMBCK_SEL_OPTION = 1U << 9, + RTC_GPS_CKOUT_EN = 1U << 10, + RTC_EOSC32_VCT_EN = 1U << 11, + RTC_EOSC32_CHOP_EN = 1U << 12, + RTC_GP_OSC32_CON = 2U << 13, + RTC_REG_XOSC32_ENB = 1U << 15, +}; + +enum { + OSC32CON_ANALOG_SETTING = RTC_GP_OSC32_CON | RTC_EOSC32_CHOP_EN | + RTC_EOSC32_VCT_EN | RTC_GPS_CKOUT_EN | RTC_EMBCK_SEL_OPTION | + RTC_EMB_K_EOSC32_MODE, +}; + +enum { + RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13, + RTC_LPD_OPT_EOSC_LPD = 1U << 13, + RTC_LPD_OPT_XOSC_LPD = 2U << 13, + RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13, + RTC_LPD_OPT_MASK = 3U << 13, +}; + +/* PMIC TOP Register Definition */ +enum { + PMIC_RG_SCK_TOP_CON0 = 0x050C, +}; + +/* PMIC TOP Register Definition */ +enum { + PMIC_RG_TOP_CKPDN_CON0 = 0x010C, + PMIC_RG_TOP_CKPDN_CON0_SET = 0x010E, + PMIC_RG_TOP_CKPDN_CON0_CLR = 0x0110, + PMIC_RG_TOP_CKPDN_CON1 = 0x0112, + PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114, + PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116, + PMIC_RG_TOP_CKSEL_CON0 = 0x0118, + PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A, + PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C, +}; + +enum { + PMIC_RG_FQMTR_32K_CK_PDN_SHIFT = 10, + PMIC_RG_FQMTR_CK_PDN_SHIFT = 11, +}; + +enum { + PMIC_RG_BANK_FQMTR_RST = 0x522, +}; + +enum { + PMIC_RG_FQMTR_DCXO26M_EN_SHIFT = 4, + PMIC_RG_BANK_FQMTR_RST_SHIFT = 6, +}; + +/* PMIC Frequency Meter Definition */ +enum { + PMIC_RG_FQMTR_CKSEL = 0x0118, + PMIC_RG_FQMTR_RST = 0x013A, + PMIC_RG_FQMTR_CON0 = 0x0546, + PMIC_RG_FQMTR_WINSET = 0x0548, + PMIC_RG_FQMTR_DATA = 0x054A, + FQMTR_TIMEOUT_US = 8000, +}; + +enum { + PMIC_FQMTR_FIX_CLK_26M = 0U << 0, + PMIC_FQMTR_FIX_CLK_XOSC_32K_DET = 1U << 0, + PMIC_FQMTR_FIX_CLK_EOSC_32K = 2U << 0, + PMIC_FQMTR_FIX_CLK_RTC_32K = 3U << 0, + PMIC_FQMTR_FIX_CLK_DCXO1M_CK = 4U << 0, + PMIC_FQMTR_FIX_CLK_TCK_SEC = 5U << 0, + PMIC_FQMTR_FIX_CLK_PMU_32K = 6U << 0, + PMIC_FQMTR_CKSEL_MASK = 7U << 0, +}; + +enum { + PMIC_FQMTR_RST_SHIFT = 8, +}; + +enum { + PMIC_FQMTR_CON0_XOSC32_CK = 0U << 0, + PMIC_FQMTR_CON0_DCXO_F32K_CK = 1U << 0, + PMIC_FQMTR_CON0_EOSC32_CK = 2U << 0, + PMIC_FQMTR_CON0_XOSC32_CK_DETECTON = 3U << 0, + PMIC_FQMTR_CON0_FQM26M_CK = 4U << 0, + PMIC_FQMTR_CON0_FQM32k_CK = 5U << 0, + PMIC_FQMTR_CON0_TEST_CK = 6U << 0, + PMIC_FQMTR_CON0_TCKSEL_MASK = 7U << 0, + PMIC_FQMTR_CON0_BUSY = 1U << 3, + PMIC_FQMTR_CON0_DCXO26M_EN = 1U << 4, + PMIC_FQMTR_CON0_FQMTR_EN = 1U << 15, +}; + +enum { + RTC_FQMTR_LOW_BASE = 794 - 2, + RTC_FQMTR_HIGH_BASE = 794 + 2, +}; + +enum { + RTC_XOSCCALI_START = 0x00, + RTC_XOSCCALI_END = 0x1f, +}; + +enum { + RTC_TC_MTH_MASK = 0xf, +}; + +enum { + RTC_K_EOSC_RSV_0 = 1 << 8, + RTC_K_EOSC_RSV_1 = 1 << 9, + RTC_K_EOSC_RSV_2 = 1 << 10, +}; + +void rtc_read(u16 addr, u16 *rdata); +void rtc_write(u16 addr, u16 wdata); +void rtc_bbpu_power_on(void); +int rtc_init(int recover); +bool rtc_gpio_init(void); +void rtc_boot(void); +u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size); +#endif /* SOC_MEDIATEK_MT8195_RTC_H */ diff --git a/src/soc/mediatek/mt8195/include/soc/usb.h b/src/soc/mediatek/mt8195/include/soc/usb.h new file mode 100644 index 0000000..e39ec38 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/usb.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8195_USB_H +#define SOC_MEDIATEK_MT8195_USB_H + +#include <soc/usb_common.h> + +struct ssusb_sif_port { + struct sif_u2_phy_com u2phy; + u32 reserved0[64 * 5]; + struct sif_u3phyd u3phyd; + u32 reserved1[64]; + struct sif_u3phya u3phya; + struct sif_u3phya_da u3phya_da; + u32 reserved2[64 * 3]; +}; +check_member(ssusb_sif_port, u3phyd, 0x600); +check_member(ssusb_sif_port, u3phya, 0x800); +check_member(ssusb_sif_port, u3phya_da, 0x900); +check_member(ssusb_sif_port, reserved2, 0xa00); + +#define USB_PORT_NUMBER 1 + +#endif diff --git a/src/soc/mediatek/mt8195/usb.c b/src/soc/mediatek/mt8195/usb.c new file mode 100644 index 0000000..7b6347e --- /dev/null +++ b/src/soc/mediatek/mt8195/usb.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/infracfg.h> +#include <soc/pll.h> +#include <soc/usb.h> + +void mtk_usb_prepare(void) +{ + setbits32(&mtk_topckgen->clk_cfg_11_clr, BIT(7) | BIT(15)); + setbits32(&mt8195_infracfg_ao->module_sw_cg_2_clr, BIT(1) | BIT(31)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/53897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73ea90512228a659657f2019249e7142c673e68e Gerrit-Change-Number: 53897 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Yuchen Huang <yuchen.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8195: Add RTC driver
by Hung-Te Lin (Code Review) 10 May '21

10 May '21

Attention is currently required from: Rex-BC Chen. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53897 ) Change subject: soc/mediatek/mt8195: Add RTC driver ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: need rebase -- To view, visit https://review.coreboot.org/c/coreboot/+/53897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73ea90512228a659657f2019249e7142c673e68e Gerrit-Change-Number: 53897 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Yuchen Huang <yuchen.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Mon, 10 May 2021 01:58:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Add clk_buf driver
by Hung-Te Lin (Code Review) 10 May '21

10 May '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53896 ) Change subject: soc/mediatek/mt8195: Add clk_buf driver ...................................................................... soc/mediatek/mt8195: Add clk_buf driver Both mt8192 and mt8195 use mt6359p clk_buf. But mt8195 clk_buf uses legacy co-clock mode without srclken_rc. Signed-off-by: Yuchen Huang <yuchen.huang(a)mediatek.corp-partner.google.com> Change-Id: Ie9ee91449a7a14e77231493f807b321b2dbaa6a6 Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53896 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/cherry/romstage.c R src/soc/mediatek/common/clkbuf.c R src/soc/mediatek/common/include/soc/clkbuf.h M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8195/Makefile.inc 5 files changed, 9 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/cherry/romstage.c b/src/mainboard/google/cherry/romstage.c index cba5995..f4bb1ca 100644 --- a/src/mainboard/google/cherry/romstage.c +++ b/src/mainboard/google/cherry/romstage.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/stages.h> +#include <soc/clkbuf.h> #include <soc/mt6315.h> #include <soc/mt6359p.h> #include <soc/pmif.h> @@ -10,4 +11,5 @@ mtk_pmif_init(); mt6359p_init(); mt6315_init(); + clk_buf_init(); } diff --git a/src/soc/mediatek/mt8192/clkbuf.c b/src/soc/mediatek/common/clkbuf.c similarity index 98% rename from src/soc/mediatek/mt8192/clkbuf.c rename to src/soc/mediatek/common/clkbuf.c index 83fdb92..7354571 100644 --- a/src/soc/mediatek/mt8192/clkbuf.c +++ b/src/soc/mediatek/common/clkbuf.c @@ -5,8 +5,9 @@ #include <device/mmio.h> #include <soc/clkbuf.h> #include <soc/pmif.h> +#if CONFIG(SRCLKEN_RC_SUPPORT) #include <soc/srclken_rc.h> - +#endif #define BUFTAG "[CLKBUF]" #define buf_info(fmt, arg ...) printk(BIOS_INFO, BUFTAG "%s,%d: " fmt, \ diff --git a/src/soc/mediatek/mt8192/include/soc/clkbuf.h b/src/soc/mediatek/common/include/soc/clkbuf.h similarity index 92% rename from src/soc/mediatek/mt8192/include/soc/clkbuf.h rename to src/soc/mediatek/common/include/soc/clkbuf.h index b5fa3a3..d9bad06 100644 --- a/src/soc/mediatek/mt8192/include/soc/clkbuf.h +++ b/src/soc/mediatek/common/include/soc/clkbuf.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef SOC_MEDIATEK_MT8192_CLKBUF_H -#define SOC_MEDIATEK_MT8192_CLKBUF_H +#ifndef SOC_MEDIATEK_COMMON_CLKBUF_H +#define SOC_MEDIATEK_COMMON_CLKBUF_H #include <device/mmio.h> @@ -66,4 +66,4 @@ int clk_buf_init(void); -#endif /* SOC_MEDIATEK_MT8192_CLKBUF_H */ +#endif /* SOC_MEDIATEK_COMMON_CLKBUF_H */ diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index e2abc5e..484cfb8 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -23,7 +23,7 @@ romstage-y += ../common/auxadc.c romstage-y += ../common/cbmem.c -romstage-y += clkbuf.c srclken_rc.c +romstage-y += ../common/clkbuf.c srclken_rc.c romstage-y += ../common/dram_init.c romstage-y += ../common/dramc_param.c romstage-y += ../common/flash_controller.c diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index c344849..cc855b2 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -20,6 +20,7 @@ verstage-y += ../common/wdt.c romstage-y += ../common/cbmem.c +romstage-y += ../common/clkbuf.c romstage-y += emi.c romstage-y += ../common/flash_controller.c romstage-y += ../common/gpio.c gpio.c -- To view, visit https://review.coreboot.org/c/coreboot/+/53896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9ee91449a7a14e77231493f807b321b2dbaa6a6 Gerrit-Change-Number: 53896 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Yuchen Huang <yuchen.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8195: Configure eMMC and SDCard
by Hung-Te Lin (Code Review) 10 May '21

10 May '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53895 ) Change subject: soc/mediatek/mt8195: Configure eMMC and SDCard ...................................................................... soc/mediatek/mt8195: Configure eMMC and SDCard Change-Id: I0ed82e860612e8a62f361e60d217280f775ab239 Signed-off-by: Wenbin Mei <wenbin.mei(a)mediatek.com> Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53895 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/cherry/Makefile.inc A src/mainboard/google/cherry/mainboard.c M src/soc/mediatek/mt8195/Makefile.inc 3 files changed, 120 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/cherry/Makefile.inc b/src/mainboard/google/cherry/Makefile.inc index a1aa2fd..4720dc5 100644 --- a/src/mainboard/google/cherry/Makefile.inc +++ b/src/mainboard/google/cherry/Makefile.inc @@ -12,4 +12,5 @@ ramstage-y += memlayout.ld ramstage-y += chromeos.c +ramstage-y += mainboard.c ramstage-y += reset.c diff --git a/src/mainboard/google/cherry/mainboard.c b/src/mainboard/google/cherry/mainboard.c new file mode 100644 index 0000000..37d3d1c6 --- /dev/null +++ b/src/mainboard/google/cherry/mainboard.c @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/mmio.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <soc/i2c.h> +#include <soc/mt6360.h> +#include <soc/regulator.h> + +DEFINE_BITFIELD(MSDC0_DRV, 29, 0) +DEFINE_BITFIELD(MSDC1_DRV, 17, 0) +DEFINE_BITFIELD(MSDC1_GPIO_MODE0_0, 26, 24) +DEFINE_BITFIELD(MSDC1_GPIO_MODE0_1, 30, 28) +DEFINE_BITFIELD(MSDC1_GPIO_MODE1_0, 2, 0) +DEFINE_BITFIELD(MSDC1_GPIO_MODE1_1, 6, 4) +DEFINE_BITFIELD(MSDC1_GPIO_MODE1_2, 10, 8) +DEFINE_BITFIELD(MSDC1_GPIO_MODE1_3, 14, 12) + +#define MSDC0_DRV_VALUE 0x1b6db6db +#define MSDC1_DRV_VALUE 0x1b6db +#define MSDC1_GPIO_MODE0_VALUE 0x1 +#define MSDC1_GPIO_MODE1_VALUE 0x1 + +enum { + MSDC1_GPIO_MODE0_BASE = 0x100053d0, + MSDC1_GPIO_MODE1_BASE = 0x100053e0, +}; + +static void configure_emmc(void) +{ + void *gpio_base = (void *)IOCFG_TL_BASE; + int i; + + const gpio_t emmc_pu_pin[] = { + GPIO(EMMC_DAT0), GPIO(EMMC_DAT1), + GPIO(EMMC_DAT2), GPIO(EMMC_DAT3), + GPIO(EMMC_DAT4), GPIO(EMMC_DAT5), + GPIO(EMMC_DAT6), GPIO(EMMC_DAT7), + GPIO(EMMC_CMD), GPIO(EMMC_RSTB), + }; + + const gpio_t emmc_pd_pin[] = { + GPIO(EMMC_DSL), GPIO(EMMC_CLK), + }; + + for (i = 0; i < ARRAY_SIZE(emmc_pu_pin); i++) + gpio_set_pull(emmc_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); + + for (i = 0; i < ARRAY_SIZE(emmc_pd_pin); i++) + gpio_set_pull(emmc_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + + /* set eMMC cmd/dat/clk/ds/rstb pins driving to 8mA */ + SET32_BITFIELDS(gpio_base, MSDC0_DRV, MSDC0_DRV_VALUE); +} + +static void configure_sdcard(void) +{ + void *gpio_base = (void *)IOCFG_RB_BASE; + void *gpio_mode0_base = (void *)MSDC1_GPIO_MODE0_BASE; + void *gpio_mode1_base = (void *)MSDC1_GPIO_MODE1_BASE; + int i; + + const gpio_t sdcard_pu_pin[] = { + GPIO(MSDC1_DAT0), GPIO(MSDC1_DAT1), + GPIO(MSDC1_DAT2), GPIO(MSDC1_DAT3), + GPIO(MSDC1_CMD), + }; + + const gpio_t sdcard_pd_pin[] = { + GPIO(MSDC1_CLK), + }; + + for (i = 0; i < ARRAY_SIZE(sdcard_pu_pin); i++) + gpio_set_pull(sdcard_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); + + for (i = 0; i < ARRAY_SIZE(sdcard_pd_pin); i++) + gpio_set_pull(sdcard_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + + /* set sdcard cmd/dat/clk pins driving to 8mA */ + SET32_BITFIELDS(gpio_base, MSDC1_DRV, MSDC1_DRV_VALUE); + + /* set sdcard dat2/dat0/dat3/cmd/clk pins to msdc1 mode */ + SET32_BITFIELDS(gpio_mode0_base, + MSDC1_GPIO_MODE0_0, MSDC1_GPIO_MODE0_VALUE, + MSDC1_GPIO_MODE0_1, MSDC1_GPIO_MODE0_VALUE); + + /* set sdcard dat1 pin to msdc1 mode */ + SET32_BITFIELDS(gpio_mode1_base, + MSDC1_GPIO_MODE1_0, MSDC1_GPIO_MODE1_VALUE, + MSDC1_GPIO_MODE1_1, MSDC1_GPIO_MODE1_VALUE, + MSDC1_GPIO_MODE1_2, MSDC1_GPIO_MODE1_VALUE, + MSDC1_GPIO_MODE1_3, MSDC1_GPIO_MODE1_VALUE); + + mtk_i2c_bus_init(7); + mt6360_init(7); + mt6360_ldo_enable(MT6360_LDO3, 1); + mt6360_ldo_enable(MT6360_LDO5, 1); +} + +static void mainboard_init(struct device *dev) +{ + configure_emmc(); + configure_sdcard(); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +}; diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index aca3905..c344849 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -46,6 +46,7 @@ ramstage-y += ../common/timer.c timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/wdt.c +ramstage-y += mt6360.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8195/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include -- To view, visit https://review.coreboot.org/c/coreboot/+/53895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ed82e860612e8a62f361e60d217280f775ab239 Gerrit-Change-Number: 53895 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8195: Add i2c driver support
by Hung-Te Lin (Code Review) 10 May '21

10 May '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53894 ) Change subject: soc/mediatek/mt8195: Add i2c driver support ...................................................................... soc/mediatek/mt8195: Add i2c driver support TEST=write/read EEPROM on MT8195 EVB successfully Change-Id: Ia26e55512501e9758d7f5543d176730cf30ce03d Signed-off-by: kewei xu <kewei.xu(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53894 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/i2c.c A src/soc/mediatek/mt8195/include/soc/i2c.h 3 files changed, 230 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index f848f7b..aca3905 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -3,6 +3,7 @@ bootblock-y += bootblock.c bootblock-y += ../common/flash_controller.c bootblock-y += ../common/gpio.c gpio.c +bootblock-y += ../common/i2c.c i2c.c bootblock-y += ../common/mmu_operations.c bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c @@ -12,6 +13,7 @@ verstage-y += ../common/flash_controller.c verstage-y += ../common/gpio.c gpio.c +verstage-y += ../common/i2c.c i2c.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c timer.c verstage-y += ../common/uart.c @@ -21,6 +23,7 @@ romstage-y += emi.c romstage-y += ../common/flash_controller.c romstage-y += ../common/gpio.c gpio.c +romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/pll.c pll.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c timer.c @@ -35,6 +38,7 @@ ramstage-y += emi.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c +ramstage-y += ../common/i2c.c i2c.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c diff --git a/src/soc/mediatek/mt8195/i2c.c b/src/soc/mediatek/mt8195/i2c.c new file mode 100644 index 0000000..648083e --- /dev/null +++ b/src/soc/mediatek/mt8195/i2c.c @@ -0,0 +1,168 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <device/mmio.h> +#include <soc/pll.h> +#include <soc/i2c.h> +#include <soc/gpio.h> + +#define I2C_CLK_HZ (UNIVPLL_HZ / 20) +#define I2C_FULL_DUTY 100 +#define I2C_HALF_DUTY 50 +#define I2C_ADJUSTED_DUTY 50 +#define I2C_FS_START_CON 0x0 + +struct mtk_i2c mtk_i2c_bus_controller[] = { + [0] = { + .i2c_regs = (void *)(I2C_BASE), + .i2c_dma_regs = (void *)(I2C_DMA_BASE), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + [1] = { + .i2c_regs = (void *)(I2C_BASE + 0x1000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x180), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + [2] = { + .i2c_regs = (void *)(I2C_BASE + 0x2000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x300), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + [3] = { + .i2c_regs = (void *)(I2C_BASE + 0x3000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x400), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + [4] = { + .i2c_regs = (void *)(I2C_BASE + 0x4000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x480), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + [5] = { + .i2c_regs = (void *)(I2C_BASE - 0x100000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x500), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + [6] = { + .i2c_regs = (void *)(I2C_BASE - 0xFF000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x580), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + [7] = { + .i2c_regs = (void *)(I2C_BASE - 0xFE000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x600), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, +}; + +#define I2C_BUS_NUMBER ARRAY_SIZE(mtk_i2c_bus_controller) + +struct pad_func { + gpio_t gpio; + u8 func; +}; + +#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} + +static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = { + [0] = { + PAD_FUNC(SDA0, SDA0), + PAD_FUNC(SCL0, SCL0), + }, + [1] = { + PAD_FUNC(SDA1, SDA1), + PAD_FUNC(SCL1, SCL1), + }, + [2] = { + PAD_FUNC(SDA2, SDA2), + PAD_FUNC(SCL2, SCL2), + }, + [3] = { + PAD_FUNC(SDA3, SDA3), + PAD_FUNC(SCL3, SCL3), + }, + [4] = { + PAD_FUNC(SDA4, SDA4), + PAD_FUNC(SCL4, SCL4), + }, + [5] = { + PAD_FUNC(HDMIRX_SCL, SCL5), + PAD_FUNC(HDMIRX_SDA, SDA5), + }, + [6] = { + PAD_FUNC(HDMITX_SCL, SCL6), + PAD_FUNC(HDMITX_SDA, SDA6), + }, + [7] = { + PAD_FUNC(HDMIRX_HTPLG, SCL7), + PAD_FUNC(HDMIRX_PWR5V, SDA7), + }, + +}; + +static void mtk_i2c_set_gpio_pinmux(uint8_t bus) +{ + assert(bus < I2C_BUS_NUMBER); + + const struct pad_func *ptr = i2c_funcs[bus]; + for (size_t i = 0; i < 2; i++) { + gpio_set_mode(ptr[i].gpio, ptr[i].func); + if (bus <= I2C4) + gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP); + } +} + +static void mtk_i2c_speed_init(uint8_t bus) +{ + uint8_t step_div; + const uint8_t clock_div = 5; + const uint8_t sample_div = 1; + uint32_t i2c_freq; + uint32_t tar_speed = 400; + uint32_t tar_speed_high; + uint32_t tar_speed_low; + + assert(bus < I2C_BUS_NUMBER); + + /* Adjust ratio of high/low level */ + tar_speed_high = tar_speed * I2C_HALF_DUTY / I2C_ADJUSTED_DUTY; + + /* Calculate i2c frequency */ + step_div = DIV_ROUND_UP(I2C_CLK_HZ, + (tar_speed_high * KHz * sample_div * 2) * clock_div); + i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2 * clock_div); + assert(sample_div < 8 && step_div < 64 && + i2c_freq <= tar_speed_high * KHz && + i2c_freq >= (tar_speed_high - 20) * KHz); + + /* Init i2c bus timing register */ + write32(&mtk_i2c_bus_controller[bus].i2c_regs->timing, + (sample_div - 1) << 8 | (step_div - 1)); + + /* Adjust ratio of high/low level */ + tar_speed_low = tar_speed * I2C_HALF_DUTY / + (I2C_FULL_DUTY - I2C_ADJUSTED_DUTY); + + /* Calculate i2c frequency */ + step_div = DIV_ROUND_UP(I2C_CLK_HZ, + (tar_speed_low * KHz * sample_div * 2) * clock_div); + i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2 * clock_div); + assert(sample_div < 8 && step_div < 64 && + i2c_freq <= tar_speed_low * KHz && + i2c_freq >= (tar_speed_low - 20) * KHz); + write32(&mtk_i2c_bus_controller[bus].i2c_regs->ltiming, + (sample_div - 1) << 6 | (step_div - 1)); + + /* Init i2c bus clock_div register */ + write32(&mtk_i2c_bus_controller[bus].i2c_regs->clock_div, + clock_div - 1); + + /* Adjust tSU,STA/tHD,STA/tSU,STO */ + write32(&mtk_i2c_bus_controller[bus].i2c_regs->ext_conf, I2C_FS_START_CON); +} + +void mtk_i2c_bus_init(uint8_t bus) +{ + mtk_i2c_speed_init(bus); + mtk_i2c_set_gpio_pinmux(bus); +} diff --git a/src/soc/mediatek/mt8195/include/soc/i2c.h b/src/soc/mediatek/mt8195/include/soc/i2c.h new file mode 100644 index 0000000..977106e --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/i2c.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8195_I2C_H +#define SOC_MEDIATEK_MT8195_I2C_H + +#include <soc/i2c_common.h> + +/* I2C Register */ +struct mt_i2c_regs { + uint32_t data_port; + uint32_t slave_addr; + uint32_t intr_mask; + uint32_t intr_stat; + uint32_t control; + uint32_t transfer_len; + uint32_t transac_len; + uint32_t delay_len; + uint32_t timing; + uint32_t start; + uint32_t ext_conf; + uint32_t ltiming; + uint32_t hs; + uint32_t io_config; + uint32_t fifo_addr_clr; + uint32_t reserved0[2]; + uint32_t transfer_aux_len; + uint32_t clock_div; + uint32_t time_out; + uint32_t softreset; + uint32_t reserved1[36]; + uint32_t debug_stat; + uint32_t debug_ctrl; + uint32_t reserved2[2]; + uint32_t fifo_stat; + uint32_t fifo_thresh; + uint32_t reserved3[932]; + uint32_t multi_dma; + uint32_t reserved4[2]; + uint32_t rollback; +}; + +/* I2C ID Number*/ +enum { + I2C0, + I2C1, + I2C2, + I2C3, + I2C4, + I2C5, + I2C6, + I2C7, +}; + +check_member(mt_i2c_regs, multi_dma, 0xf8c); + +void mtk_i2c_bus_init(uint8_t bus); + +#endif /* SOC_MEDIATEK_MT8195_I2C_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/53894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia26e55512501e9758d7f5543d176730cf30ce03d Gerrit-Change-Number: 53894 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8195: Add mt6360 driver for LDO access
by Hung-Te Lin (Code Review) 10 May '21

10 May '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53893 ) Change subject: soc/mediatek/mt8195: Add mt6360 driver for LDO access ...................................................................... soc/mediatek/mt8195: Add mt6360 driver for LDO access Signed-off-by: Andrew SH Cheng <andrew-sh.cheng(a)mediatek.com> Change-Id: I68ca7067f76a67c4e797437593539f8f85909edc Reviewed-on: https://review.coreboot.org/c/coreboot/+/53893 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- A src/soc/mediatek/mt8195/include/soc/mt6360.h A src/soc/mediatek/mt8195/mt6360.c 2 files changed, 357 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8195/include/soc/mt6360.h b/src/soc/mediatek/mt8195/include/soc/mt6360.h new file mode 100644 index 0000000..3ac66fa --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/mt6360.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8195_MT6360_H__ +#define __SOC_MEDIATEK_MT8195_MT6360_H__ + +#include <stdint.h> + +enum mt6360_ldo_id { + MT6360_LDO1 = 0, + MT6360_LDO2, + MT6360_LDO3, + MT6360_LDO5, + MT6360_LDO_COUNT, +}; + +#define MT6360_LDO_I2C_ADDR 0x64 +#define MT6360_PMIC_I2C_ADDR 0x1A + +void mt6360_init(uint8_t bus); +void mt6360_ldo_enable(enum mt6360_ldo_id ldo_id, uint8_t enable); +uint8_t mt6360_ldo_is_enabled(enum mt6360_ldo_id ldo_id); +void mt6360_ldo_set_voltage(enum mt6360_ldo_id ldo_id, u32 voltage_uv); +u32 mt6360_ldo_get_voltage(enum mt6360_ldo_id ldo_id); +#endif diff --git a/src/soc/mediatek/mt8195/mt6360.c b/src/soc/mediatek/mt8195/mt6360.c new file mode 100644 index 0000000..9ca3b60 --- /dev/null +++ b/src/soc/mediatek/mt8195/mt6360.c @@ -0,0 +1,333 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/i2c_simple.h> +#include <soc/mt6360.h> +#include <stdbool.h> +#include <string.h> + +enum { + LDO_INDEX = 0, + PMIC_INDEX, +}; + +struct mt6360_i2c_data { + u8 bus; + u8 addr; +}; + +static struct mt6360_i2c_data i2c_data[] = { + [LDO_INDEX] = { + .addr = MT6360_LDO_I2C_ADDR, + }, + [PMIC_INDEX] = { + .addr = MT6360_PMIC_I2C_ADDR, + }, +}; + +static const uint32_t mt6360_ldo1_vsel_table[0x10] = { + [0x4] = 1800000, + [0x5] = 2000000, + [0x6] = 2100000, + [0x7] = 2500000, + [0x8] = 2700000, + [0x9] = 2800000, + [0xA] = 2900000, + [0xB] = 3000000, + [0xC] = 3100000, + [0xD] = 3300000, +}; + +static const uint32_t mt6360_ldo3_vsel_table[0x10] = { + [0x4] = 1800000, + [0xA] = 2900000, + [0xB] = 3000000, + [0xD] = 3300000, +}; + +static const uint32_t mt6360_ldo5_vsel_table[0x10] = { + [0x2] = 2900000, + [0x3] = 3000000, + [0x5] = 3300000, +}; + +struct mt6360_ldo_data { + uint8_t enable_reg; + uint8_t enable_mask; + uint8_t vsel_reg; + uint8_t vsel_mask; + const uint32_t *vsel_table; + uint32_t vsel_table_len; +}; + +#define MT6360_LDO_DATA(_enreg, _enmask, _vreg, _vmask, _table) \ +{ \ + .enable_reg = _enreg, \ + .enable_mask = _enmask, \ + .vsel_reg = _vreg, \ + .vsel_mask = _vmask, \ + .vsel_table = _table, \ + .vsel_table_len = ARRAY_SIZE(_table), \ +} + + +static const struct mt6360_ldo_data ldo_data[MT6360_LDO_COUNT] = { + [MT6360_LDO1] = MT6360_LDO_DATA(0x17, 0x40, 0x1B, 0xFF, mt6360_ldo1_vsel_table), + [MT6360_LDO2] = MT6360_LDO_DATA(0x11, 0x40, 0x15, 0xFF, mt6360_ldo1_vsel_table), + [MT6360_LDO3] = MT6360_LDO_DATA(0x05, 0x40, 0x09, 0xFF, mt6360_ldo3_vsel_table), + [MT6360_LDO5] = MT6360_LDO_DATA(0x0B, 0x40, 0x0F, 0xFF, mt6360_ldo5_vsel_table), +}; + +#define CRC8_TABLE_SIZE 256 +static u8 crc8_table[CRC8_TABLE_SIZE]; + +static u8 crc8(const u8 table[CRC8_TABLE_SIZE], u8 *pdata, size_t nbytes) +{ + u8 crc = 0; + + while (nbytes-- > 0) + crc = table[(crc ^ *pdata++) & 0xff]; + + return crc; +} + +static int mt6360_i2c_write_byte(struct mt6360_i2c_data *i2c, u8 reg, u8 data) +{ + u8 chunk[5] = { 0 }; + + if ((reg & 0xc0) != 0) { + printk(BIOS_ERR, "%s: not support reg [%#x]\n", __func__, reg); + return -1; + } + + /* + * chunk[0], dev address + * chunk[1], reg address + * chunk[2], data to write + * chunk[3], crc of chunk[0 ~ 2] + * chunk[4], blank + */ + chunk[0] = (i2c->addr & 0x7f) << 1; + chunk[1] = (reg & 0x3f); + chunk[2] = data; + chunk[3] = crc8(crc8_table, chunk, 3); + + return i2c_write_raw(i2c->bus, i2c->addr, &chunk[1], 4); +} + +static int mt6360_i2c_read_byte(struct mt6360_i2c_data *i2c, u8 reg, u8 *data) +{ + u8 chunk[4] = { 0 }; + u8 buf[2]; + int ret; + u8 crc; + + ret = i2c_read_bytes(i2c->bus, i2c->addr, reg & 0x3f, buf, 2); + + if (ret) + return ret; + /* + * chunk[0], dev address + * chunk[1], reg address + * chunk[2], received data + * chunk[3], received crc of chunk[0 ~ 2] + */ + chunk[0] = ((i2c->addr & 0x7f) << 1) + 1; + chunk[1] = (reg & 0x3f); + chunk[2] = buf[0]; + chunk[3] = buf[1]; + crc = crc8(crc8_table, chunk, 3); + + if (chunk[3] != crc) { + printk(BIOS_ERR, "%s: incorrect CRC: expected %#x, got %#x", + __func__, crc, chunk[3]); + return -1; + } + + *data = chunk[2]; + + return 0; +} + +static int mt6360_read_interface(u8 index, u8 reg, u8 *data, u8 mask, u8 shift) +{ + int ret; + u8 val = 0; + + ret = mt6360_i2c_read_byte(&i2c_data[index], reg, &val); + if (ret < 0) { + printk(BIOS_ERR, "%s: fail, reg = %#x, ret = %d\n", + __func__, reg, ret); + return ret; + } + val &= (mask << shift); + *data = (val >> shift); + return 0; +} + +static int mt6360_config_interface(u8 index, u8 reg, u8 data, u8 mask, u8 shift) +{ + int ret; + u8 val = 0; + + ret = mt6360_i2c_read_byte(&i2c_data[index], reg, &val); + if (ret < 0) { + printk(BIOS_ERR, "%s: fail, reg = %#x, ret = %d\n", + __func__, reg, ret); + return ret; + } + val &= ~(mask << shift); + val |= (data << shift); + + return mt6360_i2c_write_byte(&i2c_data[index], reg, val); +} + +static bool is_valid_ldo(enum mt6360_ldo_id id) +{ + if (id >= MT6360_LDO_COUNT) { + printk(BIOS_ERR, "%s: LDO %d is not supported\n", __func__, id); + return false; + } + + return true; +} + +void mt6360_ldo_enable(enum mt6360_ldo_id id, uint8_t enable) +{ + u8 val; + const struct mt6360_ldo_data *data; + + if (!is_valid_ldo(id)) + return; + + data = &ldo_data[id]; + + if (mt6360_read_interface(LDO_INDEX, data->enable_reg, &val, 0xFF, 0) < 0) + return; + + if (enable) + val |= data->enable_mask; + else + val &= ~(data->enable_mask); + + mt6360_config_interface(LDO_INDEX, data->enable_reg, val, 0xFF, 0); +} + +uint8_t mt6360_ldo_is_enabled(enum mt6360_ldo_id id) +{ + u8 val; + const struct mt6360_ldo_data *data; + + if (!is_valid_ldo(id)) + return 0; + + data = &ldo_data[id]; + + if (mt6360_read_interface(LDO_INDEX, data->enable_reg, &val, 0xFF, 0) < 0) + return 0; + + return (val & data->enable_mask) ? 1 : 0; +} + +void mt6360_ldo_set_voltage(enum mt6360_ldo_id id, u32 voltage_uv) +{ + u8 val = 0; + u32 voltage_uv_temp = 0; + int i; + + const struct mt6360_ldo_data *data; + + if (!is_valid_ldo(id)) + return; + + data = &ldo_data[id]; + + for (i = 0; i < data->vsel_table_len; i++) { + u32 uv = data->vsel_table[i]; + + if (uv == 0) + continue; + if (uv > voltage_uv) + break; + + val = i << 4; + voltage_uv_temp = voltage_uv - uv; + } + + if (val == 0) { + printk(BIOS_ERR, "%s: LDO %d, set %d uV not supported\n", + __func__, id, voltage_uv); + return; + } + + voltage_uv_temp /= 10000; + voltage_uv_temp = MIN(voltage_uv_temp, 0xA); + val |= (u8)voltage_uv_temp; + + mt6360_config_interface(LDO_INDEX, data->vsel_reg, val, 0xFF, 0); +} + +u32 mt6360_ldo_get_voltage(enum mt6360_ldo_id id) +{ + u8 val; + u32 voltage_uv; + + const struct mt6360_ldo_data *data; + + if (!is_valid_ldo(id)) + return 0; + + data = &ldo_data[id]; + + if (mt6360_read_interface(LDO_INDEX, data->vsel_reg, &val, 0xFF, 0) < 0) + return 0; + + voltage_uv = data->vsel_table[(val & 0xF0) >> 4]; + if (voltage_uv == 0) { + printk(BIOS_ERR, "%s: LDO %d read fail, reg = %#x\n", __func__, id, val); + return 0; + } + + val = MIN(val & 0x0F, 0x0A); + voltage_uv += val * 10000; + + return voltage_uv; +} + +static void crc8_populate_msb(u8 table[CRC8_TABLE_SIZE], u8 polynomial) +{ + int i, j; + const u8 msbit = 0x80; + u8 t = msbit; + + table[0] = 0; + + for (i = 1; i < CRC8_TABLE_SIZE; i *= 2) { + t = (t << 1) ^ (t & msbit ? polynomial : 0); + for (j = 0; j < i; j++) + table[i + j] = table[j] ^ t; + } +} + +void mt6360_init(uint8_t bus) +{ + u8 delay01, delay02, delay03, delay04; + + crc8_populate_msb(crc8_table, 0x7); + + i2c_data[LDO_INDEX].bus = bus; + i2c_data[PMIC_INDEX].bus = bus; + + mt6360_config_interface(PMIC_INDEX, 0x07, 0x04, 0xFF, 0); + mt6360_config_interface(PMIC_INDEX, 0x08, 0x00, 0xFF, 0); + mt6360_config_interface(PMIC_INDEX, 0x09, 0x02, 0xFF, 0); + mt6360_config_interface(PMIC_INDEX, 0x0A, 0x00, 0xFF, 0); + + mt6360_read_interface(PMIC_INDEX, 0x07, &delay01, 0xFF, 0); + mt6360_read_interface(PMIC_INDEX, 0x08, &delay02, 0xFF, 0); + mt6360_read_interface(PMIC_INDEX, 0x09, &delay03, 0xFF, 0); + mt6360_read_interface(PMIC_INDEX, 0x0A, &delay04, 0xFF, 0); + printk(BIOS_DEBUG, + "%s: power off sequence delay: %#x, %#x, %#x, %#x\n", + __func__, delay01, delay02, delay03, delay04); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/53893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68ca7067f76a67c4e797437593539f8f85909edc Gerrit-Change-Number: 53893 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Enable TCSS
by Deepti Deshatty (Code Review) 10 May '21

10 May '21

Attention is currently required from: Maulik V Vaghela. Deepti Deshatty has removed Tim Wawrzynczak from this change. ( https://review.coreboot.org/c/coreboot/+/54006 ) Change subject: mb/google/brya: Enable TCSS ...................................................................... Removed reviewer Tim Wawrzynczak. -- To view, visit https://review.coreboot.org/c/coreboot/+/54006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I794de3ecd5f4f18d6305fb9989a87af400b09d21 Gerrit-Change-Number: 54006 Gerrit-PatchSet: 1 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: deleteReviewer

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coreboot-gerrit May 2021