coreboot-gerrit May 2021

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Change in coreboot[master]: Revert "soc/amd/common/espi: Don't set alert pin in espi_set_initial_...
by Martin Roth (Code Review) 10 May '21

10 May '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53932 ) Change subject: Revert "soc/amd/common/espi: Don't set alert pin in espi_set_initial_config" ...................................................................... Revert "soc/amd/common/espi: Don't set alert pin in espi_set_initial_config" This reverts commit 6eced03b25954e370e20e62f2cbe41f9d5626eae. This prevents zork from booting. We get the following error: eSPI cmd0-cmd2: 00080009 00000000 00000000 data: 00000000. Error: unexpected eSPI status register bits set (Status = 0x10000010) Error: Slave GET_CONFIGURATION failed! This isn't a pure revert. It is more of a fix that keeps the old behavior. BUG=b:187122344 TEST=Boot zork an no longer see eSPI error Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: If75a35d3994b0fd23945a450032d3cc81abeb136 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53932 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 11 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 81056b0..276bb3c 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -883,6 +883,17 @@ { uint32_t espi_initial_mode = ESPI_OP_FREQ_16_MHZ | ESPI_IO_MODE_SINGLE; + switch (mb_cfg->alert_pin) { + case ESPI_ALERT_PIN_IN_BAND: + break; + case ESPI_ALERT_PIN_PUSH_PULL: + case ESPI_ALERT_PIN_OPEN_DRAIN: + espi_initial_mode |= ESPI_ALERT_MODE; + break; + default: + die("Unknown espi alert config: %u!\n", mb_cfg->alert_pin); + } + espi_write32(ESPI_SLAVE0_CONFIG, espi_initial_mode); } -- To view, visit https://review.coreboot.org/c/coreboot/+/53932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If75a35d3994b0fd23945a450032d3cc81abeb136 Gerrit-Change-Number: 53932 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: Force resets to be cold
by Martin Roth (Code Review) 10 May '21

10 May '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52982 ) Change subject: soc/amd/cezanne: Force resets to be cold ...................................................................... soc/amd/cezanne: Force resets to be cold Cezanne must use cold resets. Change the warm reset request to always set TOGGLE_ALL_PWR_GOOD. And, since the bit is sticky across power cycles, set it early for good measure. BUG=b:184281092 TEST=Majolica successfully resets using 0xcf9 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I7d4ca5665335b20100a5c802d12d79c0d0597ad9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52982 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/cezanne/fch.c M src/soc/amd/cezanne/reset.c 2 files changed, 10 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index 028ffec..f02d1ac 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -113,8 +113,14 @@ PM_ACPI_TIMER_EN_EN); } +static void fch_init_resets(void) +{ + pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); +} + void fch_init(void *chip_info) { + fch_init_resets(); i2c_soc_init(); fch_init_acpi_ports(); diff --git a/src/soc/amd/cezanne/reset.c b/src/soc/amd/cezanne/reset.c index aae76bf..d97f79e 100644 --- a/src/soc/amd/cezanne/reset.c +++ b/src/soc/amd/cezanne/reset.c @@ -7,6 +7,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/reset.h> +/* TODO: is NCP_ERR still valid? It appears reserved and always 0xff. b/184281092 */ void set_warm_reset_flag(void) { uint8_t ncp = inw(NCP_ERR); @@ -29,14 +30,13 @@ void do_warm_reset(void) { - set_warm_reset_flag(); - - /* Assert reset signals only. */ + /* Warm resets are not supported and must be executed as cold */ + pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | + TOGGLE_ALL_PWR_GOOD); outb(RST_CPU | SYS_RST, RST_CNT); } void do_board_reset(void) { - /* TODO: Would a warm_reset() suffice? */ do_cold_reset(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/52982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d4ca5665335b20100a5c802d12d79c0d0597ad9 Gerrit-Change-Number: 52982 Gerrit-PatchSet: 4 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: Force resets to be cold
by Martin Roth (Code Review) 10 May '21

10 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52982 ) Change subject: soc/amd/cezanne: Force resets to be cold ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d4ca5665335b20100a5c802d12d79c0d0597ad9 Gerrit-Change-Number: 52982 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 10 May 2021 04:14:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/mancomb: Fix TPM setting in devicetree
by Martin Roth (Code Review) 10 May '21

10 May '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53891 ) Change subject: mb/google/mancomb: Fix TPM setting in devicetree ...................................................................... mb/google/mancomb: Fix TPM setting in devicetree Fix I2C3 setting for TPM in devicetree. BUG=b:187341277 TEST=Build and boot into OS Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Change-Id: I728da76cee0c92c29df4c6ee8bfb4cd07a6366c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53891 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/mancomb/variants/baseboard/devicetree.cb 1 file changed, 9 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved EricR Lai: Looks good to me, approved diff --git a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb index 7ed9c1b..0ba1f6d 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb @@ -121,16 +121,17 @@ device pnp 0c09.0 on end end end - device ref i2c_3 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "desc" = ""Cr50 TPM"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)" - device i2c 50 on end - end - end end # domain + device ref i2c_3 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "desc" = ""Cr50 TPM"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)" + device i2c 50 on end + end + end + device ref uart_0 on end # UART0 end # chip soc/amd/cezanne -- To view, visit https://review.coreboot.org/c/coreboot/+/53891 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I728da76cee0c92c29df4c6ee8bfb4cd07a6366c4 Gerrit-Change-Number: 53891 Gerrit-PatchSet: 3 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: psp_verstage: remove not-implemented files for cezanne
by Martin Roth (Code Review) 10 May '21

10 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Kangheui Won, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53905 ) Change subject: psp_verstage: remove not-implemented files for cezanne ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/common/psp_verstage/Makefile.inc: https://review.coreboot.org/c/coreboot/+/53905/comment/af383a2b_a0f7289e PS1, Line 17: ifneq ($(CONFIG_SOC_AMD_CEZANNE),y) > I completely agree with the argument but this CL is only temporary, so I think moving files between […] Felix, I think it should be okay since it is temporary. Do you want a bug added to make sure it's fixed, or a TODO or are you okay with it as it is? These definitely need to be added back for full functionality, so I don't have any worries, but I want you to be good with it too. -- To view, visit https://review.coreboot.org/c/coreboot/+/53905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibaab4e8435624d403ef18e980146ebfd1598b61b Gerrit-Change-Number: 53905 Gerrit-PatchSet: 2 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 10 May 2021 04:12:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kangheui Won <khwon(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: psp_verstage: remove not-implemented files for cezanne
by Martin Roth (Code Review) 10 May '21

10 May '21

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Change in coreboot[master]: cezanne/psp_verstage: update SRAM address
by Martin Roth (Code Review) 10 May '21

10 May '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53904 ) Change subject: cezanne/psp_verstage: update SRAM address ...................................................................... cezanne/psp_verstage: update SRAM address Loading address and size for the user app has been changed with recent PSP release. Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: If247cdf3413c6a10f4b3c92fb7e43dd1057865d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53904 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/cezanne/include/soc/psp_verstage_addr.h 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h b/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h index bdc46cb..569d6e1 100644 --- a/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h +++ b/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h @@ -8,8 +8,8 @@ * header for the user app (verstage) must be mapped. * Size is 0x14000 bytes */ -#define PSP_SRAM_START 0x36000 -#define PSP_SRAM_SIZE (80K) +#define PSP_SRAM_START 0x26000 +#define PSP_SRAM_SIZE (148K) #define VERSTAGE_START PSP_SRAM_START /* @@ -17,7 +17,7 @@ * and make the size a multiple of 4k */ -#define PSP_VERSTAGE_STACK_START 0x49000 -#define PSP_VERSTAGE_STACK_SIZE (4K) +#define PSP_VERSTAGE_STACK_START 0x41000 +#define PSP_VERSTAGE_STACK_SIZE (40K) #endif /* AMD_CEZANNE_PSP_VERSTAGE_ADDR_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/53904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If247cdf3413c6a10f4b3c92fb7e43dd1057865d9 Gerrit-Change-Number: 53904 Gerrit-PatchSet: 2 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: amd/cezanne: verify transfer buffer in bootblock
by Martin Roth (Code Review) 10 May '21

10 May '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52965 ) Change subject: amd/cezanne: verify transfer buffer in bootblock ...................................................................... amd/cezanne: verify transfer buffer in bootblock Verify if transfer buffer is valid before progressing further to catch invalid transfer buffer early. Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: I4c470b156944b50e581dcdee47b196f46b0993f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52965 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/bootblock.c 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/bootblock.c b/src/soc/amd/cezanne/bootblock.c index 2447de6..21635c9 100644 --- a/src/soc/amd/cezanne/bootblock.c +++ b/src/soc/amd/cezanne/bootblock.c @@ -11,6 +11,7 @@ #include <cpu/x86/tsc.h> #include <soc/iomap.h> #include <soc/southbridge.h> +#include <soc/psp_transfer.h> #include <stdint.h> /* @@ -110,5 +111,11 @@ { u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val); + + if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { + verify_psp_transfer_buf(); + show_psp_transfer_info(); + } + fch_early_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/52965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c470b156944b50e581dcdee47b196f46b0993f3 Gerrit-Change-Number: 52965 Gerrit-PatchSet: 5 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: psp_verstage: differentiate bios entry
by Martin Roth (Code Review) 10 May '21

10 May '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52964 ) Change subject: psp_verstage: differentiate bios entry ...................................................................... psp_verstage: differentiate bios entry AMDFW tool stores bios dir entry to bios1_entry in picasso but bios3_entry in cezanne. Separate getting bios_dir_addr into a function and implement it on each platforms. Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Ie18ed7979a04319c074b9b251130d419dc7f22dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52964 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/psp_verstage/chipset.c M src/soc/amd/common/psp_verstage/include/psp_verstage.h M src/soc/amd/common/psp_verstage/psp_verstage.c M src/soc/amd/picasso/psp_verstage/chipset.c 4 files changed, 14 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/cezanne/psp_verstage/chipset.c b/src/soc/amd/cezanne/psp_verstage/chipset.c index 7f944eb..c0593bf 100644 --- a/src/soc/amd/cezanne/psp_verstage/chipset.c +++ b/src/soc/amd/cezanne/psp_verstage/chipset.c @@ -21,6 +21,11 @@ return svc_save_uapp_data(address, size); } +uint32_t get_bios_dir_addr(struct psp_ef_table *ef_table) +{ + return ef_table->bios3_entry; +} + /* Functions below are stub functions for not-yet-implemented PSP features. * These functions should be replaced with proper implementations later. diff --git a/src/soc/amd/common/psp_verstage/include/psp_verstage.h b/src/soc/amd/common/psp_verstage/include/psp_verstage.h index 6589725..7bfc8b7 100644 --- a/src/soc/amd/common/psp_verstage/include/psp_verstage.h +++ b/src/soc/amd/common/psp_verstage/include/psp_verstage.h @@ -48,6 +48,8 @@ uint32_t bios0_entry; uint32_t bios1_entry; uint32_t bios2_entry; + uint32_t reserved1; + uint32_t bios3_entry; } __attribute__((packed, aligned(16))); void test_svc_calls(void); @@ -59,5 +61,6 @@ uint32_t get_max_workbuf_size(uint32_t *size); uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset); uint32_t save_uapp_data(void *address, uint32_t size); +uint32_t get_bios_dir_addr(struct psp_ef_table *ef_table); #endif /* PSP_VERSTAGE_H */ diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index f6cc5e9..2265e17 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -107,7 +107,7 @@ } psp_dir_addr = ef_table->psp_table; - bios_dir_addr = ef_table->bios1_entry; + bios_dir_addr = get_bios_dir_addr(ef_table); psp_dir_in_spi = (uint32_t *)((psp_dir_addr & SPI_ADDR_MASK) + (uint32_t)boot_dev.base); bios_dir_in_spi = (uint32_t *)((bios_dir_addr & SPI_ADDR_MASK) + diff --git a/src/soc/amd/picasso/psp_verstage/chipset.c b/src/soc/amd/picasso/psp_verstage/chipset.c index 57a2ff3..b7acbcd 100644 --- a/src/soc/amd/picasso/psp_verstage/chipset.c +++ b/src/soc/amd/picasso/psp_verstage/chipset.c @@ -18,3 +18,8 @@ { return svc_get_max_workbuf_size(size); } + +uint32_t get_bios_dir_addr(struct psp_ef_table *ef_table) +{ + return ef_table->bios1_entry; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/52964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie18ed7979a04319c074b9b251130d419dc7f22dc Gerrit-Change-Number: 52964 Gerrit-PatchSet: 5 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: psp_verstage: differentiate bios entry
by Martin Roth (Code Review) 10 May '21

10 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Kangheui Won, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52964 ) Change subject: psp_verstage: differentiate bios entry ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie18ed7979a04319c074b9b251130d419dc7f22dc Gerrit-Change-Number: 52964 Gerrit-PatchSet: 4 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 10 May 2021 04:07:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit May 2021