coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/kukui: Add discrete EMCP LPDDR4X table for Kakadu/Katsu
by Sunwei Li (Code Review) 10 May '21

10 May '21

Sunwei Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54009 ) Change subject: mb/google/kukui: Add discrete EMCP LPDDR4X table for Kakadu/Katsu ...................................................................... mb/google/kukui: Add discrete EMCP LPDDR4X table for Kakadu/Katsu Add EMCP LPDDR4X DDR FEPRF6432-58A1930 for ram id 9. BUG=b:186141919 BRANCH=kukui TEST=New Emcp can boot normally on kakadu/katsu Signed-off-by: Sunway <lisunwei(a)huaqin.corp-partner.google.com> Change-Id: Ieaf05a0a7b0c0671c07b0df29319ebd91fe63e57 --- M src/mainboard/google/kukui/sdram_configs.c M src/mainboard/google/kukui/sdram_params/Makefile.inc A src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-FEPRF6432-58A1930-4GB.c 3 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/54009/1 diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c index 9eb04fe..040810e 100644 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -45,6 +45,7 @@ [0x26] = "sdram-lpddr4x-KMDV6001DA-B620-4GB", [0x27] = "sdram-lpddr4x-SDADA4CR-128G-4GB", [0x28] = "sdram-lpddr4x-MT29VZZZCD9GQKPR-046-8GB", + [0x29] = "sdram-lpddr4x-FEPRF6432-58A1930-4GB", /* Table shared by Cozmo and its variants, offset = 0x30 */ [0x30] = "sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB", diff --git a/src/mainboard/google/kukui/sdram_params/Makefile.inc b/src/mainboard/google/kukui/sdram_params/Makefile.inc index 4117bf2..cb8f427 100644 --- a/src/mainboard/google/kukui/sdram_params/Makefile.inc +++ b/src/mainboard/google/kukui/sdram_params/Makefile.inc @@ -14,6 +14,7 @@ sdram-params += sdram-lpddr4x-MT53E1G32D2NP-046-4GB sdram-params += sdram-lpddr4x-MT29VZZZCD9GQKPR-046-8GB sdram-params += sdram-lpddr4x-MT29VZZZAD9GQFSM-046-4GB +sdram-params += sdram-lpddr4x-FEPRF6432-58A1930-4GB $(foreach params,$(sdram-params), \ $(eval cbfs-files-y += $(params)) \ diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-FEPRF6432-58A1930-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-FEPRF6432-58A1930-4GB.c new file mode 100644 index 0000000..86c3e8f --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-FEPRF6432-58A1930-4GB.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_param.h> + +struct sdram_params params = { + .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .frequency = 1600, + .rank_num = 1, + .ddr_geometry = DDR_TYPE_2CH_1RK_4GB_4, + .wr_level = { + [CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} }, + [CHANNEL_B] = { {0x22, 0x1E}, {0x22, 0x1E} } + }, + .cbt_cs_dly = { + [CHANNEL_A] = {0x5, 0x4}, + [CHANNEL_B] = {0x8, 0x8} + }, + .cbt_final_vref = { + [CHANNEL_A] = {0x56, 0x56}, + [CHANNEL_B] = {0x56, 0x56} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_NORMAL_MODE, + .delay_cell_unit = 868, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/54009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaf05a0a7b0c0671c07b0df29319ebd91fe63e57 Gerrit-Change-Number: 54009 Gerrit-PatchSet: 1 Gerrit-Owner: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/adl: Allow mainboard to fill CmdMirror and DqDqsRetraining
by Werner Zeh (Code Review) 10 May '21

10 May '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51027 ) Change subject: soc/intel/adl: Allow mainboard to fill CmdMirror and DqDqsRetraining ...................................................................... soc/intel/adl: Allow mainboard to fill CmdMirror and DqDqsRetraining We need to modify update CmdMirror and LpDdrDqDqsRetraining parameters for ADLRVP board. Allowing this parameters to be filled by devicetree will allow flexibility to update values as per board designs. Note that both UPDs are applicable for both DDR and Lpddr memory types. BUG=None BRANCH=None TEST=Build works and UPD values have been filled correctly Change-Id: I55b4b4aee46231c8c38e208c357b4376ecf6e9d9 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51027 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/include/soc/meminit.h M src/soc/intel/alderlake/meminit.c 2 files changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h index 96e049c..49e3c76 100644 --- a/src/soc/intel/alderlake/include/soc/meminit.h +++ b/src/soc/intel/alderlake/include/soc/meminit.h @@ -103,6 +103,12 @@ /* Board type */ uint8_t UserBd; + + /* Command Mirror */ + uint8_t CmdMirror; + + /* Enable/Disable TxDqDqs Retraining for Lp4/Lp5/DDR */ + uint8_t LpDdrDqDqsReTraining; }; void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index 48d3386..33f26da 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -226,6 +226,12 @@ mem_cfg->UserBd = mb_cfg->UserBd; set_rcomp_config(mem_cfg, mb_cfg); + /* Fill command mirror for memory */ + mem_cfg->CmdMirror = mb_cfg->CmdMirror; + + /* Fill LpDdrrDqDqs Retraining for memory */ + mem_cfg->LpDdrDqDqsReTraining = mb_cfg->LpDdrDqDqsReTraining; + switch (mb_cfg->type) { case MEM_TYPE_DDR4: case MEM_TYPE_DDR5: -- To view, visit https://review.coreboot.org/c/coreboot/+/51027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55b4b4aee46231c8c38e208c357b4376ecf6e9d9 Gerrit-Change-Number: 51027 Gerrit-PatchSet: 6 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-CC: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: TEST-ONLY: vendorcode/mediatek/mt8192: force use 0.6875mV(SHU1) for 3...
by Xi Chen (Code Review) 10 May '21

10 May '21

Xi Chen has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52966 ) Change subject: TEST-ONLY: vendorcode/mediatek/mt8192: force use 0.6875mV(SHU1) for 3200Mbps ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/52966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50d20f66b03506817ba1ab7a55e2f1a516ad5559 Gerrit-Change-Number: 52966 Gerrit-PatchSet: 1 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: TEST-ONLY: vendorcode/mediatek/mt8192: adjust SHU sequence as blob se...
by Xi Chen (Code Review) 10 May '21

10 May '21

Xi Chen has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/53906 ) Change subject: TEST-ONLY: vendorcode/mediatek/mt8192: adjust SHU sequence as blob sequence ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/53906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0812cc724972910ab531e7e77400d8f52924d02 Gerrit-Change-Number: 53906 Gerrit-PatchSet: 1 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/mediatek/mt8195: Enable and initialize eint
by Rex-BC Chen (Code Review) 10 May '21

10 May '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu, Yidi Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54007 ) Change subject: soc/mediatek/mt8195: Enable and initialize eint ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54007/comment/61c66309_2430a849 PS1, Line 8: > Please elaborate, and summarize what eint does, and how it’s been tested. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/54007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I703d87e3dc49cf4e0b7ff0c75a6ea80245dd73d3 Gerrit-Change-Number: 54007 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 10 May 2021 05:55:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: DO-NOT-SUBMIT: MT8195 Cherry review ToT
by Rex-BC Chen (Code Review) 10 May '21

10 May '21

Attention is currently required from: Rex-BC Chen, Yidi Lin. Rex-BC Chen has uploaded a new patch set (#61) to the change originally created by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/52260 ) Change subject: DO-NOT-SUBMIT: MT8195 Cherry review ToT ...................................................................... DO-NOT-SUBMIT: MT8195 Cherry review ToT Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: I3ed96b245bbb52501e9b7d6b89ed42468f505ab0 --- M 3rdparty/amd_blobs M 3rdparty/blobs M 3rdparty/intel-microcode M 3rdparty/qc_blobs M README.md 5 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/52260/61 -- To view, visit https://review.coreboot.org/c/coreboot/+/52260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ed96b245bbb52501e9b7d6b89ed42468f505ab0 Gerrit-Change-Number: 52260 Gerrit-PatchSet: 61 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8195: Enable and initialize eint
by Rex-BC Chen (Code Review) 10 May '21

10 May '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu, Yidi Lin. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54007 to look at the new patch set (#2). Change subject: soc/mediatek/mt8195: Enable and initialize eint ...................................................................... soc/mediatek/mt8195: Enable and initialize eint eint event mask register is used to mask eint wakeup source. All wakeup sources are masked by default. Since most MediaTek SoCs do not have this design, we can't modify the kernel eint upstream driver to solve the issue 'Can't wake using power button (cros_ec) or touchpad'. So we add a driver here to unmask all wakeup sources. Change-Id: I703d87e3dc49cf4e0b7ff0c75a6ea80245dd73d3 Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> --- M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/bootblock.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/54007/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I703d87e3dc49cf4e0b7ff0c75a6ea80245dd73d3 Gerrit-Change-Number: 54007 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: doc/releases/coreboot-4.14: Add x86 bootblock and ACPI GNVS changes
by Werner Zeh (Code Review) 10 May '21

10 May '21

Attention is currently required from: Angel Pons, Kyösti Mälkki. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54008 ) Change subject: doc/releases/coreboot-4.14: Add x86 bootblock and ACPI GNVS changes ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa58a9ac7c6dcc391cd9942295319a8677cd4492 Gerrit-Change-Number: 54008 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Mon, 10 May 2021 05:46:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: enable ARM64_USE_ARM_TRUSTED_FIRMWARE
by Paul Menzel (Code Review) 10 May '21

10 May '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53898 ) Change subject: soc/mediatek/mt8195: enable ARM64_USE_ARM_TRUSTED_FIRMWARE ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/53898/comment/20bbd802_0995c150 PS3, Line 9: Enable ATF support. > … to support multiple cores? Is that the problem to be fixed? https://review.coreboot.org/c/coreboot/+/53898/comment/35204ded_75170924 PS3, Line 12: No bug entry? -- To view, visit https://review.coreboot.org/c/coreboot/+/53898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1ef29894fa3a6022574c3874dee62617133b12c Gerrit-Change-Number: 53898 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Mon, 10 May 2021 05:35:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Enable and initialize eint
by Paul Menzel (Code Review) 10 May '21

10 May '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu, Yidi Lin. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54007 ) Change subject: soc/mediatek/mt8195: Enable and initialize eint ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54007/comment/45eeadd6_5dae4963 PS1, Line 8: Please elaborate, and summarize what eint does, and how it’s been tested. -- To view, visit https://review.coreboot.org/c/coreboot/+/54007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I703d87e3dc49cf4e0b7ff0c75a6ea80245dd73d3 Gerrit-Change-Number: 54007 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 10 May 2021 05:29:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2021