coreboot-gerrit May 2021

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Change in coreboot[master]: psp_verstage: move platform-specific code to chipset.c
by Martin Roth (Code Review) 10 May '21

10 May '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52963 ) Change subject: psp_verstage: move platform-specific code to chipset.c ...................................................................... psp_verstage: move platform-specific code to chipset.c Move all platform-specific code except direct svc calls to chipset.c. There will be differences between each platforms and we can't put everything into svc.c. TEST=build firmware for zork Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Ie7a71d1632800072a17c26591e13e09e0269cf75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52963 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/psp_verstage/Makefile.inc R src/soc/amd/cezanne/psp_verstage/chipset.c M src/soc/amd/cezanne/psp_verstage/svc.c M src/soc/amd/picasso/psp_verstage/Makefile.inc A src/soc/amd/picasso/psp_verstage/chipset.c M src/soc/amd/picasso/psp_verstage/svc.c 6 files changed, 37 insertions(+), 27 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/cezanne/psp_verstage/Makefile.inc b/src/soc/amd/cezanne/psp_verstage/Makefile.inc index 3f92433..ea9353d 100644 --- a/src/soc/amd/cezanne/psp_verstage/Makefile.inc +++ b/src/soc/amd/cezanne/psp_verstage/Makefile.inc @@ -8,7 +8,7 @@ subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage verstage-y += svc.c -verstage-y += stub.c +verstage-y += chipset.c verstage-y += $(top)/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_startup.S verstage-y += $(top)/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_end.S diff --git a/src/soc/amd/cezanne/psp_verstage/stub.c b/src/soc/amd/cezanne/psp_verstage/chipset.c similarity index 61% rename from src/soc/amd/cezanne/psp_verstage/stub.c rename to src/soc/amd/cezanne/psp_verstage/chipset.c index b3ec704..7f944eb 100644 --- a/src/soc/amd/cezanne/psp_verstage/stub.c +++ b/src/soc/amd/cezanne/psp_verstage/chipset.c @@ -11,6 +11,21 @@ #include <reset.h> #include <timer.h> +uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset) +{ + return svc_update_psp_bios_dir(psp_dir_offset, bios_dir_offset); +} + +uint32_t save_uapp_data(void *address, uint32_t size) +{ + return svc_save_uapp_data(address, size); +} + + +/* Functions below are stub functions for not-yet-implemented PSP features. + * These functions should be replaced with proper implementations later. + */ + uint32_t svc_write_postcode(uint32_t postcode) { return 0; diff --git a/src/soc/amd/cezanne/psp_verstage/svc.c b/src/soc/amd/cezanne/psp_verstage/svc.c index 3d10c22..70cb369 100644 --- a/src/soc/amd/cezanne/psp_verstage/svc.c +++ b/src/soc/amd/cezanne/psp_verstage/svc.c @@ -82,11 +82,6 @@ return retval; } -uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset) -{ - return svc_update_psp_bios_dir(psp_dir_offset, bios_dir_offset); -} - uint32_t svc_update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset) { @@ -96,11 +91,6 @@ return retval; } -uint32_t save_uapp_data(void *address, uint32_t size) -{ - return svc_save_uapp_data(address, size); -} - uint32_t svc_save_uapp_data(void *address, uint32_t size) { uint32_t retval = 0; diff --git a/src/soc/amd/picasso/psp_verstage/Makefile.inc b/src/soc/amd/picasso/psp_verstage/Makefile.inc index 32b594d..41296c9 100644 --- a/src/soc/amd/picasso/psp_verstage/Makefile.inc +++ b/src/soc/amd/picasso/psp_verstage/Makefile.inc @@ -4,6 +4,7 @@ verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/picasso/include verstage-y += svc.c +verstage-y += chipset.c verstage-y += $(top)/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S verstage-y += $(top)/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_end.S diff --git a/src/soc/amd/picasso/psp_verstage/chipset.c b/src/soc/amd/picasso/psp_verstage/chipset.c new file mode 100644 index 0000000..57a2ff3 --- /dev/null +++ b/src/soc/amd/picasso/psp_verstage/chipset.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bl_uapp/bl_syscall_public.h> +#include <psp_verstage.h> + +uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset) +{ + return svc_update_psp_bios_dir(psp_dir_offset, bios_dir_offset, + DIR_OFFSET_SET); +} + +uint32_t save_uapp_data(void *address, uint32_t size) +{ + return svc_save_uapp_data(UAPP_COPYBUF_CHROME_WORKBUF, address, size); +} + +uint32_t get_max_workbuf_size(uint32_t *size) +{ + return svc_get_max_workbuf_size(size); +} diff --git a/src/soc/amd/picasso/psp_verstage/svc.c b/src/soc/amd/picasso/psp_verstage/svc.c index 28e6baf..d94ec76 100644 --- a/src/soc/amd/picasso/psp_verstage/svc.c +++ b/src/soc/amd/picasso/psp_verstage/svc.c @@ -96,12 +96,6 @@ return retval; } -uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset) -{ - return svc_update_psp_bios_dir(psp_dir_offset, bios_dir_offset, - DIR_OFFSET_SET); -} - uint32_t svc_update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset, enum dir_offset_operation operation) { @@ -112,11 +106,6 @@ return retval; } -uint32_t save_uapp_data(void *address, uint32_t size) -{ - return svc_save_uapp_data(UAPP_COPYBUF_CHROME_WORKBUF, address, size); -} - uint32_t svc_save_uapp_data(enum uapp_copybuf type, void *address, uint32_t size) { @@ -149,11 +138,6 @@ return retval; } -uint32_t get_max_workbuf_size(uint32_t *size) -{ - return svc_get_max_workbuf_size(size); -} - uint32_t svc_get_max_workbuf_size(uint32_t *size) { uint32_t retval = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/52963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7a71d1632800072a17c26591e13e09e0269cf75 Gerrit-Change-Number: 52963 Gerrit-PatchSet: 5 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: psp_verstage: move platform-specific code to chipset.c
by Martin Roth (Code Review) 10 May '21

10 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Kangheui Won, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52963 ) Change subject: psp_verstage: move platform-specific code to chipset.c ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7a71d1632800072a17c26591e13e09e0269cf75 Gerrit-Change-Number: 52963 Gerrit-PatchSet: 4 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 10 May 2021 04:04:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cezanne/psp_verstage: clean up duplicated target
by Martin Roth (Code Review) 10 May '21

10 May '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52962 ) Change subject: cezanne/psp_verstage: clean up duplicated target ...................................................................... cezanne/psp_verstage: clean up duplicated target psp_verstage.bin target is already defined at common/psp_verstage/Makefile.inc, thus removing it here. Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Ica4b09282d1c4cfc555c18ba50951458b8580826 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52962 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/psp_verstage/Makefile.inc 1 file changed, 0 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/cezanne/psp_verstage/Makefile.inc b/src/soc/amd/cezanne/psp_verstage/Makefile.inc index 8f268ca..3f92433 100644 --- a/src/soc/amd/cezanne/psp_verstage/Makefile.inc +++ b/src/soc/amd/cezanne/psp_verstage/Makefile.inc @@ -12,6 +12,3 @@ verstage-y += $(top)/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_startup.S verstage-y += $(top)/src/vendorcode/amd/fsp/cezanne/bl_uapp/bl_uapp_end.S - -$(obj)/psp_verstage.bin: $(objcbfs)/verstage.elf - $(OBJCOPY_verstage) -O binary $^ $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/52962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica4b09282d1c4cfc555c18ba50951458b8580826 Gerrit-Change-Number: 52962 Gerrit-PatchSet: 5 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cezanne/psp_verstage: populate a/b firmware
by Martin Roth (Code Review) 10 May '21

10 May '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52961 ) Change subject: cezanne/psp_verstage: populate a/b firmware ...................................................................... cezanne/psp_verstage: populate a/b firmware Build amdfw_[ab] and put them into CBFS. We can reuse FW_[AB] position from zork since we have same flash layout and size. Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Idb31afa7a513f01593b2af75515a170dfca8d360 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52961 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc 2 files changed, 63 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index dafc26f..51bc4bc 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -416,4 +416,22 @@ This is the byte before the default first byte used by VBNV (0x26 + 0x0E - 1) +if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + +config RWA_REGION_ONLY + string + default "apu/amdfw_a" + help + Add a space-delimited list of filenames that should only be in the + RW-A section. + +config RWB_REGION_ONLY + string + default "apu/amdfw_b" + help + Add a space-delimited list of filenames that should only be in the + RW-B section. + +endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + endif # SOC_AMD_CEZANNE diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index ebdad45..7053960 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -73,6 +73,14 @@ $(call int-subtract, 0xffffffff \ $(call int-shift-left, \ 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) + +CEZANNE_FW_A_POSITION=$(call int-add, \ + $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_A_START" {print $$3}' $(obj)/fmap_config.h) \ + 0x40) + +CEZANNE_FW_B_POSITION=$(call int-add, \ + $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_B_START" {print $$3}' $(obj)/fmap_config.h) \ + 0x40) # # PSP Directory Table items # @@ -234,11 +242,48 @@ $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ --maxsize $(PSP_BIOSBIN_SIZE) +$(obj)/amdfw_a.rom: $(obj)/amdfw.rom + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ + --location $(shell printf "%#x" $(CEZANNE_FW_A_POSITION)) \ + --anywhere \ + --multilevel \ + --output $@ + +$(obj)/amdfw_b.rom: $(obj)/amdfw.rom + rm -f $@ + @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + $(AMDFWTOOL) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ + --location $(shell printf "%#x" $(CEZANNE_FW_B_POSITION)) \ + --anywhere \ + --multilevel \ + --output $@ + + cbfs-files-y += apu/amdfw apu/amdfw-file := $(obj)/amdfw.rom apu/amdfw-position := $(CEZANNE_FWM_POSITION) apu/amdfw-type := raw +ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) +cbfs-files-y += apu/amdfw_a +apu/amdfw_a-file := $(obj)/amdfw_a.rom +apu/amdfw_a-position := $(call strip_quotes, $(CEZANNE_FW_A_POSITION)) +apu/amdfw_a-type := raw + +cbfs-files-y += apu/amdfw_b +apu/amdfw_b-file := $(obj)/amdfw_b.rom +apu/amdfw_b-position := $(call strip_quotes, $(CEZANNE_FW_B_POSITION)) +apu/amdfw_b-type := raw +endif + cpu_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/UcodePatch_*.bin) endif # ($(CONFIG_SOC_AMD_CEZANNE),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/52961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb31afa7a513f01593b2af75515a170dfca8d360 Gerrit-Change-Number: 52961 Gerrit-PatchSet: 5 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: merged

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Change in coreboot[master]: cezanne/psp_verstage: populate a/b firmware
by Martin Roth (Code Review) 10 May '21

10 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Kangheui Won, Arthur Heymans, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52961 ) Change subject: cezanne/psp_verstage: populate a/b firmware ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb31afa7a513f01593b2af75515a170dfca8d360 Gerrit-Change-Number: 52961 Gerrit-PatchSet: 4 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 10 May 2021 04:03:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Enable GFX HDA device
by Martin Roth (Code Review) 10 May '21

10 May '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52974 ) Change subject: mb/google/guybrush: Enable GFX HDA device ...................................................................... mb/google/guybrush: Enable GFX HDA device Enable Display Controller Engine Audio endpoint to enable HDMI audio. BUG=b:186479763 TEST=Build and boot to OS in guybrush. Change-Id: I5e35440e8e70ee125d37c7ac30c9219ec69c7c6e Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52974 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 88a0a1c..1d01fff 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -60,6 +60,7 @@ device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) + device ref gfx_hda on end # GFX HD Audio Controller device ref xhci_0 on # USB 3.1 (USB0) chip drivers/usb/acpi device ref xhci_0_root_hub on -- To view, visit https://review.coreboot.org/c/coreboot/+/52974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e35440e8e70ee125d37c7ac30c9219ec69c7c6e Gerrit-Change-Number: 52974 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Enable PP5000_PEN
by Martin Roth (Code Review) 10 May '21

10 May '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53943 ) Change subject: mb/google/guybrush: Enable PP5000_PEN ...................................................................... mb/google/guybrush: Enable PP5000_PEN Everybody wants a stylish stylus. Enable the power system to it. BUG=b:186267293 TEST=connect multimeter to PP5000_PEN and see it go from 0 to 1. MAGIC! Signed-off-by: Eric Peers <epeers(a)google.com> Change-Id: I11d05c118ec9451d26136c320f3650c489e02c59 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53943 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 336fd62..c89ded2 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -19,7 +19,7 @@ /* SOC_PEN_DETECT_ODL */ PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S0i3), /* EN_PP5000_PEN */ - PAD_GPO(GPIO_5, LOW), + PAD_GPO(GPIO_5, HIGH), /* EN_PP3300_WLAN */ PAD_GPO(GPIO_6, HIGH), /* EN_PP3300_TCHPAD */ -- To view, visit https://review.coreboot.org/c/coreboot/+/53943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11d05c118ec9451d26136c320f3650c489e02c59 Gerrit-Change-Number: 53943 Gerrit-PatchSet: 2 Gerrit-Owner: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Enable PP5000_PEN
by Martin Roth (Code Review) 10 May '21

10 May '21

Attention is currently required from: Raul Rangel, Marshall Dawson, Eric Peers, Karthik Ramasubramanian. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53943 ) Change subject: mb/google/guybrush: Enable PP5000_PEN ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/53943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11d05c118ec9451d26136c320f3650c489e02c59 Gerrit-Change-Number: 53943 Gerrit-PatchSet: 1 Gerrit-Owner: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 10 May 2021 04:00:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Enable and initialize eint
by Rex-BC Chen (Code Review) 10 May '21

10 May '21

Attention is currently required from: Yidi Lin. Hello Yidi Lin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/54007 to review the following change. Change subject: soc/mediatek/mt8195: Enable and initialize eint ...................................................................... soc/mediatek/mt8195: Enable and initialize eint Change-Id: I703d87e3dc49cf4e0b7ff0c75a6ea80245dd73d3 Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> --- M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/bootblock.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/54007/1 diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 514acbd..88cb070 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -1,6 +1,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8195),y) bootblock-y += bootblock.c +bootblock-y += ../common/eint_event.c bootblock-y += ../common/flash_controller.c bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/i2c.c i2c.c diff --git a/src/soc/mediatek/mt8195/bootblock.c b/src/soc/mediatek/mt8195/bootblock.c index 8dffe56..17fd27e 100644 --- a/src/soc/mediatek/mt8195/bootblock.c +++ b/src/soc/mediatek/mt8195/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <soc/eint_event.h> #include <soc/mmu_operations.h> #include <soc/pll.h> #include <soc/wdt.h> @@ -10,4 +11,5 @@ mtk_mmu_init(); mtk_wdt_init(); mt_pll_init(); + unmask_eint_event_mask(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/54007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I703d87e3dc49cf4e0b7ff0c75a6ea80245dd73d3 Gerrit-Change-Number: 54007 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8195: enable ARM64_USE_ARM_TRUSTED_FIRMWARE
by Rex-BC Chen (Code Review) 10 May '21

10 May '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53898 ) Change subject: soc/mediatek/mt8195: enable ARM64_USE_ARM_TRUSTED_FIRMWARE ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > before atf upstream is updated, can you temporarily remove this from review tree so we can have the […] I move this patch ouside TOT. -- To view, visit https://review.coreboot.org/c/coreboot/+/53898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1ef29894fa3a6022574c3874dee62617133b12c Gerrit-Change-Number: 53898 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Mon, 10 May 2021 02:39:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit May 2021