coreboot-gerrit May 2021

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Change in coreboot[master]: mb/google/cherry: Configure TPM
by Hung-Te Lin (Code Review) 10 May '21

10 May '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53900 ) Change subject: mb/google/cherry: Configure TPM ...................................................................... mb/google/cherry: Configure TPM Change-Id: I1d6ecdb31eef65d2e96d9251348390aa8598be6c Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53900 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/cherry/Kconfig M src/mainboard/google/cherry/bootblock.c M src/mainboard/google/cherry/chromeos.c 3 files changed, 19 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/cherry/Kconfig b/src/mainboard/google/cherry/Kconfig index b9c63ea..7377c6c 100644 --- a/src/mainboard/google/cherry/Kconfig +++ b/src/mainboard/google/cherry/Kconfig @@ -22,6 +22,8 @@ select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_SPI + select MAINBOARD_HAS_I2C_TPM_CR50 if VBOOT + select MAINBOARD_HAS_TPM2 if VBOOT config MAINBOARD_DIR string @@ -31,6 +33,14 @@ string default "Cherry" if BOARD_GOOGLE_CHERRY +config DRIVER_TPM_I2C_BUS + hex + default 0x3 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x50 + # On MT8195 the SPI flash is actually using a SPI-NOR controller with its own bus. # The number here should be a virtual value as (SPI_BUS_NUMBER + 1). config BOOT_DEVICE_SPI_FLASH_BUS diff --git a/src/mainboard/google/cherry/bootblock.c b/src/mainboard/google/cherry/bootblock.c index dbc6c26..93f0bce 100644 --- a/src/mainboard/google/cherry/bootblock.c +++ b/src/mainboard/google/cherry/bootblock.c @@ -3,6 +3,7 @@ #include <bootblock_common.h> #include <device/mmio.h> #include <soc/gpio.h> +#include <soc/i2c.h> #include <soc/spi.h> #include "gpio.h" @@ -36,7 +37,9 @@ void bootblock_mainboard_init(void) { + mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS); mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0); nor_set_gpio_pinmux(); setup_chromeos_gpios(); + gpio_eint_configure(GPIO_GSC_AP_INT, IRQ_TYPE_EDGE_RISING); } diff --git a/src/mainboard/google/cherry/chromeos.c b/src/mainboard/google/cherry/chromeos.c index 1a869a3..03e44d5 100644 --- a/src/mainboard/google/cherry/chromeos.c +++ b/src/mainboard/google/cherry/chromeos.c @@ -3,6 +3,7 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <gpio.h> +#include <security/tpm/tis.h> #include "gpio.h" @@ -28,3 +29,8 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } + +int tis_plat_irq_status(void) +{ + return gpio_eint_poll(GPIO_GSC_AP_INT); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/53900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d6ecdb31eef65d2e96d9251348390aa8598be6c Gerrit-Change-Number: 53900 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/cherry: Enable Chrome EC
by Hung-Te Lin (Code Review) 10 May '21

10 May '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53899 ) Change subject: mb/google/cherry: Enable Chrome EC ...................................................................... mb/google/cherry: Enable Chrome EC Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: Iab3549b5c4e7d845ddd284a0df3fb448e11fbdcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/53899 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/cherry/Kconfig M src/mainboard/google/cherry/bootblock.c M src/mainboard/google/cherry/chromeos.c M src/mainboard/google/cherry/reset.c 4 files changed, 18 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/cherry/Kconfig b/src/mainboard/google/cherry/Kconfig index bf46532..b9c63ea 100644 --- a/src/mainboard/google/cherry/Kconfig +++ b/src/mainboard/google/cherry/Kconfig @@ -6,14 +6,22 @@ if BOARD_GOOGLE_CHERRY_COMMON +config VBOOT + select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_VBNV_FLASH + config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_MEDIATEK_MT8195 select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS + select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS select COMMON_CBFS_SPI_WRAPPER select SPI_FLASH select SPI_FLASH_INCLUDE_ALL_DRIVERS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_SPI config MAINBOARD_DIR string @@ -28,4 +36,8 @@ config BOOT_DEVICE_SPI_FLASH_BUS int default 7 + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 0x0 endif diff --git a/src/mainboard/google/cherry/bootblock.c b/src/mainboard/google/cherry/bootblock.c index adb87d0..dbc6c26 100644 --- a/src/mainboard/google/cherry/bootblock.c +++ b/src/mainboard/google/cherry/bootblock.c @@ -3,6 +3,7 @@ #include <bootblock_common.h> #include <device/mmio.h> #include <soc/gpio.h> +#include <soc/spi.h> #include "gpio.h" @@ -35,6 +36,7 @@ void bootblock_mainboard_init(void) { + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0); nor_set_gpio_pinmux(); setup_chromeos_gpios(); } diff --git a/src/mainboard/google/cherry/chromeos.c b/src/mainboard/google/cherry/chromeos.c index f606ba3..1a869a3 100644 --- a/src/mainboard/google/cherry/chromeos.c +++ b/src/mainboard/google/cherry/chromeos.c @@ -28,9 +28,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_recovery_mode_switch(void) -{ - /* TODO: use Chrome EC switches when EC support is added */ - return 0; -} diff --git a/src/mainboard/google/cherry/reset.c b/src/mainboard/google/cherry/reset.c index 3a97ee5..91ee7c0 100644 --- a/src/mainboard/google/cherry/reset.c +++ b/src/mainboard/google/cherry/reset.c @@ -1,7 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <gpio.h> #include <reset.h> +#include "gpio.h" + void do_board_reset(void) { + gpio_output(GPIO_RESET, 1); } -- To view, visit https://review.coreboot.org/c/coreboot/+/53899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab3549b5c4e7d845ddd284a0df3fb448e11fbdcb Gerrit-Change-Number: 53899 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: doc/releases/coreboot-4.14: Add x86 bootblock and ACPI GNVS changes
by Paul Menzel (Code Review) 10 May '21

10 May '21

Attention is currently required from: Angel Pons, Kyösti Mälkki, Werner Zeh. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54008 ) Change subject: doc/releases/coreboot-4.14: Add x86 bootblock and ACPI GNVS changes ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/54008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa58a9ac7c6dcc391cd9942295319a8677cd4492 Gerrit-Change-Number: 54008 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 10 May 2021 05:27:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: doc/releases/coreboot-4.14: Add x86 bootblock and ACPI GNVS changes
by Kyösti Mälkki (Code Review) 10 May '21

10 May '21

Attention is currently required from: Werner Zeh. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54008 ) Change subject: doc/releases/coreboot-4.14: Add x86 bootblock and ACPI GNVS changes ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/54008/comment/b88c184c_307cff37 PS1, Line 7: GNVS > add "changes" or "adaptions" to the end of the line? Done File Documentation/releases/coreboot-4.14-relnotes.md: https://review.coreboot.org/c/coreboot/+/54008/comment/d8335ace_c230a0cc PS1, Line 66: favour > favor Done -- To view, visit https://review.coreboot.org/c/coreboot/+/54008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa58a9ac7c6dcc391cd9942295319a8677cd4492 Gerrit-Change-Number: 54008 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 10 May 2021 04:52:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: doc/releases/coreboot-4.14: Add x86 bootblock and ACPI GNVS changes
by Kyösti Mälkki (Code Review) 10 May '21

10 May '21

Attention is currently required from: Kyösti Mälkki. Hello build bot (Jenkins), Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54008 to look at the new patch set (#2). Change subject: doc/releases/coreboot-4.14: Add x86 bootblock and ACPI GNVS changes ...................................................................... doc/releases/coreboot-4.14: Add x86 bootblock and ACPI GNVS changes Change-Id: Ifa58a9ac7c6dcc391cd9942295319a8677cd4492 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M Documentation/releases/coreboot-4.14-relnotes.md 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/54008/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa58a9ac7c6dcc391cd9942295319a8677cd4492 Gerrit-Change-Number: 54008 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: doc/releases/coreboot-4.14: Add x86 bootblock and ACPI GNVS
by Werner Zeh (Code Review) 10 May '21

10 May '21

Attention is currently required from: Kyösti Mälkki. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54008 ) Change subject: doc/releases/coreboot-4.14: Add x86 bootblock and ACPI GNVS ...................................................................... Patch Set 1: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/54008/comment/5dbe7178_fe6e6f41 PS1, Line 7: GNVS add "changes" or "adaptions" to the end of the line? File Documentation/releases/coreboot-4.14-relnotes.md: https://review.coreboot.org/c/coreboot/+/54008/comment/5ff0f8f7_fd695962 PS1, Line 66: favour favor -- To view, visit https://review.coreboot.org/c/coreboot/+/54008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa58a9ac7c6dcc391cd9942295319a8677cd4492 Gerrit-Change-Number: 54008 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Mon, 10 May 2021 04:48:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: doc/releases/coreboot-4.14: Add x86 bootblock and ACPI GNVS
by Kyösti Mälkki (Code Review) 10 May '21

10 May '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54008 ) Change subject: doc/releases/coreboot-4.14: Add x86 bootblock and ACPI GNVS ...................................................................... doc/releases/coreboot-4.14: Add x86 bootblock and ACPI GNVS Change-Id: Ifa58a9ac7c6dcc391cd9942295319a8677cd4492 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M Documentation/releases/coreboot-4.14-relnotes.md 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/54008/1 diff --git a/Documentation/releases/coreboot-4.14-relnotes.md b/Documentation/releases/coreboot-4.14-relnotes.md index 6b629f4..cbbadd3 100644 --- a/Documentation/releases/coreboot-4.14-relnotes.md +++ b/Documentation/releases/coreboot-4.14-relnotes.md @@ -61,4 +61,19 @@ moved to the common AMD SoC code, so that they could be used by the Cezanne code instead of adding another slightly different copy. +### X86 bootblock layout + +The static size C_ENV_BOOTBLOCK_SIZE was mostly dropped in favour of +dynamically allocating the stage size; the Kconfig is still available +to use as a fixed size and to enforce a maximum for selected chipsets. +Linker sections are now top-aligned for a reduced flash footprint and to +maintain the requirements of near jump from reset vector. + +### ACPI GNVS framework + +SMI handlers for APM_CNT_GNVS_UDPATE were dropped; GNVS pointer to SMM is +now passed from within SMM_MODULE_LOADER. Allocation and initialisations +for common ACPI GNVS table entries were largely moved to one centralized +implementation. + ### Add significant changes here -- To view, visit https://review.coreboot.org/c/coreboot/+/54008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa58a9ac7c6dcc391cd9942295319a8677cd4492 Gerrit-Change-Number: 54008 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: move acpigen_dptc_call_alib to new common alib
by Martin Roth (Code Review) 10 May '21

10 May '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53940 ) Change subject: soc/amd/picasso: move acpigen_dptc_call_alib to new common alib ...................................................................... soc/amd/picasso: move acpigen_dptc_call_alib to new common alib Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib0f7da12429b6278d1e4bc5d6650c7ee0f3b5209 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53940 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/common/block/acpi/Kconfig M src/soc/amd/common/block/acpi/Makefile.inc A src/soc/amd/common/block/acpi/alib.c M src/soc/amd/common/block/include/amdblocks/alib.h M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/root_complex.c 6 files changed, 27 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/common/block/acpi/Kconfig b/src/soc/amd/common/block/acpi/Kconfig index 716610e..846db88 100644 --- a/src/soc/amd/common/block/acpi/Kconfig +++ b/src/soc/amd/common/block/acpi/Kconfig @@ -5,5 +5,8 @@ help Select this option to use the AcpiMmio ACPI registers. +config SOC_AMD_COMMON_BLOCK_ACPI_ALIB + bool + config SOC_AMD_COMMON_BLOCK_ACPI_GPIO bool diff --git a/src/soc/amd/common/block/acpi/Makefile.inc b/src/soc/amd/common/block/acpi/Makefile.inc index e14dba2..9f774d4 100644 --- a/src/soc/amd/common/block/acpi/Makefile.inc +++ b/src/soc/amd/common/block/acpi/Makefile.inc @@ -9,6 +9,7 @@ ramstage-y += pm_state.c ramstage-y += tables.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_ALIB) += alib.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_GPIO) += gpio.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_ACPI diff --git a/src/soc/amd/common/block/acpi/alib.c b/src/soc/amd/common/block/acpi/alib.c new file mode 100644 index 0000000..5e1e8fb --- /dev/null +++ b/src/soc/amd/common/block/acpi/alib.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> +#include <amdblocks/alib.h> +#include <types.h> + +void acpigen_dptc_call_alib(const char *buf_name, uint8_t *buffer, size_t size) +{ + /* Name (buf_name, Buffer(size) {...} */ + acpigen_write_name(buf_name); + acpigen_write_byte_buffer(buffer, size); + + /* \_SB.ALIB(0xc, buf_name) */ + acpigen_emit_namestring("\\_SB.ALIB"); + acpigen_write_integer(ALIB_FUNCTION_DYNAMIC_POWER_THERMAL_CONFIG); + acpigen_emit_namestring(buf_name); +} diff --git a/src/soc/amd/common/block/include/amdblocks/alib.h b/src/soc/amd/common/block/include/amdblocks/alib.h index 5e92924..b9d34c5 100644 --- a/src/soc/amd/common/block/include/amdblocks/alib.h +++ b/src/soc/amd/common/block/include/amdblocks/alib.h @@ -21,6 +21,8 @@ uint32_t value; } __packed; +void acpigen_dptc_call_alib(const char *buf_name, uint8_t *buffer, size_t size); + #endif /* !__ACPI__ */ #endif /* AMD_COMMON_ALIB_H */ diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 2f36f2e..e69fb62 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -28,6 +28,7 @@ select SOC_AMD_COMMON_BLOCK_ACP select SOC_AMD_COMMON_BLOCK_ACPI select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_ACPI_ALIB select SOC_AMD_COMMON_BLOCK_ACPI_GPIO select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_APOB diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 979da3e..3517e3d 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -177,18 +177,6 @@ setup_ioapic((u8 *)GNB_IO_APIC_ADDR, GNB_IOAPIC_ID); } -static void dptc_call_alib(const char *buf_name, uint8_t *buffer, size_t size) -{ - /* Name (buf_name, Buffer(size) {...} */ - acpigen_write_name(buf_name); - acpigen_write_byte_buffer(buffer, size); - - /* \_SB.ALIB(0xc, buf_name) */ - acpigen_emit_namestring("\\_SB.ALIB"); - acpigen_write_integer(ALIB_FUNCTION_DYNAMIC_POWER_THERMAL_CONFIG); - acpigen_emit_namestring(buf_name); -} - static void acipgen_dptci(void) { const struct soc_amd_picasso_config *config = config_of_soc(); @@ -214,13 +202,14 @@ /* If (LEqual ("\_SB.PCI0.LPCB.EC0.TBMD", 1)) */ acpigen_write_if_lequal_namestr_int("\\_SB.PCI0.LPCB.EC0.TBMD", 1); - dptc_call_alib("TABB", (uint8_t *)(void *)&tablet_mode_input, + acpigen_dptc_call_alib("TABB", (uint8_t *)(void *)&tablet_mode_input, sizeof(tablet_mode_input)); /* Else */ acpigen_write_else(); - dptc_call_alib("DEFB", (uint8_t *)(void *)&default_input, sizeof(default_input)); + acpigen_dptc_call_alib("DEFB", (uint8_t *)(void *)&default_input, + sizeof(default_input)); acpigen_pop_len(); /* Else */ -- To view, visit https://review.coreboot.org/c/coreboot/+/53940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0f7da12429b6278d1e4bc5d6650c7ee0f3b5209 Gerrit-Change-Number: 53940 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso: move acpigen_dptc_call_alib to new common alib
by Martin Roth (Code Review) 10 May '21

10 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53940 ) Change subject: soc/amd/picasso: move acpigen_dptc_call_alib to new common alib ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/53940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0f7da12429b6278d1e4bc5d6650c7ee0f3b5209 Gerrit-Change-Number: 53940 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 10 May 2021 04:21:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Disable CBFS MCACHE again
by Martin Roth (Code Review) 10 May '21

10 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Julius Werner. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53933 ) Change subject: soc/amd/picasso: Disable CBFS MCACHE again ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Did this ever work and break again or was it just broken the whole time? […] I don't know that this ever worked. I know it wasn't working early on, and I'm not positive when CBFS_MCACHE was enabled. FMAP_CACHE is (or at least used to be) working, but I haven't worked on ToT in a while, so I'm not sure what's working right now. -- To view, visit https://review.coreboot.org/c/coreboot/+/53933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68b4b73670e750207414f0d85ff96f21481be8ce Gerrit-Change-Number: 53933 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 10 May 2021 04:19:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit May 2021