coreboot-gerrit May 2021

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Change in coreboot[master]: security/intel/cbnt: Rename bg-prov to cbnt-prov
by Angel Pons (Code Review) 10 May '21

10 May '21

Attention is currently required from: Christian Walter, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52970 ) Change subject: security/intel/cbnt: Rename bg-prov to cbnt-prov ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54a9f458e124d355d50b5edd8694dee39657bc0d Gerrit-Change-Number: 52970 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 10 May 2021 08:04:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/entry16.S: Make Intel CBnT TOCTOU safe
by Arthur Heymans (Code Review) 10 May '21

10 May '21

Attention is currently required from: Christian Walter, Angel Pons, Kyösti Mälkki, Patrick Rudolph. Hello Christian Walter, Angel Pons, Kyösti Mälkki, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54010 to look at the new patch set (#2). Change subject: cpu/x86/entry16.S: Make Intel CBnT TOCTOU safe ...................................................................... cpu/x86/entry16.S: Make Intel CBnT TOCTOU safe Intel CBnT (and Boot Guard) makes the chain of trust TOCTOU safe by setting up NEM (non eviction mode) in the ACM. The CBnT IBB (Initial BootBlock) therefore should not disable caching. Sidenote: the MSR macros are taken from the slimbootloader project. TESTED: ocp/Deltalake boot with and without CBnT and also a broken CBnT setup. Change-Id: Id2031e4e406655e14198e45f137ba152f8b6f567 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/entry16.S M src/include/cpu/intel/msr.h 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/54010/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2031e4e406655e14198e45f137ba152f8b6f567 Gerrit-Change-Number: 54010 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8195: Disable UFS reference clock
by Rex-BC Chen (Code Review) 10 May '21

10 May '21

Attention is currently required from: Yidi Lin. Hello Yidi Lin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/54011 to review the following change. Change subject: soc/mediatek/mt8195: Disable UFS reference clock ...................................................................... soc/mediatek/mt8195: Disable UFS reference clock UFS reference clock (refclk) is enabled by default, which will cause the UFSHCI to hold the SPM signal and lead to suspend failure. Since UFS kernel driver is not built-in, disable refclk in coreboot stage. Change UFSHCI base register to 0x11270000. Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: I1386e59f802a9e3c938a7e8dbeea547fbcb02709 --- M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/include/soc/addressmap.h M src/soc/mediatek/mt8195/soc.c 3 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/54011/1 diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 88cb070..efd4a12 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -48,6 +48,7 @@ ramstage-y += soc.c ramstage-y += ../common/timer.c timer.c ramstage-y += ../common/uart.c +ramstage-y += ../common/ufs.c ramstage-y += ../common/usb.c usb.c ramstage-y += ../common/wdt.c ramstage-y += mt6360.c diff --git a/src/soc/mediatek/mt8195/include/soc/addressmap.h b/src/soc/mediatek/mt8195/include/soc/addressmap.h index db24b77..60b730a 100644 --- a/src/soc/mediatek/mt8195/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8195/include/soc/addressmap.h @@ -61,6 +61,7 @@ SPIS1_BASE = IO_PHYS + 0x0101E000, SSUSB_IPPC_BASE = IO_PHYS + 0x01203E00, MSDC0_BASE = IO_PHYS + 0x01230000, + UFSHCI_BASE = IO_PHYS + 0x01270000, SFLASH_REG_BASE = IO_PHYS + 0x0132C000, EFUSEC_BASE = IO_PHYS + 0x01C10000, MIPITX_BASE = IO_PHYS + 0x01C80000, @@ -73,7 +74,6 @@ IOCFG_RB_BASE = IO_PHYS + 0x01EB0000, IOCFG_TL_BASE = IO_PHYS + 0x01F40000, MSDC0_TOP_BASE = IO_PHYS + 0x01F50000, - UFSHCI_BASE = IO_PHYS + 0x01FA0000, DISP_OVL0_BASE = IO_PHYS + 0x0C000000, DISP_RDMA0_BASE = IO_PHYS + 0x0C002000, DISP_COLOR0_BASE = IO_PHYS + 0x0C003000, diff --git a/src/soc/mediatek/mt8195/soc.c b/src/soc/mediatek/mt8195/soc.c index 4c98a66..cd161e8 100644 --- a/src/soc/mediatek/mt8195/soc.c +++ b/src/soc/mediatek/mt8195/soc.c @@ -3,6 +3,7 @@ #include <device/device.h> #include <soc/emi.h> #include <soc/mmu_operations.h> +#include <soc/ufs.h> #include <symbols.h> static void soc_read_resources(struct device *dev) @@ -13,6 +14,7 @@ static void soc_init(struct device *dev) { mtk_mmu_disable_l2c_sram(); + ufs_disable_refclk(); } static struct device_operations soc_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/54011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1386e59f802a9e3c938a7e8dbeea547fbcb02709 Gerrit-Change-Number: 54011 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation/releases: Fill in coreboot 4.14 release notes
by Patrick Georgi (Code Review) 10 May '21

10 May '21

Attention is currently required from: Angel Pons. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54003 ) Change subject: Documentation/releases: Fill in coreboot 4.14 release notes ...................................................................... Patch Set 1: (2 comments) Patchset: PS1: > I imagine you know that CB:52735 should go in beforehand. I'm well aware, yes. File Documentation/releases/coreboot-4.14-relnotes.md: https://review.coreboot.org/c/coreboot/+/54003/comment/8b8194e2_16f8eeed PS1, Line 123: ### Add significant changes here > Drop? yes, but that part of the file will be a merge conflict area anyway (e.g. with CB:52735) -- To view, visit https://review.coreboot.org/c/coreboot/+/54003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79530c91424112247e485a5a41debc666e0072d4 Gerrit-Change-Number: 54003 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 10 May 2021 07:29:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/entry16.S: Make Intel CBnT TOCTOU safe
by build bot (Jenkins) (Code Review) 10 May '21

10 May '21

Attention is currently required from: Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54010 ) Change subject: cpu/x86/entry16.S: Make Intel CBnT TOCTOU safe ...................................................................... Patch Set 1: (1 comment) File src/include/cpu/intel/msr.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118898): https://review.coreboot.org/c/coreboot/+/54010/comment/7ff7eefa_c3c6d6a4 PS1, Line 23: #define B_BOOT_GUARD_SACM_INFO_CAPABILITY (1 << 32 Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/54010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2031e4e406655e14198e45f137ba152f8b6f567 Gerrit-Change-Number: 54010 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 10 May 2021 07:27:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/entry16.S: Make Intel CBnT TOCTOU safe
by Arthur Heymans (Code Review) 10 May '21

10 May '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54010 ) Change subject: cpu/x86/entry16.S: Make Intel CBnT TOCTOU safe ...................................................................... cpu/x86/entry16.S: Make Intel CBnT TOCTOU safe Intel CBnT (and Boot Guard) makes the chain of trust TOCTOU safe by setting up NEM (non eviction mode) in the ACM. The CBnT IBB (Initial BootBlock) therefore should not disable caching. Sidenote: the MSR macros are taken from the slimbootloader project. Change-Id: Id2031e4e406655e14198e45f137ba152f8b6f567 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/entry16.S M src/include/cpu/intel/msr.h 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/54010/1 diff --git a/src/cpu/x86/entry16.S b/src/cpu/x86/entry16.S index e1bfbf1..147906f 100644 --- a/src/cpu/x86/entry16.S +++ b/src/cpu/x86/entry16.S @@ -115,10 +115,24 @@ subw %ax, %bx lgdtl %cs:(%bx) +#if CONFIG(INTEL_CBNT_SUPPORT) +#include <cpu/intel/msr.h> + movl $MSR_BOOT_GUARD_SACM_INFO, %ecx + rdmsr + andl $B_BOOT_GUARD_SACM_INFO_NEM_ENABLED, %eax + jz 1f + movl %cr0, %eax + andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ + orl $0x01, %eax /* PE = 1 */ + movl %eax, %cr0 + jmp 2f +#endif +1: movl %cr0, %eax andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ orl $0x60000001, %eax /* CD, NW, PE = 1 */ movl %eax, %cr0 +2: /* Restore BIST to %eax */ movl %ebp, %eax diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h index 935ac30..28dea68 100644 --- a/src/include/cpu/intel/msr.h +++ b/src/include/cpu/intel/msr.h @@ -14,6 +14,14 @@ #define MSR_PLATFORM_INFO 0xce +#define MSR_BOOT_GUARD_SACM_INFO 0x13a +#define V_TPM_PRESENT_MASK 0x06 +#define B_BOOT_GUARD_SACM_INFO_NEM_ENABLED (1 << 0) +#define B_BOOT_GUARD_SACM_INFO_TPM_SUCCESS (1 << 3) +#define B_BOOT_GUARD_SACM_INFO_MEASURED_BOOT (1 << 5) +#define B_BOOT_GUARD_SACM_INFO_VERIFIED_BOOT (1 << 6) +#define B_BOOT_GUARD_SACM_INFO_CAPABILITY (1 << 32 + #define MSR_PKG_C10_RESIDENCY 0x632 #endif /* CPU_INTEL_MSR_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/54010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2031e4e406655e14198e45f137ba152f8b6f567 Gerrit-Change-Number: 54010 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Enable CnviBtAudioOffload
by Vamshi Krishna Gopal (Code Review) 10 May '21

10 May '21

Attention is currently required from: Sugnan Prabhu S, Vamshi Krishna Gopal, Sathya Prakash M R, Usha P. Vamshi Krishna Gopal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52860 ) Change subject: mb/google/brya: Enable CnviBtAudioOffload ...................................................................... Patch Set 1: (1 comment) This change is ready for review. Patchset: PS1: This WIP Activity. From kernel space we are verifying as below 1. Pair and connect BT headset 2. Issue the HCI cmds from DUT hcitool cmd 3f 08 00 00 00 00 10 00 00 00 10 00 10 00 10 00 84 01 00 00 00 00 hcitool cmd 3f 39 00 01 01 hcitool cmd 01 3d 00 01 40 1F 00 00 40 1F 00 00 02 00 00 00 00 02 00 00 00 00 3C 00 3C 00 80 3E 00 00 80 3E 00 00 04 00 00 00 00 04 00 00 00 00 10 00 10 00 02 02 00 00 01 01 10 10 0C 00 80 03 02 3.Wait to hear a very weak/faint pop from headset, then issue the playback cmd: aplay -Dplughw:0,50 -r8000 --channels=1 -fS16_LE /home/a2002011001-e02-8kHz-mono.wav To check capture: arecord -vv -Dplughw:0,50 -r8000 --channels=1 -fS16_LE /home/test.wav -- To view, visit https://review.coreboot.org/c/coreboot/+/52860 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I905d1e1d37f6fb992080edb83f8a86f501196f93 Gerrit-Change-Number: 52860 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.corp-partner.google.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.com> Gerrit-Attention: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Mon, 10 May 2021 07:11:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Fill CmdMirror and DqDqsRetraining for ADLRVP
by Maulik V Vaghela (Code Review) 10 May '21

10 May '21

Attention is currently required from: Varshit B Pandya, Furquan Shaikh, Selma Bensaid, Tim Wawrzynczak, Balaji Manigandan, Brandon Breitenstein. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51028 ) Change subject: mb/intel/adlrvp: Fill CmdMirror and DqDqsRetraining for ADLRVP ...................................................................... Patch Set 9: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/51028/comment/f460c91d_2ae28a59 PS5, Line 9: ADL M > `ADL-M` Done https://review.coreboot.org/c/coreboot/+/51028/comment/e845bdc2_d1f4d858 PS5, Line 11: bydefault > by default Done -- To view, visit https://review.coreboot.org/c/coreboot/+/51028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e16b9a3d3e6a92dacba9d38782df408596ed5e1 Gerrit-Change-Number: 51028 Gerrit-PatchSet: 9 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-CC: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Comment-Date: Mon, 10 May 2021 06:56:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/kukui: Add discrete EMCP LPDDR4X table for Kakadu/Katsu
by Hung-Te Lin (Code Review) 10 May '21

10 May '21

Attention is currently required from: Sunwei Li, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54009 ) Change subject: mb/google/kukui: Add discrete EMCP LPDDR4X table for Kakadu/Katsu ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaf05a0a7b0c0671c07b0df29319ebd91fe63e57 Gerrit-Change-Number: 54009 Gerrit-PatchSet: 1 Gerrit-Owner: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 10 May 2021 06:56:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Fill CmdMirror and DqDqsRetraining for ADLRVP
by Maulik V Vaghela (Code Review) 10 May '21

10 May '21

Attention is currently required from: Varshit B Pandya, Furquan Shaikh, Maulik V Vaghela, Selma Bensaid, Balaji Manigandan, Tim Wawrzynczak, Brandon Breitenstein. Hello Bora Guvendik, Varshit B Pandya, build bot (Jenkins), Furquan Shaikh, Selma Bensaid, Tim Wawrzynczak, Balaji Manigandan, Tim Wawrzynczak, Brandon Breitenstein, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51028 to look at the new patch set (#8). Change subject: mb/intel/adlrvp: Fill CmdMirror and DqDqsRetraining for ADLRVP ...................................................................... mb/intel/adlrvp: Fill CmdMirror and DqDqsRetraining for ADLRVP ADL-M LP4 RVP has command mirror enabled and we need to fill correct value of this UPD to pass the MRC. Also, Value of TxDqDqsRetraining is set to 1 by default and we need to disable it for only ADL-M LP5 RVP. BUG=None BRANCH=None TEST=UPD values has been pass correctly and MRC passes on LP4/LP5 board Change-Id: I3e16b9a3d3e6a92dacba9d38782df408596ed5e1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/intel/adlrvp/memory.c 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/51028/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/51028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e16b9a3d3e6a92dacba9d38782df408596ed5e1 Gerrit-Change-Number: 51028 Gerrit-PatchSet: 8 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-CC: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021