coreboot-gerrit May 2021

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Change in coreboot[master]: device/device.c: Print bus numbers in decimal
by Angel Pons (Code Review) 10 May '21

10 May '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54015 ) Change subject: device/device.c: Print bus numbers in decimal ...................................................................... device/device.c: Print bus numbers in decimal For consistency with other log messages, print bus numbers in decimal. Change-Id: Ib08ae40fc67c5f8fafd760e8dbb729d6de34c2bb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/device/device.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/54015/1 diff --git a/src/device/device.c b/src/device/device.c index aa10d6f..a3bf1a1 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -154,7 +154,7 @@ { struct device *curdev; - printk(BIOS_SPEW, "%s %s bus %x link: %d\n", dev_path(bus->dev), + printk(BIOS_SPEW, "%s %s bus %d link: %d\n", dev_path(bus->dev), __func__, bus->secondary, bus->link_num); /* Walk through all devices and find which resources they need. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/54015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib08ae40fc67c5f8fafd760e8dbb729d6de34c2bb Gerrit-Change-Number: 54015 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8195: Enable SCP SRAM
by build bot (Jenkins) (Code Review) 10 May '21

10 May '21

Attention is currently required from: Hung-Te Lin. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54014 ) Change subject: soc/mediatek/mt8195: Enable SCP SRAM ...................................................................... Patch Set 1: (1 comment) File src/soc/mediatek/mt8195/scp.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118904): https://review.coreboot.org/c/coreboot/+/54014/comment/60d56601_96629667 PS1, Line 19: } adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/54014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40862f8d74e5aa17361f1c91ea31a10b0a4ffb31 Gerrit-Change-Number: 54014 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Mon, 10 May 2021 10:02:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Enable SCP SRAM
by Rex-BC Chen (Code Review) 10 May '21

10 May '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54014 ) Change subject: soc/mediatek/mt8195: Enable SCP SRAM ...................................................................... soc/mediatek/mt8195: Enable SCP SRAM Enable SCP SRAM to allow module in SCPSYS to access DRAM. TEST=AFE acess DRAM successfully Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I40862f8d74e5aa17361f1c91ea31a10b0a4ffb31 --- M src/mainboard/google/cherry/romstage.c M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/include/soc/scp.h A src/soc/mediatek/mt8195/scp.c 4 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/54014/1 diff --git a/src/mainboard/google/cherry/romstage.c b/src/mainboard/google/cherry/romstage.c index cdb2681..ec7e4f9 100644 --- a/src/mainboard/google/cherry/romstage.c +++ b/src/mainboard/google/cherry/romstage.c @@ -6,6 +6,7 @@ #include <soc/mt6359p.h> #include <soc/pmif.h> #include <soc/rtc.h> +#include <soc/scp.h> void platform_romstage_main(void) { @@ -14,4 +15,5 @@ mt6315_init(); clk_buf_init(); rtc_boot(); + scp_rsi_enable(); } diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index efd4a12..67ceed3 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -27,6 +27,7 @@ romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/pll.c pll.c +romstage-y += scp.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c timer.c romstage-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8195/include/soc/scp.h b/src/soc/mediatek/mt8195/include/soc/scp.h new file mode 100644 index 0000000..c5c552b --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/scp.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8195_SCP_H +#define SOC_MEDIATEK_MT8195_SCP_H + +#include <soc/addressmap.h> + +#define SCP_SRAM_PDN_DISABLE_VAL 0xFFFFFFFF + +#define REG_L1TCM_SRAM_PDN (void *)(SCP_CFG_BASE + 0x2102C) + +void scp_rsi_enable(void); +void scp_rsi_disable(void); +#endif diff --git a/src/soc/mediatek/mt8195/scp.c b/src/soc/mediatek/mt8195/scp.c new file mode 100644 index 0000000..05cacc4 --- /dev/null +++ b/src/soc/mediatek/mt8195/scp.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/scp.h> + +void scp_rsi_enable(void) +{ + u32 val; + + for (val = SCP_SRAM_PDN_DISABLE_VAL; val != 0U;) { + val = val >> 1; + write32(REG_L1TCM_SRAM_PDN, val); + } +} + +void scp_rsi_disable(void) +{ + write32(REG_L1TCM_SRAM_PDN, SCP_SRAM_PDN_DISABLE_VAL); +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/54014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40862f8d74e5aa17361f1c91ea31a10b0a4ffb31 Gerrit-Change-Number: 54014 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/cherry: Pass reset gpio parameter to BL31
by Rex-BC Chen (Code Review) 10 May '21

10 May '21

Attention is currently required from: Yidi Lin. Hello Yidi Lin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/54013 to review the following change. Change subject: mb/google/cherry: Pass reset gpio parameter to BL31 ...................................................................... mb/google/cherry: Pass reset gpio parameter to BL31 To support gpio reset SoC, we need to pass the reset gpio parameter to BL31. TEST=execute `echo b > /proc/sysrq-trigger` to reboot system Change-Id: I1a55216c0d5a00bbdb373d931bd50ebe7ca5694f Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> --- M src/mainboard/google/cherry/mainboard.c 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/54013/1 diff --git a/src/mainboard/google/cherry/mainboard.c b/src/mainboard/google/cherry/mainboard.c index 5015531..2607a2d 100644 --- a/src/mainboard/google/cherry/mainboard.c +++ b/src/mainboard/google/cherry/mainboard.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bl31.h> #include <bootmode.h> #include <console/console.h> #include <delay.h> @@ -12,6 +13,10 @@ #include <soc/regulator.h> #include <soc/usb.h> +#include "gpio.h" + +#include <arm-trusted-firmware/include/export/plat/mediatek/common/plat_params_exp.h> + DEFINE_BITFIELD(MSDC0_DRV, 29, 0) DEFINE_BITFIELD(MSDC1_DRV, 17, 0) DEFINE_BITFIELD(MSDC1_GPIO_MODE0_0, 26, 24) @@ -31,6 +36,17 @@ MSDC1_GPIO_MODE1_BASE = 0x100053e0, }; +static void register_reset_to_bl31(void) +{ + static struct bl_aux_param_gpio param_reset = { + .h = { .type = BL_AUX_PARAM_MTK_RESET_GPIO }, + .gpio = { .polarity = ARM_TF_GPIO_LEVEL_HIGH }, + }; + + param_reset.gpio.index = GPIO_RESET.id; + register_bl31_aux_param(&param_reset.h); +} + static void configure_emmc(void) { void *gpio_base = (void *)IOCFG_TL_BASE; @@ -107,6 +123,8 @@ configure_emmc(); configure_sdcard(); setup_usb_host(); + + register_reset_to_bl31(); } static void mainboard_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/54013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a55216c0d5a00bbdb373d931bd50ebe7ca5694f Gerrit-Change-Number: 54013 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8195: Disable UFS reference clock
by Yu-Ping Wu (Code Review) 10 May '21

10 May '21

Attention is currently required from: Hung-Te Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54011 ) Change subject: soc/mediatek/mt8195: Disable UFS reference clock ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1386e59f802a9e3c938a7e8dbeea547fbcb02709 Gerrit-Change-Number: 54011 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Mon, 10 May 2021 09:27:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Enable and initialize eint
by Yu-Ping Wu (Code Review) 10 May '21

10 May '21

Attention is currently required from: Hung-Te Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54007 ) Change subject: soc/mediatek/mt8195: Enable and initialize eint ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I703d87e3dc49cf4e0b7ff0c75a6ea80245dd73d3 Gerrit-Change-Number: 54007 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Mon, 10 May 2021 09:26:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/entry16.S: Make Intel CBnT TOCTOU safe
by Angel Pons (Code Review) 10 May '21

10 May '21

Attention is currently required from: Christian Walter, Arthur Heymans, Kyösti Mälkki, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54010 ) Change subject: cpu/x86/entry16.S: Make Intel CBnT TOCTOU safe ...................................................................... Patch Set 2: (1 comment) File src/cpu/x86/entry16.S: https://review.coreboot.org/c/coreboot/+/54010/comment/e8c68ccf_2cd80a89 PS2, Line 135: 2: The main concern I have with your approach is that the cr0 read-modify-write sequence is repeated twice, but I'm not bothered enough to block this change. > The advantage with how I did it, is that for non-CBnT platforms nothing changes. Sure. > Keeping track of registers depending on CPP is probably better to avoid. Even with your approach, %ecx and %edx are only clobbered inside the #if/#endif section. In any case, the code that sets up IDT/GDT already clobbers these registers. > See the discussion in CB:38252 I see this comment from kmalkki: > Just my personal preference, there is a read-modify-write sequence on cr0 that I would rather not see split to so many lines. Specially with rdmsr there in the middle register usage is not so obvious. I didn't split the read-modify-write sequence because of this. -- To view, visit https://review.coreboot.org/c/coreboot/+/54010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2031e4e406655e14198e45f137ba152f8b6f567 Gerrit-Change-Number: 54010 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 10 May 2021 09:23:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: payload/external/tianocore/Kconfig: Toggle default payload
by Patrik Tesarik (Code Review) 10 May '21

10 May '21

Attention is currently required from: Felix Singer, Nico Huber, Martin Roth, Stefan Reinauer, Angel Pons, Andrey Petrov, Patrick Rudolph. Patrik Tesarik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53934 ) Change subject: payload/external/tianocore/Kconfig: Toggle default payload ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/53934/comment/58527026_dad4b252 PS5, Line 11: is not working > Just wondering.. […] I can't go into (technical) detail regarding TIANOCORE_COREBOOTPAYLOAD, but symptomatically there are X64 Exception Errors (NM device not found or Divide Error, see [1]) showing up on the UP2 board and even with qemu-system-x86_64 emulation with the "-M pc" setting, which corresponds to "i440fx". Using "-M q35" it works. [1] https://wiki.osdev.org/Exceptions#Device_Not_Available -- To view, visit https://review.coreboot.org/c/coreboot/+/53934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib50fdaf2cd5c599e497ef8ca06e5692a9e69b813 Gerrit-Change-Number: 53934 Gerrit-PatchSet: 5 Gerrit-Owner: Patrik Tesarik Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 10 May 2021 09:15:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/entry16.S: Make Intel CBnT TOCTOU safe
by Arthur Heymans (Code Review) 10 May '21

10 May '21

Attention is currently required from: Christian Walter, Angel Pons, Kyösti Mälkki, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54010 ) Change subject: cpu/x86/entry16.S: Make Intel CBnT TOCTOU safe ...................................................................... Patch Set 2: (1 comment) File src/cpu/x86/entry16.S: https://review.coreboot.org/c/coreboot/+/54010/comment/9020936c_d922f57b PS2, Line 135: 2: > Looks like CMOVcc does not work with immediates... > > movl $0x60000001, %ebx /* CD, NW, PE = 1 */ > #if CONFIG(INTEL_CBNT_SUPPORT) > #include <cpu/intel/msr.h> > /* Do not disable caching if the BootGuard ACM has set up CAR */ > movl $MSR_BOOT_GUARD_SACM_INFO, %ecx > rdmsr > movl $0x01, %edx /* PE = 1 */ > test $B_BOOT_GUARD_SACM_INFO_NEM_ENABLED, %eax > cmovne %edx, %ebx > #endif > movl %cr0, %eax > andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ > orl %ebx, %eax > movl %eax, %cr0 > > Alternatively, use a jump The advantage with how I did it, is that for non-CBnT platforms nothing changes. Keeping track of registers depending on CPP is probably better to avoid. See the discussion in CB:38252 -- To view, visit https://review.coreboot.org/c/coreboot/+/54010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2031e4e406655e14198e45f137ba152f8b6f567 Gerrit-Change-Number: 54010 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 10 May 2021 08:56:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/entry16.S: Make Intel CBnT TOCTOU safe
by Angel Pons (Code Review) 10 May '21

10 May '21

Attention is currently required from: Christian Walter, Arthur Heymans, Kyösti Mälkki, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54010 ) Change subject: cpu/x86/entry16.S: Make Intel CBnT TOCTOU safe ...................................................................... Patch Set 2: (1 comment) File src/cpu/x86/entry16.S: https://review.coreboot.org/c/coreboot/+/54010/comment/52b01468_63ea9d1b PS2, Line 135: 2: > Since %ebx is not used, how about: […] Looks like CMOVcc does not work with immediates... movl $0x60000001, %ebx /* CD, NW, PE = 1 */ #if CONFIG(INTEL_CBNT_SUPPORT) #include <cpu/intel/msr.h> /* Do not disable caching if the BootGuard ACM has set up CAR */ movl $MSR_BOOT_GUARD_SACM_INFO, %ecx rdmsr movl $0x01, %edx /* PE = 1 */ test $B_BOOT_GUARD_SACM_INFO_NEM_ENABLED, %eax cmovne %edx, %ebx #endif movl %cr0, %eax andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ orl %ebx, %eax movl %eax, %cr0 Alternatively, use a jump -- To view, visit https://review.coreboot.org/c/coreboot/+/54010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2031e4e406655e14198e45f137ba152f8b6f567 Gerrit-Change-Number: 54010 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 10 May 2021 08:50:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit May 2021