coreboot-gerrit May 2021

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Change in coreboot[master]: drivers/i2c/cs42l42: Make HS_BIAS_SENSE_EN optional
by build bot (Jenkins) (Code Review) 10 May '21

10 May '21

Attention is currently required from: Furquan Shaikh, Ian Feng, Vitaly Rodionov, Angel Pons, Marco Chen, Karthik Ramasubramanian. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52981 ) Change subject: drivers/i2c/cs42l42: Make HS_BIAS_SENSE_EN optional ...................................................................... Patch Set 3: (1 comment) File src/drivers/i2c/cs42l42/cs42l42.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118921): https://review.coreboot.org/c/coreboot/+/52981/comment/b98522a8_491e01f9 PS3, Line 90: acpi_dp_add_integer(dsd, "cirrus,hs-bias-sense-disable", config->hs_bias_sense_disable ? 1 : 0); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/52981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87c6f01af1bdb5b1cb8e399191519598d7fbe9ea Gerrit-Change-Number: 52981 Gerrit-PatchSet: 3 Gerrit-Owner: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Marco Chen <marcochen(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 10 May 2021 15:13:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/cs42l42: Make HS_BIAS_SENSE_EN optional
by Vitaly Rodionov (Code Review) 10 May '21

10 May '21

Attention is currently required from: Furquan Shaikh, Ian Feng, Vitaly Rodionov, Angel Pons, Marco Chen, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Marco Chen, Karthik Ramasubramanian, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52981 to look at the new patch set (#3). Change subject: drivers/i2c/cs42l42: Make HS_BIAS_SENSE_EN optional ...................................................................... drivers/i2c/cs42l42: Make HS_BIAS_SENSE_EN optional HSBIAS_SENSE_EN configures HSBIAS output current sense through the external 2.21-k resistor. HSBIAS_SENSE is hardware feature to reduce the potential pop noise during the headset plug out slowly. But on some platforms ESD voltage will affect it causing test to fail, especially with CTIA headset type. For different hardware setups, a designer might want to tweak default behavior. Signed-off-by: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> Change-Id: I87c6f01af1bdb5b1cb8e399191519598d7fbe9ea --- M src/drivers/i2c/cs42l42/chip.h M src/drivers/i2c/cs42l42/cs42l42.c 2 files changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/52981/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/52981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87c6f01af1bdb5b1cb8e399191519598d7fbe9ea Gerrit-Change-Number: 52981 Gerrit-PatchSet: 3 Gerrit-Owner: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Marco Chen <marcochen(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: device: Drop unused `uma_memory_{base,size}` globals
by Felix Held (Code Review) 10 May '21

10 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53977 ) Change subject: device: Drop unused `uma_memory_{base,size}` globals ...................................................................... device: Drop unused `uma_memory_{base,size}` globals These global variables are not used anywhere. Drop them. Change-Id: I3fe60b970153d913ae7b005257e2b53647d6f343 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53977 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/device/device.c M src/include/device/device.h 2 files changed, 0 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/device/device.c b/src/device/device.c index aa10d6f..5611022 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -66,12 +66,6 @@ DECLARE_SPIN_LOCK(dev_lock) -#if CONFIG(GFXUMA) -/* IGD UMA memory */ -uint64_t uma_memory_base = 0; -uint64_t uma_memory_size = 0; -#endif - /** * Allocate a new device structure. * diff --git a/src/include/device/device.h b/src/include/device/device.h index 01e2c82..88b5310 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -168,12 +168,6 @@ extern const char mainboard_name[]; -#if CONFIG(GFXUMA) -/* IGD UMA memory */ -extern uint64_t uma_memory_base; -extern uint64_t uma_memory_size; -#endif - /* Generic device interface functions */ struct device *alloc_dev(struct bus *parent, struct device_path *path); void dev_initialize_chips(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/53977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fe60b970153d913ae7b005257e2b53647d6f343 Gerrit-Change-Number: 53977 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: src: Drop "This file is part of the coreboot project" lines
by Felix Held (Code Review) 10 May '21

10 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53976 ) Change subject: src: Drop "This file is part of the coreboot project" lines ...................................................................... src: Drop "This file is part of the coreboot project" lines Commit 6b5bc77c9b22c398262ff3f4dae3e14904c57366 (treewide: Remove "this file is part of" lines) removed most of them, but missed some files. Change-Id: Ib8e7ab26a74b52f86d91faeba77df3331531763f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53976 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/include/metadata_hash.h M src/lib/metadata_hash.c M src/soc/intel/apollolake/include/soc/msr.h M src/soc/intel/xeon_sp/acpi/gpio.asl M src/vendorcode/amd/agesa/Kconfig 5 files changed, 0 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/src/include/metadata_hash.h b/src/include/metadata_hash.h index bfa7ef1..e945300 100644 --- a/src/include/metadata_hash.h +++ b/src/include/metadata_hash.h @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ #ifndef _METADATA_HASH_H_ #define _METADATA_HASH_H_ diff --git a/src/lib/metadata_hash.c b/src/lib/metadata_hash.c index 5619efe..e10f6ff 100644 --- a/src/lib/metadata_hash.c +++ b/src/lib/metadata_hash.c @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ #include <assert.h> #include <metadata_hash.h> diff --git a/src/soc/intel/apollolake/include/soc/msr.h b/src/soc/intel/apollolake/include/soc/msr.h index cee11c2..e35c881 100644 --- a/src/soc/intel/apollolake/include/soc/msr.h +++ b/src/soc/intel/apollolake/include/soc/msr.h @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ #ifndef _SOC_MSR_H_ #define _SOC_MSR_H_ diff --git a/src/soc/intel/xeon_sp/acpi/gpio.asl b/src/soc/intel/xeon_sp/acpi/gpio.asl index 6fe3d51..c7a9f95 100644 --- a/src/soc/intel/xeon_sp/acpi/gpio.asl +++ b/src/soc/intel/xeon_sp/acpi/gpio.asl @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ #include <soc/gpio.h> #include <soc/pcr_ids.h> diff --git a/src/vendorcode/amd/agesa/Kconfig b/src/vendorcode/amd/agesa/Kconfig index 67055ea..ce59fe1 100644 --- a/src/vendorcode/amd/agesa/Kconfig +++ b/src/vendorcode/amd/agesa/Kconfig @@ -1,5 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only -# This file is part of the coreboot project. choice prompt "DDR3 memory profile" -- To view, visit https://review.coreboot.org/c/coreboot/+/53976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8e7ab26a74b52f86d91faeba77df3331531763f Gerrit-Change-Number: 53976 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: include/console: Rename and update POST_ENTRY_RAMSTAGE postcode
by Subrata Banik (Code Review) 10 May '21

10 May '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Angel Pons, Tim Wawrzynczak. Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Angel Pons, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52947 to look at the new patch set (#2). Change subject: include/console: Rename and update POST_ENTRY_RAMSTAGE postcode ...................................................................... include/console: Rename and update POST_ENTRY_RAMSTAGE postcode Rename and update POST_ENTRY_RAMSTAGE postcode value from 0x80 to 0x6f to make the ramstage postcodes appear in an incremental order. Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I60f4bd8b2e6b2b887dee7c4991a14ce5d644fdba --- M src/include/console/post_codes.h M src/lib/hardwaremain.c 2 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/52947/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60f4bd8b2e6b2b887dee7c4991a14ce5d644fdba Gerrit-Change-Number: 52947 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: include/console: Rename POST_ENTRY_RAMSTAGE to POST_ENTRY_HARDWAREMAIN
by Subrata Banik (Code Review) 10 May '21

10 May '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Angel Pons, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52947 ) Change subject: include/console: Rename POST_ENTRY_RAMSTAGE to POST_ENTRY_HARDWAREMAIN ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52947/comment/4bf476ad_5fdce40b PS1, Line 7: Rename > This patch also changes the POSTed value, it's more than a rename. Ack https://review.coreboot.org/c/coreboot/+/52947/comment/185100e2_e6ae8a26 PS1, Line 9: updated > nit: update Ack File src/include/console/post_codes.h: https://review.coreboot.org/c/coreboot/+/52947/comment/8357e0c6_0d8b7ea5 PS1, Line 120: > One tab too few Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/52947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60f4bd8b2e6b2b887dee7c4991a14ce5d644fdba Gerrit-Change-Number: 52947 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Mon, 10 May 2021 14:21:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Merge soc_memory_init_params() into its caller
by Felix Held (Code Review) 10 May '21

10 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52491 ) Change subject: soc/intel/cannonlake: Merge soc_memory_init_params() into its caller ...................................................................... soc/intel/cannonlake: Merge soc_memory_init_params() into its caller soc_memory_init_params() does not only configure memory init parameters. Despite its name, it also configures many other things. Therefore, merge it into its caller function platform_fsp_memory_init_params_cb() to prevent confusions. Built clevo/l140cu with BUILD_TIMELESS=1. coreboot.rom remains the same. Change-Id: Id3b6395ea5d5cb714a412c856d66d4a9bcbd9c12 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52491 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/cannonlake/romstage/fsp_params.c 1 file changed, 5 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 5eddf85..2bb3024 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -17,19 +17,21 @@ #include "../chip.h" -static void soc_memory_init_params(FSPM_UPD *mupd, const config_t *config) +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { + const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); + assert(dev != NULL); + const config_t *config = config_of(dev); FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig; - unsigned int i; uint32_t mask = 0; - const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); /* * Probe for no IGD and disable InternalGfx and panel power to prevent a * crash in FSP-M. */ + dev = pcidev_path_on_root(SA_DEVFN_IGD); const bool igd_on = !CONFIG(SOC_INTEL_DISABLE_IGD) && dev && dev->enabled; if (igd_on && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) != 0xffff) { /* Set IGD stolen size to 64MB. */ @@ -131,17 +133,6 @@ if (config->DisableHeciRetry) tconfig->DisableHeciRetry = config->DisableHeciRetry; #endif -} - -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -{ - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); - assert(dev != NULL); - const config_t *config = config_of(dev); - FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig; - - soc_memory_init_params(mupd, config); /* Enable SMBus controller based on config */ dev = pcidev_path_on_root(PCH_DEVFN_SMBUS); -- To view, visit https://review.coreboot.org/c/coreboot/+/52491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3b6395ea5d5cb714a412c856d66d4a9bcbd9c12 Gerrit-Change-Number: 52491 Gerrit-PatchSet: 12 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: include/console: Fix duplicate entry of postcode 0x79
by Subrata Banik (Code Review) 10 May '21

10 May '21

Attention is currently required from: Subrata Banik, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52895 ) Change subject: include/console: Fix duplicate entry of postcode 0x79 ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52895/comment/b456756f_1ab0a2d1 PS4, Line 9: Changed > Change Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Gerrit-Change-Number: 52895 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 10 May 2021 14:16:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: include/console: Fix duplicate entry of postcode 0x79
by Subrata Banik (Code Review) 10 May '21

10 May '21

Attention is currently required from: Subrata Banik, Nico Huber, Furquan Shaikh, Tim Wawrzynczak. Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52895 to look at the new patch set (#5). Change subject: include/console: Fix duplicate entry of postcode 0x79 ...................................................................... include/console: Fix duplicate entry of postcode 0x79 Change POST_PRE_HARDWAREMAIN postcode value from 0x79 to 0x6e to avoid duplicate entry. Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/c_start.S M src/include/console/post_codes.h 2 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/52895/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/52895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Gerrit-Change-Number: 52895 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: Set proper defaults in chipset devicetree
by Felix Held (Code Review) 10 May '21

10 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53925 ) Change subject: soc/intel/skylake: Set proper defaults in chipset devicetree ...................................................................... soc/intel/skylake: Set proper defaults in chipset devicetree LPC, P2SB and Power Management controller are always needed. Thus, enable them by default. Change-Id: I20b8cbe536da70fccc3d11e1eedf4a5e14bfc862 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53925 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/skylake/chipset.cb 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/skylake/chipset.cb b/src/soc/intel/skylake/chipset.cb index 428db67..37100f0 100644 --- a/src/soc/intel/skylake/chipset.cb +++ b/src/soc/intel/skylake/chipset.cb @@ -59,9 +59,9 @@ device pci 1e.4 alias emmc off end # EMMC device pci 1e.5 alias sdio off end # SDIO device pci 1e.6 alias sdxc off end # SDXC - device pci 1f.0 alias lpc_espi off end # LPC Interface - device pci 1f.1 alias p2sb off end # P2SB - device pci 1f.2 alias pmc off end # Power Management Controller + device pci 1f.0 alias lpc_espi on end # LPC Interface + device pci 1f.1 alias p2sb on end # P2SB + device pci 1f.2 alias pmc on end # Power Management Controller device pci 1f.3 alias hda off end # Intel HDA device pci 1f.4 alias smbus off end # SMBus device pci 1f.5 alias fast_spi off end # PCH SPI -- To view, visit https://review.coreboot.org/c/coreboot/+/53925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20b8cbe536da70fccc3d11e1eedf4a5e14bfc862 Gerrit-Change-Number: 53925 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit May 2021