Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54019 )
Change subject: payloads/Tianocore: Update default build target, simplify build options
......................................................................
payloads/Tianocore: Update default build target, simplify build options
Drop the deprecated COREBOOTPAYLOAD option, and replace it with MrChromebox's
updated UefiPayloadPkg option. Simplify the Kconfig options to make it easier
to build from upstream edk2 master. Clean up the Makefile now that we're only
building from a single Tianocore package/target.
Test: build/boot qemu Q35 target with both UefiPayload and Upstream options.
Change-Id: If545fbd0c30be6dcc6ff43107b80980fa23a527e
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M Documentation/payloads.md
M payloads/external/Makefile.inc
M payloads/external/tianocore/Kconfig
M payloads/external/tianocore/Makefile
4 files changed, 24 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/54019/1
diff --git a/Documentation/payloads.md b/Documentation/payloads.md
index eee841e..7f4c08c 100644
--- a/Documentation/payloads.md
+++ b/Documentation/payloads.md
@@ -21,7 +21,7 @@
implementation of the UEFI Specifications that modern firmware for PCs is
based on. There were various projects in the past to make it suitable as a
coreboot payload, but these days this function is available directly in the
-CorebootPayloadPkg part of its source tree.
+UefiPayloadPkg part of its source tree.
## GRUB2
diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc
index 9b4e708..7f7937c 100644
--- a/payloads/external/Makefile.inc
+++ b/payloads/external/Makefile.inc
@@ -146,7 +146,7 @@
CONFIG_TIANOCORE_USE_8254_TIMER=$(CONFIG_TIANOCORE_USE_8254_TIMER) \
CONFIG_TIANOCORE_BOOTSPLASH_FILE=$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
CONFIG_TIANOCORE_UEFIPAYLOAD=$(CONFIG_TIANOCORE_UEFIPAYLOAD) \
- CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \
+ CONFIG_TIANOCORE_UPSTREAM=$(CONFIG_TIANOCORE_UPSTREAM) \
CONFIG_MMCONF_BASE_ADDRESS=$(CONFIG_MMCONF_BASE_ADDRESS) \
CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \
GCC_CC_x86_32=$(GCC_CC_x86_32) \
diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig
index 87b6e15..8b99eda 100644
--- a/payloads/external/tianocore/Kconfig
+++ b/payloads/external/tianocore/Kconfig
@@ -4,26 +4,26 @@
string "Tianocore binary"
default "payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd"
help
- The result of a corebootPkg build
+ The result of a UefiPayloadPkg build
choice
prompt "Tianocore payload"
- default TIANOCORE_COREBOOTPAYLOAD
+ default TIANOCORE_UEFIPAYLOAD
help
- Select which type of payload Tianocore will build (default is CorebootPayload)
- CorebootPayload: MrChromebox's customized version of Tianocore which works on most
- (all?) x86_64 devices
- UEFIPayload: Use upstream Tianocore payload from https://github.com/tianocore/edk2
-
-config TIANOCORE_COREBOOTPAYLOAD
- bool "CorebootPayload"
- help
- Select this option to build using MrChromebox's custom Tianocore tree
- i.e. a version of Tianocore that builds without any errors and just works.
+ Select which type of payload Tianocore will build (default is UefiPayload)
+ UefiPayload: MrChromebox's customized fork of Tianocore which works on most
+ x86_64 devices
+ Upstream: Use upstream Tianocore payload from https://github.com/tianocore/edk2
config TIANOCORE_UEFIPAYLOAD
bool "UEFIPayload"
help
+ Select this option to build using MrChromebox's custom Tianocore fork,
+ which incorporates fixes/improvements from System76's and 9Elements' trees.
+
+config TIANOCORE_UPSTREAM
+ bool "Upstream"
+ help
Select this option if you want to use upstream EDK2 to build Tianocore.
endchoice
diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile
index 7cd34f1..c9e4d1f 100644
--- a/payloads/external/tianocore/Makefile
+++ b/payloads/external/tianocore/Makefile
@@ -6,18 +6,15 @@
project_name=Tianocore
project_dir=$(CURDIR)/tianocore
project_git_repo=https://github.com/mrchromebox/edk2
-project_git_branch=coreboot_fb
+project_git_branch=uefipayloadpkg
upstream_git_repo=https://github.com/tianocore/edk2
-ifeq ($(CONFIG_TIANOCORE_UEFIPAYLOAD),y)
-bootloader=UefiPayloadPkg
-logo_pkg=MdeModulePkg
build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE
+
+ifeq ($(CONFIG_TIANOCORE_UPSTREAM),y)
TAG=upstream/master
else
-bootloader=CorebootPayloadPkg
-logo_pkg=CorebootPayloadPkg
-# STABLE revision is MrChromebox's coreboot framebuffer (coreboot_fb) branch
+# STABLE revision is MrChromebox's UefiPayloadPkg (ueifpayloadpkg) branch
TAG=origin/$(project_git_branch)
endif
@@ -39,17 +36,13 @@
TIMEOUT=-D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT)
-ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y)
ifeq ($(CONFIG_TIANOCORE_TARGET_IA32), y)
-ARCH=-a IA32 -p CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+ARCH=-a IA32
else
-ARCH=-a IA32 -a X64 -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
-endif
-else
-ARCH=-a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc
+ARCH=-a IA32 -a X64
endif
-BUILD_STR=-q $(ARCH) -t COREBOOT -b $(BUILD_TYPE) $(TIMER) $(TIMEOUT) $(build_flavor)
+BUILD_STR=-q $(ARCH) -p UefiPayloadPkg/UefiPayloadPkg.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMER) $(TIMEOUT) $(build_flavor)
all: clean build
@@ -93,9 +86,9 @@
echo " Copying custom bootsplash image"; \
case "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" in \
/*) cp $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
- $(project_dir)/$(logo_pkg)/Logo/Logo.bmp;; \
+ $(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
*) cp $(top)/$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
- $(project_dir)/$(logo_pkg)/Logo/Logo.bmp;; \
+ $(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
esac \
fi; \
cd $(project_dir); \
@@ -108,7 +101,7 @@
fi; \
build $(BUILD_STR); \
mv $(project_dir)/Build/$(bootloader)*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd; \
- git checkout $(logo_pkg)/Logo/Logo.bmp > /dev/null 2>&1 || true
+ git checkout MdeModulePkg/Logo/Logo.bmp > /dev/null 2>&1 || true
clean:
test -d $(project_dir) && (cd $(project_dir); rm -rf Build; rm -f Conf/tools_def.txt) || exit 0
--
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Star Labs has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52796 )
Change subject: src/intel: Add LOCKDIS to mark SPI as writable in SKL
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> 0x80 means locked, SMM BIOS write protection not enabled, writes disabled. […]
You can still write to it, that wasn't the problem. It's just the register being wrong.
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Nikolai Vyssotski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52230 )
Change subject: soc/amd/cezanne: Supply SMBIOS/DMI Type 17 data
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52230/comment/86747c4e_dca39606
PS1, Line 16: but then stoneyridge will break
> Can dmi_info. […]
No, those are different between CZN and PCO.
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Change subject: src/intel: Add LOCKDIS to mark SPI as writable in SKL
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> that's indeed strange, but all platforms use the same code to lock the BC register. […]
0x80 means locked, SMM BIOS write protection not enabled, writes disabled. One can set bit 0 to enable writes.
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Change subject: ec: Add Star Labs ITE 8987E support
......................................................................
Patch Set 7:
(2 comments)
File src/ec/starlabs/it8987/ec.h:
https://review.coreboot.org/c/coreboot/+/52797/comment/ae57c05f_13d4f557
PS6, Line 11: 0x4e
> The datasheet for the IT8987 does allow 0x2e/0x2f and 0x4e/0x4f as address/data register pairs. […]
But it could be changed. See comment in source file.
File src/ec/starlabs/it8987/ec.c:
https://review.coreboot.org/c/coreboot/+/52797/comment/6f2028da_a735da12
PS7, Line 16: IT8987E_ADDR
this address can be optioned from the struct device* passed in it8987_init. It's the address you assign to the PNP device in the mainboard's devicetree. There are also helper functions that allow to read the SIO address space, no need to open code it.
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Hello build bot (Jenkins), Furquan Shaikh, Marco Chen, Karthik Ramasubramanian, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52981
to look at the new patch set (#4).
Change subject: drivers/i2c/cs42l42: Make HS_BIAS_SENSE_EN optional
......................................................................
drivers/i2c/cs42l42: Make HS_BIAS_SENSE_EN optional
HSBIAS_SENSE_EN configures HSBIAS output current sense through
the external 2.21-k resistor. HSBIAS_SENSE is hardware feature to reduce
the potential pop noise during the headset plug out slowly. But on some
platforms ESD voltage will affect it causing test to fail, especially
with CTIA headset type. For different hardware setups, a designer might
want to tweak default behavior.
Signed-off-by: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com>
Change-Id: I87c6f01af1bdb5b1cb8e399191519598d7fbe9ea
---
M src/drivers/i2c/cs42l42/chip.h
M src/drivers/i2c/cs42l42/cs42l42.c
2 files changed, 14 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/52981/4
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