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Change subject: cpu/x86/entry16.S: Make Intel CBnT TOCTOU safe
......................................................................
Patch Set 2: Code-Review+1
(4 comments)
File src/cpu/x86/entry16.S:
https://review.coreboot.org/c/coreboot/+/54010/comment/fa71be8d_690edda2
PS2, Line 135: 2:
Since %ebx is not used, how about:
movl $0x60000001, %ebx /* CD, NW, PE = 1 */
#if CONFIG(INTEL_CBNT_SUPPORT)
#include <cpu/intel/msr.h>
/* Do not disable caching if the BootGuard ACM has set up CAR */
movl $MSR_BOOT_GUARD_SACM_INFO, %ecx
rdmsr
test $B_BOOT_GUARD_SACM_INFO_NEM_ENABLED, %eax
cmovne $0x01, %ebx /* PE = 1 */
#endif
movl %cr0, %eax
andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
orl %ebx, %eax
movl %eax, %cr0
I didn't test this
File src/include/cpu/intel/msr.h:
https://review.coreboot.org/c/coreboot/+/54010/comment/c657f11a_6e7afbf1
PS2, Line 17:
For consistency with the other definitions, could you please indent these with tabs?
https://review.coreboot.org/c/coreboot/+/54010/comment/4bebe61c_9a6ea39b
PS2, Line 18:
nit: the bitfield macros for the other MSRs have an additional space after `#define`
https://review.coreboot.org/c/coreboot/+/54010/comment/d247cf13_b70ab4e1
PS2, Line 23: (1 << 32)
Isn't this shift undefined behavior?
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Change subject: doc/releases/coreboot-4.14: Add x86 bootblock and ACPI GNVS changes
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Patch Set 2: Code-Review+2
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Change subject: docs: correct and rewrite documentation regarding n/c / unused pads
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Patch Set 13: Code-Review+1
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54003 )
Change subject: Documentation/releases: Fill in coreboot 4.14 release notes
......................................................................
Patch Set 1:
(2 comments)
Patchset:
PS1:
> I'm well aware, yes.
CB:54008 as well
File Documentation/releases/coreboot-4.14-relnotes.md:
https://review.coreboot.org/c/coreboot/+/54003/comment/43a28dda_02d6ff72
PS1, Line 123: ### Add significant changes here
> yes, but that part of the file will be a merge conflict area anyway (e.g. […]
Alright, CB:54008 would also conflict
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Change subject: doc/relnotes/4.14: add Intel Xeon-SP support status change
......................................................................
Patch Set 6: Code-Review+1
(1 comment)
File Documentation/releases/coreboot-4.14-relnotes.md:
https://review.coreboot.org/c/coreboot/+/52735/comment/5528ec74_6f310789
PS6, Line 76: [1] https://www.intel.in/content/www/in/en/products/details/processors/xeon/sca…
nit: I'd use the en_US page:
https://www.intel.com/content/www/us/en/products/details/processors/xeon/sc…
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Hello build bot (Jenkins), Christian Walter, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52971
to look at the new patch set (#2).
Change subject: 3rdparty/intel-sec-tools: Update submodule pointer
......................................................................
3rdparty/intel-sec-tools: Update submodule pointer
Some changes:
- bg-prov got renamed to cbnt-prov
- cbfs support was added which means that providing IBB.Base/Size
separatly is not required anymore. Also fspt.bin gets added as an
IBB to secure the root of trust.
Change-Id: I20379e9723fa18e0ebfb0622c050524d4e6d2717
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M 3rdparty/intel-sec-tools
M src/security/intel/cbnt/Makefile.inc
2 files changed, 4 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/52971/2
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Change subject: UPDATE 3rdparty/intel-sec-tools
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52971/comment/84b5b230_6e6436f5
PS1, Line 7: UPDATE 3rdparty/intel-sec-tools
> There's no need to shout (uppercase text): […]
Done
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