coreboot-gerrit May 2021

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Change in coreboot[master]: northbridge/amd/pi/00630F01: Remove unused directory and code
by Felix Held (Code Review) 09 May '21

09 May '21

Attention is currently required from: Michał Żygowski, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53992 ) Change subject: northbridge/amd/pi/00630F01: Remove unused directory and code ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: there's also a cpu directory for this family. but this is something for after the release anyway -- To view, visit https://review.coreboot.org/c/coreboot/+/53992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85a68f8fdb422ccfc80a5b85d47950e25cfff6df Gerrit-Change-Number: 53992 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Sun, 09 May 2021 18:17:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/amd/agesa/acpi_tables.c: Remove 00630F01 occurrence
by Felix Held (Code Review) 09 May '21

09 May '21

Attention is currently required from: Michał Żygowski, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53995 ) Change subject: drivers/amd/agesa/acpi_tables.c: Remove 00630F01 occurrence ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: let's wait with removing unused chipset code until after the release -- To view, visit https://review.coreboot.org/c/coreboot/+/53995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b7ea886c4116ee2437e00639956ac9c3b0a9e48 Gerrit-Change-Number: 53995 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Sun, 09 May 2021 18:16:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Generate PCI GPP ACPI names
by Felix Held (Code Review) 09 May '21

09 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52870 ) Change subject: soc/amd/cezanne: Generate PCI GPP ACPI names ...................................................................... soc/amd/cezanne: Generate PCI GPP ACPI names We can generate the names, so there is no need to hard code a table. This will make the code more generic so it can be reused with picasso in the future. BUG=b:184766519 TEST=Dump guybrush ACPI table and verify it looks correct. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I5134d1dba4fcb9ce8cc4bfad1c619331a95f3b11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52870 Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/pcie_gpp.c 1 file changed, 9 insertions(+), 31 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/cezanne/pcie_gpp.c b/src/soc/amd/cezanne/pcie_gpp.c index 283470b..58c7761 100644 --- a/src/soc/amd/cezanne/pcie_gpp.c +++ b/src/soc/amd/cezanne/pcie_gpp.c @@ -11,43 +11,21 @@ #include <device/pci_ids.h> #include <device/pciexp.h> #include <soc/pci_devs.h> +#include <stdio.h> +#include <stdlib.h> static const char *pcie_gpp_acpi_name(const struct device *dev) { + char *name; + if (dev->path.type != DEVICE_PATH_PCI) return NULL; - switch (dev->path.pci.devfn) { - case PCIE_GPP_1_0_DEVFN: - return "GP10"; - case PCIE_GPP_1_1_DEVFN: - return "GP11"; - case PCIE_GPP_1_2_DEVFN: - return "GP12"; - case PCIE_GPP_2_0_DEVFN: - return "GP20"; - case PCIE_GPP_2_1_DEVFN: - return "GP21"; - case PCIE_GPP_2_2_DEVFN: - return "GP22"; - case PCIE_GPP_2_3_DEVFN: - return "GP23"; - case PCIE_GPP_2_4_DEVFN: - return "GP24"; - case PCIE_GPP_2_5_DEVFN: - return "GP25"; - case PCIE_GPP_2_6_DEVFN: - return "GP26"; - case PCIE_ABC_A_DEVFN: - return "GPPA"; - case PCIE_GPP_B_DEVFN: - return "GPPB"; - case PCIE_GPP_C_DEVFN: - return "GPPC"; - default: - printk(BIOS_ERR, "%s: Unhanded devfn 0x%x\n", __func__, dev->path.pci.devfn); - return NULL; - } + name = malloc(ACPI_NAME_BUFFER_SIZE); + snprintf(name, ACPI_NAME_BUFFER_SIZE, "GP%02x", dev->path.pci.devfn); + name[4] = '\0'; + + return name; } static void acpi_device_write_gpp_pci_dev(const struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/52870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5134d1dba4fcb9ce8cc4bfad1c619331a95f3b11 Gerrit-Change-Number: 52870 Gerrit-PatchSet: 10 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: Enable GNB IO-APIC _PRT
by Felix Held (Code Review) 09 May '21

09 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53936 ) Change subject: soc/amd/cezanne: Enable GNB IO-APIC _PRT ...................................................................... soc/amd/cezanne: Enable GNB IO-APIC _PRT We can now use the GNB IO-APIC. BUG=b:184766519 TEST=Boot guybrush to OS with `pci=nomsi amd_iommu=off noapic` Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I4df5a4583f14044d2efcde3a9de9dd85e898a11d Reviewed-on: https://review.coreboot.org/c/coreboot/+/53936 Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/pcie_gpp.c 1 file changed, 1 insertion(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/cezanne/pcie_gpp.c b/src/soc/amd/cezanne/pcie_gpp.c index 16c6b23..283470b 100644 --- a/src/soc/amd/cezanne/pcie_gpp.c +++ b/src/soc/amd/cezanne/pcie_gpp.c @@ -65,8 +65,7 @@ acpigen_write_ADR_pci_device(dev); acpigen_write_STA(acpi_device_status(dev)); - /* b/187083211 - Enable GNB IO-APIC */ - acpigen_write_pci_FCH_PRT(dev); + acpigen_write_pci_GNB_PRT(dev); acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ -- To view, visit https://review.coreboot.org/c/coreboot/+/53936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4df5a4583f14044d2efcde3a9de9dd85e898a11d Gerrit-Change-Number: 53936 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: add GNB IOAPIC support
by Felix Held (Code Review) 09 May '21

09 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52905 ) Change subject: soc/amd/cezanne: add GNB IOAPIC support ...................................................................... soc/amd/cezanne: add GNB IOAPIC support To configure and enable the IOAPIC in the graphics and northbridge (GNB) container, FSP needs to write an undocumented register, so pass the GNB IOAPIC MMIO base address to make it show up at that address. BUG=b:187083211 TEST=Boot guybrush and see IO-APIC initialized IOAPIC[0]: apic_id 16, version 33, address 0xfec00000, GSI 0-23 IOAPIC[1]: apic_id 17, version 33, address 0xfec01000, GSI 24-55 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I1e127ce500d052783f0a6e13fb2ad16a8e408b0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52905 Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/acpi.c M src/soc/amd/cezanne/fsp_m_params.c M src/soc/amd/cezanne/include/soc/iomap.h M src/soc/amd/cezanne/root_complex.c 4 files changed, 29 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index fd11589..180a1e5 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -28,7 +28,8 @@ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, FCH_IOAPIC_ID, IO_APIC_ADDR, 0); - /* TODO: Add GNB-IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, + GNB_IOAPIC_ID, GNB_IO_APIC_ADDR, IO_APIC_INTERRUPTS); current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *)current, diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 8da38ff..4aff7e0 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/apob_cache.h> +#include <amdblocks/ioapic.h> #include <amdblocks/memmap.h> #include <assert.h> #include <console/uart.h> @@ -50,6 +51,13 @@ fill_ddi_descriptors(mcfg, fsp_ddi, num_ddi); } +static void fsp_assign_ioapic_upds(FSP_M_CONFIG *mcfg) +{ + mcfg->gnb_ioapic_base = GNB_IO_APIC_ADDR; + mcfg->gnb_ioapic_id = GNB_IOAPIC_ID; + mcfg->fch_ioapic_id = FCH_IOAPIC_ID; +} + void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSP_M_CONFIG *mcfg = &mupd->FspmConfig; @@ -129,4 +137,5 @@ config->telemetry_vddcrsocoffset; fsp_fill_pcie_ddi_descriptors(mcfg); + fsp_assign_ioapic_upds(mcfg); } diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index 83bb817..486e3cf 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -11,6 +11,8 @@ #if ENV_X86 /* MMIO Ranges */ +/* IO_APIC_ADDR defined in arch/x86 0xfec00000 */ +#define GNB_IO_APIC_ADDR 0xfec01000 #define SPI_BASE_ADDRESS 0xfec10000 #if CONFIG(HPET_ADDRESS_OVERRIDE) diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index ba84681..5d021ba 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/acpi.h> +#include <amdblocks/ioapic.h> #include <amdblocks/memmap.h> +#include <arch/ioapic.h> #include <cbmem.h> #include <console/console.h> #include <cpu/amd/msr.h> @@ -9,6 +11,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <fsp/util.h> +#include <soc/iomap.h> #include <stdint.h> /* @@ -70,6 +73,7 @@ unsigned int idx = 0; const struct hob_header *hob = fsp_get_hob_list(); const struct hob_resource *res; + struct resource *gnb_apic; uintptr_t early_reserved_dram_start, early_reserved_dram_end; const struct memmap_early_dram *e = memmap_get_early_dram_usage(); @@ -129,6 +133,17 @@ printk(BIOS_ERR, "Error: failed to set resources for type %d\n", res->type); } + + /* GNB IOAPIC resource */ + gnb_apic = new_resource(dev, GNB_IO_APIC_ADDR); + gnb_apic->base = GNB_IO_APIC_ADDR; + gnb_apic->size = 0x00001000; + gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void root_complex_init(struct device *dev) +{ + setup_ioapic((u8 *)GNB_IO_APIC_ADDR, GNB_IOAPIC_ID); } static void root_complex_fill_ssdt(const struct device *device) @@ -145,6 +160,7 @@ .read_resources = read_resources, .set_resources = noop_set_resources, .enable_resources = pci_dev_enable_resources, + .init = root_complex_init, .acpi_name = gnb_acpi_name, .acpi_fill_ssdt = root_complex_fill_ssdt, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/52905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e127ce500d052783f0a6e13fb2ad16a8e408b0e Gerrit-Change-Number: 52905 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Populate PIC IRQ data
by Felix Held (Code Review) 09 May '21

09 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52915 ) Change subject: mb/google/guybrush: Populate PIC IRQ data ...................................................................... mb/google/guybrush: Populate PIC IRQ data The PIC IRQs are required so we can correctly set up the PCI_INT registers. This only matters when booting in PIC mode. We don't need to set the IO-APIC registers since the linux kernel will auto-assign those to reduce conflicts. BUG=b:184766519 TEST=Boot guybrush with `pci=nomsi,noacpi amd_iommu=off noapic` and verify xhci and graphics continue to work. $ cat /proc/interrupts 12: 285064 XT-PIC nvme0q0, nvme0q1, rtw88_pci 13: 100000 XT-PIC xhci-hcd:usb1 14: 4032 XT-PIC amdgpu, xhci-hcd:usb3 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I1d66ccd08a86a64242dbc909c57ff9685828f61f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52915 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/guybrush/mainboard.c 1 file changed, 8 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Felix Held: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c index b406bf3..def0c63 100644 --- a/src/mainboard/google/guybrush/mainboard.c +++ b/src/mainboard/google/guybrush/mainboard.c @@ -47,14 +47,14 @@ uint8_t pic_irq_num; uint8_t apic_irq_num; } guybrush_fch[] = { - { PIRQ_A, PIRQ_NC, PIRQ_NC }, - { PIRQ_B, PIRQ_NC, PIRQ_NC }, - { PIRQ_C, PIRQ_NC, PIRQ_NC }, - { PIRQ_D, PIRQ_NC, PIRQ_NC }, - { PIRQ_E, PIRQ_NC, PIRQ_NC }, - { PIRQ_F, PIRQ_NC, PIRQ_NC }, - { PIRQ_G, PIRQ_NC, PIRQ_NC }, - { PIRQ_H, PIRQ_NC, PIRQ_NC }, + { PIRQ_A, 12, PIRQ_NC }, + { PIRQ_B, 14, PIRQ_NC }, + { PIRQ_C, 15, PIRQ_NC }, + { PIRQ_D, 12, PIRQ_NC }, + { PIRQ_E, 14, PIRQ_NC }, + { PIRQ_F, 15, PIRQ_NC }, + { PIRQ_G, 12, PIRQ_NC }, + { PIRQ_H, 14, PIRQ_NC }, { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ }, { PIRQ_SD, PIRQ_NC, PIRQ_NC }, -- To view, visit https://review.coreboot.org/c/coreboot/+/52915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d66ccd08a86a64242dbc909c57ff9685828f61f Gerrit-Change-Number: 52915 Gerrit-PatchSet: 9 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: Generate PCI routing table
by Felix Held (Code Review) 09 May '21

09 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51556 ) Change subject: soc/amd/cezanne: Generate PCI routing table ...................................................................... soc/amd/cezanne: Generate PCI routing table Use the new acpigen_write_PRT to write the _PRT for each PCI bridge. BUG=b:184766519 TEST=Dump guybrush ACPI table and verify it looks correct. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Idb559335435a95e73640e6d7fb224e16e0592326 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51556 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/acpi/soc.asl M src/soc/amd/cezanne/pcie_gpp.c 2 files changed, 30 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/cezanne/acpi/soc.asl b/src/soc/amd/cezanne/acpi/soc.asl index 5039ca1..e603307 100644 --- a/src/soc/amd/cezanne/acpi/soc.asl +++ b/src/soc/amd/cezanne/acpi/soc.asl @@ -12,6 +12,8 @@ #include "pci_int_defs.asl" + #include <soc/amd/common/acpi/pci_int.asl> + #include "mmio.asl" #include "pci0.asl" diff --git a/src/soc/amd/cezanne/pcie_gpp.c b/src/soc/amd/cezanne/pcie_gpp.c index 4ab206b..16c6b23 100644 --- a/src/soc/amd/cezanne/pcie_gpp.c +++ b/src/soc/amd/cezanne/pcie_gpp.c @@ -1,6 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <acpi/acpi_device.h> +#include <acpi/acpigen.h> +#include <acpi/acpigen_pci.h> +#include <amdblocks/amd_pci_util.h> +#include <assert.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -46,6 +50,28 @@ } } +static void acpi_device_write_gpp_pci_dev(const struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + const char *name = acpi_device_name(dev); + + assert(dev->path.type == DEVICE_PATH_PCI); + assert(name); + assert(scope); + + acpigen_write_scope(scope); + acpigen_write_device(name); + + acpigen_write_ADR_pci_device(dev); + acpigen_write_STA(acpi_device_status(dev)); + + /* b/187083211 - Enable GNB IO-APIC */ + acpigen_write_pci_FCH_PRT(dev); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + static struct device_operations internal_pcie_gpp_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, @@ -53,7 +79,7 @@ .scan_bus = pci_scan_bridge, .reset_bus = pci_bus_reset, .acpi_name = pcie_gpp_acpi_name, - .acpi_fill_ssdt = acpi_device_write_pci_dev, + .acpi_fill_ssdt = acpi_device_write_gpp_pci_dev, }; static const struct pci_driver internal_pcie_gpp_driver __pci_driver = { @@ -69,7 +95,7 @@ .scan_bus = pciexp_scan_bridge, .reset_bus = pci_bus_reset, .acpi_name = pcie_gpp_acpi_name, - .acpi_fill_ssdt = acpi_device_write_pci_dev, + .acpi_fill_ssdt = acpi_device_write_gpp_pci_dev, }; static const unsigned short external_pci_gpp_ids[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/51556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb559335435a95e73640e6d7fb224e16e0592326 Gerrit-Change-Number: 51556 Gerrit-PatchSet: 11 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: Populate PCI_INTR registers
by Felix Held (Code Review) 09 May '21

09 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52914 ) Change subject: soc/amd/cezanne: Populate PCI_INTR registers ...................................................................... soc/amd/cezanne: Populate PCI_INTR registers This uses the new FSP PCI methods to pull the routing table and populate the pirq data structure. BUG=b:184766519 TEST=Boot guybrush and verify we get Got IRQ 0x1F (disabled) messages Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ie21229cc2fb4fd5b85c0b9e933f7b43af24864b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52914 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/fch.c 2 files changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 1d769be..dafc26f 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -61,6 +61,7 @@ select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE + select SOC_AMD_COMMON_FSP_PCI select SSE2 select UDK_2017_BINDING select X86_AMD_FIXED_MTRRS diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index 88265ab..028ffec 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -131,6 +131,12 @@ { /* Write PCI_INTR regs 0xC00/0xC01 */ write_pci_int_table(); + + /* pirq_data is consumed by `write_pci_cfg_irqs` */ + populate_pirq_data(); + + /* Write IRQs for all devicetree enabled devices */ + write_pci_cfg_irqs(); } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/52914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie21229cc2fb4fd5b85c0b9e933f7b43af24864b0 Gerrit-Change-Number: 52914 Gerrit-PatchSet: 8 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/fsp/pci: Add helper methods for PCI IRQ table
by Felix Held (Code Review) 09 May '21

09 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52911 ) Change subject: soc/amd/common/fsp/pci: Add helper methods for PCI IRQ table ...................................................................... soc/amd/common/fsp/pci: Add helper methods for PCI IRQ table These are helper methods for interacting with the AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID. BUG=b:184766519, b:184766197 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Id03d0b74ca12e7bcee11f8d13b0e802861c13923 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52911 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- A src/soc/amd/common/fsp/pci/Kconfig A src/soc/amd/common/fsp/pci/Makefile.inc A src/soc/amd/common/fsp/pci/pci_routing_info.c 3 files changed, 51 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/common/fsp/pci/Kconfig b/src/soc/amd/common/fsp/pci/Kconfig new file mode 100644 index 0000000..9d6596c --- /dev/null +++ b/src/soc/amd/common/fsp/pci/Kconfig @@ -0,0 +1,5 @@ +config SOC_AMD_COMMON_FSP_PCI + bool + select SOC_AMD_COMMON_BLOCK_PCI + help + This option enabled FSP to provide common PCI functions. diff --git a/src/soc/amd/common/fsp/pci/Makefile.inc b/src/soc/amd/common/fsp/pci/Makefile.inc new file mode 100644 index 0000000..cc1377a --- /dev/null +++ b/src/soc/amd/common/fsp/pci/Makefile.inc @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_FSP_PCI),y) + +ramstage-y += pci_routing_info.c + +endif # CONFIG_SOC_AMD_COMMON_FSP_PCI diff --git a/src/soc/amd/common/fsp/pci/pci_routing_info.c b/src/soc/amd/common/fsp/pci/pci_routing_info.c new file mode 100644 index 0000000..21423da --- /dev/null +++ b/src/soc/amd/common/fsp/pci/pci_routing_info.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/amd_pci_util.h> +#include <console/console.h> +#include <device/pci_def.h> +#include <fsp/util.h> +#include <FspGuids.h> +#include <types.h> + +const struct pci_routing_info *get_pci_routing_table(size_t *entries) +{ + static const struct pci_routing_info *routing_table; + static size_t routing_table_entries; + + size_t hob_size = 0; + + if (routing_table) { + *entries = routing_table_entries; + return routing_table; + } + + routing_table = fsp_find_extension_hob_by_guid(AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID.b, + &hob_size); + + if (routing_table == NULL || hob_size == 0) { + printk(BIOS_ERR, "Couldn't find PCIe routing HOB.\n"); + return NULL; + } + + routing_table_entries = hob_size / sizeof(struct pci_routing_info); + + for (size_t i = 0; i < routing_table_entries; ++i) { + printk(BIOS_DEBUG, "%02x.%x: group: %u, swizzle: %u, irq: %u\n", + PCI_SLOT(routing_table[i].devfn), PCI_FUNC(routing_table[i].devfn), + routing_table[i].group, routing_table[i].swizzle, routing_table[i].irq); + } + + *entries = routing_table_entries; + + return routing_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/52911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id03d0b74ca12e7bcee11f8d13b0e802861c13923 Gerrit-Change-Number: 52911 Gerrit-PatchSet: 8 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso/pci_gpp: Switch to using acpigen_write_pci_GNB_PRT
by Felix Held (Code Review) 09 May '21

09 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53935 ) Change subject: soc/amd/picasso/pci_gpp: Switch to using acpigen_write_pci_GNB_PRT ...................................................................... soc/amd/picasso/pci_gpp: Switch to using acpigen_write_pci_GNB_PRT We can now delete the picasso specific version. BUG=b:184766519 TEST=Build zork and verify SSDT has not changed Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ic79014e83c9ff63cc7a6757b16764ae23b36984f Reviewed-on: https://review.coreboot.org/c/coreboot/+/53935 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/picasso/pcie_gpp.c 1 file changed, 1 insertion(+), 63 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/picasso/pcie_gpp.c b/src/soc/amd/picasso/pcie_gpp.c index 15174f6..eabaa77 100644 --- a/src/soc/amd/picasso/pcie_gpp.c +++ b/src/soc/amd/picasso/pcie_gpp.c @@ -60,68 +60,6 @@ return NULL; } -static void acpigen_write_PRT(const struct device *dev) -{ - char link_template[] = "\\_SB.INTX"; - unsigned int irq_index; - - const struct pci_routing_info *pci_routing = get_pci_routing_info(dev->path.pci.devfn); - if (!pci_routing) { - printk(BIOS_ERR, "PCI routing table not found for %s\n", dev_path(dev)); - return; - } - - acpigen_write_method("_PRT", 0); - - /* If (PICM) */ - acpigen_write_if(); - acpigen_emit_namestring("PICM"); - - /* Return (Package{...}) */ - acpigen_emit_byte(RETURN_OP); - - acpigen_write_package(4); /* Package - APIC Routing */ - for (unsigned int i = 0; i < 4; ++i) { - irq_index = pci_calculate_irq(pci_routing, i); - - acpigen_write_package(4); - /* There is only one device attached to the bridge */ - acpigen_write_dword(0x0000FFFF); - acpigen_write_byte(i); - acpigen_write_byte(0); /* Source: GSI */ - /* GNB IO-APIC is located after the FCH IO-APIC */ - acpigen_write_dword(IO_APIC_INTERRUPTS + irq_index); - acpigen_pop_len(); - } - acpigen_pop_len(); /* Package - APIC Routing */ - - /* Else */ - acpigen_write_else(); - - /* Return (Package{...}) */ - acpigen_emit_byte(RETURN_OP); - - acpigen_write_package(4); /* Package - PIC Routing */ - for (unsigned int i = 0; i < 4; ++i) { - irq_index = pci_calculate_irq(pci_routing, i); - - link_template[8] = 'A' + (irq_index % 8); - - acpigen_write_package(4); - /* There is only one device attached to the bridge */ - acpigen_write_dword(0x0000FFFF); - acpigen_write_byte(i); - acpigen_emit_namestring(link_template); - acpigen_write_dword(0); - acpigen_pop_len(); - } - acpigen_pop_len(); /* Package - PIC Routing */ - - acpigen_pop_len(); /* End Else */ - - acpigen_pop_len(); /* Method */ -} - /* * This function writes a PCI device with _ADR, _STA, and _PRT objects: * Example: @@ -230,7 +168,7 @@ acpigen_write_ADR_pci_device(dev); acpigen_write_STA(acpi_device_status(dev)); - acpigen_write_PRT(dev); + acpigen_write_pci_GNB_PRT(dev); acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ -- To view, visit https://review.coreboot.org/c/coreboot/+/53935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic79014e83c9ff63cc7a6757b16764ae23b36984f Gerrit-Change-Number: 53935 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit May 2021