coreboot-gerrit May 2021

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Change in coreboot[master]: soc/amd/common/block/pci: Implement acpigen_write_pci_{GNB,FCH}_PRT
by Felix Held (Code Review) 09 May '21

09 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52917 ) Change subject: soc/amd/common/block/pci: Implement acpigen_write_pci_{GNB,FCH}_PRT ...................................................................... soc/amd/common/block/pci: Implement acpigen_write_pci_{GNB,FCH}_PRT This is loosely based off of picasso/pcie_gpp.c. This version uses the acpigen_write_PRT_X methods to write the actual records. There are also two functions, 1 for using the GNB, and one for using the FCH. The FCH one is useful when the GNB IO-APIC has not been initialized. BUG=b:184766519 TEST=Dump guybrush ACPI and verify it looks correct Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I926430074acb969ceb11fdb60ab56dcf91ac4c76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52917 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/include/amdblocks/amd_pci_util.h M src/soc/amd/common/block/pci/Makefile.inc A src/soc/amd/common/block/pci/acpi_prt.c 3 files changed, 217 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h index 83922c9..0a4061f 100644 --- a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h +++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h @@ -5,6 +5,7 @@ #include <types.h> #include <soc/amd_pci_int_defs.h> +#include <device/device.h> /* FCH index/data registers */ #define PCI_INTR_INDEX 0xc00 @@ -60,4 +61,7 @@ unsigned int pci_calculate_irq(const struct pci_routing_info *routing_info, unsigned int pin); +void acpigen_write_pci_GNB_PRT(const struct device *dev); +void acpigen_write_pci_FCH_PRT(const struct device *dev); + #endif /* AMD_BLOCK_PCI_UTIL_H */ diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc index 5df641b..8c7a989 100644 --- a/src/soc/amd/common/block/pci/Makefile.inc +++ b/src/soc/amd/common/block/pci/Makefile.inc @@ -1,5 +1,10 @@ -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI) += amd_pci_util.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI) += pci_routing_info.c +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI),y) + +ramstage-y += amd_pci_util.c +ramstage-y += pci_routing_info.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_prt.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_PCI ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF),y) diff --git a/src/soc/amd/common/block/pci/acpi_prt.c b/src/soc/amd/common/block/pci/acpi_prt.c new file mode 100644 index 0000000..c4c50f5 --- /dev/null +++ b/src/soc/amd/common/block/pci/acpi_prt.c @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +#include <acpi/acpigen.h> +#include <acpi/acpigen_pci.h> +#include <amdblocks/amd_pci_util.h> +#include <arch/ioapic.h> +#include <console/console.h> +#include <device/device.h> + +static void acpigen_write_PRT_GSI(const struct pci_routing_info *routing_info) +{ + unsigned int irq; + + acpigen_write_package(4); /* Package - APIC Routing */ + for (unsigned int i = 0; i < 4; ++i) { + /* GNB IO-APIC is located after the FCH IO-APIC */ + irq = IO_APIC_INTERRUPTS; + irq += pci_calculate_irq(routing_info, i); + + acpigen_write_PRT_GSI_entry( + 0, /* There is only one device attached to the bridge */ + i, /* pin */ + irq); + } + acpigen_pop_len(); /* Package - APIC Routing */ +} + +static void acpigen_write_PRT_PIC(const struct pci_routing_info *routing_info) +{ + unsigned int irq; + char link_template[] = "\\_SB.INTX"; + + acpigen_write_package(4); /* Package - PIC Routing */ + for (unsigned int i = 0; i < 4; ++i) { + irq = pci_calculate_irq(routing_info, i); + + link_template[8] = 'A' + (irq % 8); + + acpigen_write_PRT_source_entry( + 0, /* There is only one device attached to the bridge */ + i, /* pin */ + link_template /* Source */, + 0 /* Source Index */); + } + acpigen_pop_len(); /* Package - PIC Routing */ +} + +/* + * This method writes a PCI _PRT table that uses the GNB IO-APIC / PIC : + * Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + * { + * If (PICM) + * { + * Return (Package (0x04) + * { + * Package (0x04) + * { + * 0x0000FFFF, + * 0x00, + * 0x00, + * 0x00000034 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x01, + * 0x00, + * 0x00000035 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x02, + * 0x00, + * 0x00000036 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x03, + * 0x00, + * 0x00000037 + * } + * }) + * } + * Else + * { + * Return (Package (0x04) + * { + * Package (0x04) + * { + * 0x0000FFFF, + * 0x00, + * \_SB.INTA, + * 0x00000000 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x01, + * \_SB.INTB, + * 0x00000000 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x02, + * \_SB.INTC, + * 0x00000000 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x03, + * \_SB.INTD, + * 0x00000000 + * } + * }) + * } + * } + */ +void acpigen_write_pci_GNB_PRT(const struct device *dev) +{ + const struct pci_routing_info *routing_info = + get_pci_routing_info(dev->path.pci.devfn); + + if (!routing_info) + return; + + acpigen_write_method("_PRT", 0); + + /* If (PICM) */ + acpigen_write_if(); + acpigen_emit_namestring("PICM"); + + /* Return (Package{...}) */ + acpigen_emit_byte(RETURN_OP); + acpigen_write_PRT_GSI(routing_info); + + /* Else */ + acpigen_write_else(); + + /* Return (Package{...}) */ + acpigen_emit_byte(RETURN_OP); + acpigen_write_PRT_PIC(routing_info); + + acpigen_pop_len(); /* End Else */ + + acpigen_pop_len(); /* Method */ +} + + /* + * This method writes a PCI _PRT table that uses the FCH IO-APIC / PIC : + * Name (_PRT, Package (0x04) + * { + * Package (0x04) + * { + * 0x0000FFFF, + * 0x00, + * \_SB.INTA, + * 0x00000000 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x01, + * \_SB.INTB, + * 0x00000000 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x02, + * \_SB.INTC, + * 0x00000000 + * }, + * + * Package (0x04) + * { + * 0x0000FFFF, + * 0x03, + * \_SB.INTD, + * 0x00000000 + * } + * }) + */ +void acpigen_write_pci_FCH_PRT(const struct device *dev) +{ + const struct pci_routing_info *routing_info = + get_pci_routing_info(dev->path.pci.devfn); + + if (!routing_info) + return; + + acpigen_write_name("_PRT"); + acpigen_write_PRT_PIC(routing_info); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/52917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I926430074acb969ceb11fdb60ab56dcf91ac4c76 Gerrit-Change-Number: 52917 Gerrit-PatchSet: 8 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/{picasso,common/blocks/pci}: Move populate_pirq_data
by Felix Held (Code Review) 09 May '21

09 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52913 ) Change subject: soc/amd/{picasso,common/blocks/pci}: Move populate_pirq_data ...................................................................... soc/amd/{picasso,common/blocks/pci}: Move populate_pirq_data The method now dynamically allocates the pirq structure and uses the get_pci_routing_table method. BUG=b:184766519 TEST=Build guybrush and verify picasso SSDT has not changed. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I297fc3ca7227fb4794ac70bd046ce2f93da8b869 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52913 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/include/amdblocks/amd_pci_util.h M src/soc/amd/common/block/pci/pci_routing_info.c M src/soc/amd/picasso/pcie_gpp.c 3 files changed, 35 insertions(+), 30 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h index b9cd140..83922c9 100644 --- a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h +++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h @@ -51,7 +51,6 @@ uint8_t irq; } __packed; -/* Implemented by the SoC */ void populate_pirq_data(void); /* Implemented by the SoC */ diff --git a/src/soc/amd/common/block/pci/pci_routing_info.c b/src/soc/amd/common/block/pci/pci_routing_info.c index e0a6964..ac72553 100644 --- a/src/soc/amd/common/block/pci/pci_routing_info.c +++ b/src/soc/amd/common/block/pci/pci_routing_info.c @@ -3,6 +3,7 @@ #include <amdblocks/amd_pci_util.h> #include <console/console.h> #include <device/pci_def.h> +#include <stdlib.h> #include <types.h> enum pcie_swizzle_pin { @@ -55,3 +56,37 @@ return irq; } + +void populate_pirq_data(void) +{ + const struct pci_routing_info *routing_table, *routing_entry; + size_t entries = 0; + struct pirq_struct *pirq; + unsigned int irq; + + routing_table = get_pci_routing_table(&entries); + + if (!routing_table || !entries) + return; + + pirq = calloc(entries, sizeof(*pirq)); + + if (!pirq) { + printk(BIOS_ERR, "%s: Allocation failed\n", __func__); + return; + } + + for (size_t i = 0; i < entries; ++i) { + routing_entry = &routing_table[i]; + + pirq[i].devfn = routing_entry->devfn; + for (size_t j = 0; j < 4; ++j) { + irq = pci_calculate_irq(routing_entry, j); + + pirq[i].PIN[j] = irq % 8; + } + } + + pirq_data_ptr = pirq; + pirq_data_size = entries; +} diff --git a/src/soc/amd/picasso/pcie_gpp.c b/src/soc/amd/picasso/pcie_gpp.c index f609875..15174f6 100644 --- a/src/soc/amd/picasso/pcie_gpp.c +++ b/src/soc/amd/picasso/pcie_gpp.c @@ -31,35 +31,6 @@ return pci_routing_table; } -/* - * This data structure is populated from the raw data above. It is used - * by amd/common/block/pci/amd_pci_util to write the PCI_INT_LINE register - * to each PCI device. - */ -static struct pirq_struct pirq_data[ARRAY_SIZE(pci_routing_table)]; - -void populate_pirq_data(void) -{ - const struct pci_routing_info *pci_routing; - struct pirq_struct *pirq; - unsigned int irq_index; - - for (size_t i = 0; i < ARRAY_SIZE(pirq_data); ++i) { - pirq = &pirq_data[i]; - pci_routing = &pci_routing_table[i]; - - pirq->devfn = pci_routing->devfn; - for (size_t j = 0; j < 4; ++j) { - irq_index = pci_calculate_irq(pci_routing, j); - - pirq->PIN[j] = irq_index % 8; - } - } - - pirq_data_ptr = pirq_data; - pirq_data_size = ARRAY_SIZE(pirq_data); -} - static const char *pcie_gpp_acpi_name(const struct device *dev) { if (dev->path.type != DEVICE_PATH_PCI) -- To view, visit https://review.coreboot.org/c/coreboot/+/52913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I297fc3ca7227fb4794ac70bd046ce2f93da8b869 Gerrit-Change-Number: 52913 Gerrit-PatchSet: 9 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso: Migrate to struct pci_routing_info
by Felix Held (Code Review) 09 May '21

09 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53923 ) Change subject: soc/amd/picasso: Migrate to struct pci_routing_info ...................................................................... soc/amd/picasso: Migrate to struct pci_routing_info This allows us to use the common get_pci_routing_info and pci_calculate_irq. The IRQ field in the struct was also filled in from the PPR. BUG=b:184766519 TEST=Boot ezkinil and verify SSDT table is identical. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I16d90d8c89bfcf48878c0741154290ebc52a4120 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53923 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/picasso/pcie_gpp.c 1 file changed, 21 insertions(+), 46 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/picasso/pcie_gpp.c b/src/soc/amd/picasso/pcie_gpp.c index 29dfe68..f609875 100644 --- a/src/soc/amd/picasso/pcie_gpp.c +++ b/src/soc/amd/picasso/pcie_gpp.c @@ -12,30 +12,24 @@ #include <soc/pci_devs.h> #include <stdio.h> -/** - * Each PCI bridge has its INTx lines routed to one of the 8 GNB IOAPIC PCI - * groups. Each group has 4 interrupts. The INTx lines can be swizzled before - * being routed to the IOAPIC. If the IOAPIC redirection entry is masked, the - * interrupt is reduced modulo 8 onto INT[A-H] and forwarded to the FCH IOAPIC. - **/ -struct pci_routing { - unsigned int devfn; - unsigned int group; - uint8_t pin[4]; +/* See AMD PPR 55570 - IOAPIC Initialization for the table that AGESA sets up */ +const struct pci_routing_info pci_routing_table[] = { + {PCIE_GPP_0_DEVFN, 0, PCI_SWIZZLE_ABCD, 0x10}, + {PCIE_GPP_1_DEVFN, 1, PCI_SWIZZLE_ABCD, 0x11}, + {PCIE_GPP_2_DEVFN, 2, PCI_SWIZZLE_ABCD, 0x12}, + {PCIE_GPP_3_DEVFN, 3, PCI_SWIZZLE_ABCD, 0x13}, + {PCIE_GPP_4_DEVFN, 4, PCI_SWIZZLE_ABCD, 0x10}, + {PCIE_GPP_5_DEVFN, 5, PCI_SWIZZLE_ABCD, 0x11}, + {PCIE_GPP_6_DEVFN, 6, PCI_SWIZZLE_ABCD, 0x12}, + {PCIE_GPP_A_DEVFN, 7, PCI_SWIZZLE_ABCD, 0x13}, + {PCIE_GPP_B_DEVFN, 7, PCI_SWIZZLE_CDAB, 0x0C}, }; -/* See AMD PPR 55570 - IOAPIC Initialization for the table that AGESA sets up */ -static const struct pci_routing pci_routing_table[] = { - {PCIE_GPP_0_DEVFN, 0, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, - {PCIE_GPP_1_DEVFN, 1, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, - {PCIE_GPP_2_DEVFN, 2, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, - {PCIE_GPP_3_DEVFN, 3, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, - {PCIE_GPP_4_DEVFN, 4, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, - {PCIE_GPP_5_DEVFN, 5, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, - {PCIE_GPP_6_DEVFN, 6, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, - {PCIE_GPP_A_DEVFN, 7, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, - {PCIE_GPP_B_DEVFN, 7, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B} }, -}; +const struct pci_routing_info *get_pci_routing_table(size_t *entries) +{ + *entries = ARRAY_SIZE(pci_routing_table); + return pci_routing_table; +} /* * This data structure is populated from the raw data above. It is used @@ -44,28 +38,9 @@ */ static struct pirq_struct pirq_data[ARRAY_SIZE(pci_routing_table)]; -static const struct pci_routing *get_pci_routing(unsigned int devfn) -{ - for (size_t i = 0; i < ARRAY_SIZE(pci_routing_table); ++i) { - if (devfn == pci_routing_table[i].devfn) - return &pci_routing_table[i]; - } - - return NULL; -} - -static unsigned int calculate_irq(const struct pci_routing *pci_routing, unsigned int i) -{ - unsigned int irq_index; - irq_index = pci_routing->group * 4; - irq_index += pci_routing->pin[i]; - - return irq_index; -} - void populate_pirq_data(void) { - const struct pci_routing *pci_routing; + const struct pci_routing_info *pci_routing; struct pirq_struct *pirq; unsigned int irq_index; @@ -75,7 +50,7 @@ pirq->devfn = pci_routing->devfn; for (size_t j = 0; j < 4; ++j) { - irq_index = calculate_irq(pci_routing, j); + irq_index = pci_calculate_irq(pci_routing, j); pirq->PIN[j] = irq_index % 8; } @@ -119,7 +94,7 @@ char link_template[] = "\\_SB.INTX"; unsigned int irq_index; - const struct pci_routing *pci_routing = get_pci_routing(dev->path.pci.devfn); + const struct pci_routing_info *pci_routing = get_pci_routing_info(dev->path.pci.devfn); if (!pci_routing) { printk(BIOS_ERR, "PCI routing table not found for %s\n", dev_path(dev)); return; @@ -136,7 +111,7 @@ acpigen_write_package(4); /* Package - APIC Routing */ for (unsigned int i = 0; i < 4; ++i) { - irq_index = calculate_irq(pci_routing, i); + irq_index = pci_calculate_irq(pci_routing, i); acpigen_write_package(4); /* There is only one device attached to the bridge */ @@ -157,7 +132,7 @@ acpigen_write_package(4); /* Package - PIC Routing */ for (unsigned int i = 0; i < 4; ++i) { - irq_index = calculate_irq(pci_routing, i); + irq_index = pci_calculate_irq(pci_routing, i); link_template[8] = 'A' + (irq_index % 8); -- To view, visit https://review.coreboot.org/c/coreboot/+/53923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16d90d8c89bfcf48878c0741154290ebc52a4120 Gerrit-Change-Number: 53923 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/pci: Introduce struct pci_routing_info
by Felix Held (Code Review) 09 May '21

09 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53922 ) Change subject: soc/amd/common/block/pci: Introduce struct pci_routing_info ...................................................................... soc/amd/common/block/pci: Introduce struct pci_routing_info This struct is similar to `struct pci_routing` defined in picasso/pcie_gpp.c. It additionally contains the irq used for the bridge and is structured in a way that the FSP can provide via HOB. The next set of CLs will migrate the pci routing functions used by picasso into common and enable pci routing table generation for cezanne. BUG=b:184766519 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I1a8d988d125f407f0aa7bc1722d432446aa9aff8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53922 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/include/amdblocks/amd_pci_util.h M src/soc/amd/common/block/pci/Makefile.inc A src/soc/amd/common/block/pci/pci_routing_info.c 3 files changed, 85 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h index 081741a..b9cd140 100644 --- a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h +++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h @@ -31,7 +31,34 @@ void write_pci_int_table(void); const struct irq_idx_name *sb_get_apic_reg_association(size_t *size); +enum pci_routing_swizzle { + PCI_SWIZZLE_ABCD = 0, + PCI_SWIZZLE_BCDA, + PCI_SWIZZLE_CDAB, + PCI_SWIZZLE_DABC, +}; + +/** + * Each PCI bridge has its INTx lines routed to one of the GNB IO-APIC PCI + * groups. Each group has 4 interrupts. The INTx lines can be swizzled before + * being routed to the IO-APIC. If the IO-APIC redirection entry is masked, the + * interrupt is reduced modulo 8 onto INT[A-H] and forwarded to the FCH IO-APIC. + **/ +struct pci_routing_info { + uint8_t devfn; + uint8_t group; + uint8_t swizzle; + uint8_t irq; +} __packed; + /* Implemented by the SoC */ void populate_pirq_data(void); +/* Implemented by the SoC */ +const struct pci_routing_info *get_pci_routing_table(size_t *entries); + +const struct pci_routing_info *get_pci_routing_info(unsigned int devfn); + +unsigned int pci_calculate_irq(const struct pci_routing_info *routing_info, unsigned int pin); + #endif /* AMD_BLOCK_PCI_UTIL_H */ diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc index 78453d4..5df641b 100644 --- a/src/soc/amd/common/block/pci/Makefile.inc +++ b/src/soc/amd/common/block/pci/Makefile.inc @@ -1,4 +1,5 @@ ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI) += amd_pci_util.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI) += pci_routing_info.c ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF),y) diff --git a/src/soc/amd/common/block/pci/pci_routing_info.c b/src/soc/amd/common/block/pci/pci_routing_info.c new file mode 100644 index 0000000..e0a6964 --- /dev/null +++ b/src/soc/amd/common/block/pci/pci_routing_info.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/amd_pci_util.h> +#include <console/console.h> +#include <device/pci_def.h> +#include <types.h> + +enum pcie_swizzle_pin { + PIN_A, + PIN_B, + PIN_C, + PIN_D, +}; + +static const uint8_t pcie_swizzle_table[][4] = { + {PIN_A, PIN_B, PIN_C, PIN_D}, + {PIN_B, PIN_C, PIN_D, PIN_A}, + {PIN_C, PIN_D, PIN_A, PIN_B}, + {PIN_D, PIN_A, PIN_B, PIN_C}, +}; + +const struct pci_routing_info *get_pci_routing_info(unsigned int devfn) +{ + const struct pci_routing_info *routing_info; + size_t entries = 0; + + routing_info = get_pci_routing_table(&entries); + + if (!routing_info || !entries) + return NULL; + + for (size_t i = 0; i < entries; ++i, ++routing_info) + if (routing_info->devfn == devfn) + return routing_info; + + printk(BIOS_ERR, "Failed to find PCIe routing info for dev: %#x, fn: %#x\n", + PCI_SLOT(devfn), PCI_FUNC(devfn)); + + return NULL; +} + +unsigned int pci_calculate_irq(const struct pci_routing_info *routing_info, + unsigned int pin) +{ + unsigned int irq; + + if (routing_info->swizzle >= ARRAY_SIZE(pcie_swizzle_table)) + die("%s: swizzle %u out of bounds\n", __func__, routing_info->swizzle); + + if (pin >= ARRAY_SIZE(pcie_swizzle_table[routing_info->swizzle])) + die("%s: pin %u out of bounds\n", __func__, pin); + + irq = routing_info->group * 4; + irq += pcie_swizzle_table[routing_info->swizzle][pin]; + + return irq; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/53922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a8d988d125f407f0aa7bc1722d432446aa9aff8 Gerrit-Change-Number: 53922 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/x86/smm: Fix typo
by Patrick Georgi (Code Review) 09 May '21

09 May '21

Attention is currently required from: Paul Menzel. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53926 ) Change subject: cpu/x86/smm: Fix typo ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/53926/comment/f64ea61e_9f7e1cf7 PS1, Line 7: cpu/x86/smm: Fix typo > … in comment That's kinda obvious from the patch, no? -- To view, visit https://review.coreboot.org/c/coreboot/+/53926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28f262078cf7f5ec4ed707639e845710a8cc56ea Gerrit-Change-Number: 53926 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sun, 09 May 2021 18:02:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: util/genbuild_h: Update IASL location finding code
by Martin Roth (Code Review) 09 May '21

09 May '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54001 ) Change subject: util/genbuild_h: Update IASL location finding code ...................................................................... util/genbuild_h: Update IASL location finding code Update the iasl path finding code to use XGCCPATH if it's set, and to look for iasl on the path if it's not set and not under util/crossgcc. On the jenkins builders, iasl is in the path, not in util/crossgcc/xgcc. On the systems of people who have multiple copies of coreboot, it makes sense to just have a single copy of the toolchain and define XGCCPATH in the environment to point to it. Previously, either of these situations resulted in a warning from the genbuild_h tool that iasl was not found under util/crossgcc, which was true, but not particularly relevant, and generated confusion. If xcompile already existed before make was run, the correct path would be found, but on an initial build, this check couldn't find iasl. BUG=None TEST=Build with iasl in /util/crossgcc/xgcc/bin, in the path and in a directory pointed to with XGCCPATH. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Ic2f8dca0be8bfb54d3c672fab6cf6f005bb394c3 --- M util/genbuild_h/genbuild_h.sh 1 file changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/54001/1 diff --git a/util/genbuild_h/genbuild_h.sh b/util/genbuild_h/genbuild_h.sh index 10ca0c5..c898fb6 100755 --- a/util/genbuild_h/genbuild_h.sh +++ b/util/genbuild_h/genbuild_h.sh @@ -5,6 +5,7 @@ DATE="" GITREV="" TIMESOURCE="" +XGCCPATH="${XGCCPATH:-util/crossgcc/xgcc/bin/}" export LANG=C export LC_ALL=C @@ -47,8 +48,15 @@ esac } -IASL=util/crossgcc/xgcc/bin/iasl +# Look for IASL in XGCCPATH and xcompile. Unfortunately, +# xcompile isn't available on the first build. +# If neither of those gives a valid iasl, check the path. +IASL="${XGCCPATH}iasl" eval $(grep ^IASL:= "$XCOMPILE" 2>/dev/null | sed s,:=,=,) +if [ ! -x "${IASL}" ]; then + IASL=$(command -v iasl) +fi +IASLVERSION="$(${IASL} -v | grep version | sed 's/.*version //')" >/dev/null #Print out the information that goes into build.h printf "/* build system definitions (autogenerated) */\n" @@ -72,5 +80,5 @@ printf "#define COREBOOT_DMI_DATE \"$(our_date "$DATE" +%m/%d/%Y)\"\n" printf "\n" printf "#define COREBOOT_COMPILE_TIME \"$(our_date "$DATE" +%T)\"\n" -printf "#define ASL_VERSION 0x%d\n" `$IASL -v | grep version | sed 's/.*version //'` +printf "#define ASL_VERSION 0x%d\n" "${IASLVERSION}" printf "#endif\n" -- To view, visit https://review.coreboot.org/c/coreboot/+/54001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2f8dca0be8bfb54d3c672fab6cf6f005bb394c3 Gerrit-Change-Number: 54001 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: [NOT WORKING] mb/gigabyte/ga-f2a55m-hd2: Add new mainboard
by build bot (Jenkins) (Code Review) 09 May '21

09 May '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54000 ) Change subject: [NOT WORKING] mb/gigabyte/ga-f2a55m-hd2: Add new mainboard ...................................................................... Patch Set 1: (1 comment) File src/mainboard/gigabyte/ga-f2a55m-hd2/OemCustomize.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118873): https://review.coreboot.org/c/coreboot/+/54000/comment/9ba9369e_a67554a1 PS1, Line 145: /*MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/54000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icba25c1066cbbb461a5d3ef22d68e8c89357f425 Gerrit-Change-Number: 54000 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 09 May 2021 17:11:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [NOT WORKING] mb/gigabyte/ga-f2a55m-hd2: Add new mainboard
by Angel Pons (Code Review) 09 May '21

09 May '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54000 ) Change subject: [NOT WORKING] mb/gigabyte/ga-f2a55m-hd2: Add new mainboard ...................................................................... [NOT WORKING] mb/gigabyte/ga-f2a55m-hd2: Add new mainboard This is a µATX mainboard with a FM2 socket and two DDR3 DIMM slots. Working: - Serial port - DIMM SPD map Not working: - AGESA memory initialisation coreboot-4.13-3633-g5a157cd000 Sat May 8 20:38:53 UTC 2021 bootblock starting (log level: 8)... FMAP: Found "FLASH" version 1.1 at 0x0. FMAP: base = 0xffc00000 size = 0x400000 #areas = 3 FMAP: area COREBOOT found @ 200 (4193792 bytes) CBFS: mcache @0x00034e00 built for 16 files, used 0x380 of 0x2000 bytes CBFS: Found 'fallback/romstage' @0x30e00 size 0x4c450 in mcache @0x00034fec BS: bootblock times (exec / console): total (unknown) / 19 ms coreboot-4.13-3633-g5a157cd000 Sat May 8 20:38:53 UTC 2021 romstage starting (log level: 8)... APIC 00: CPU Family_Model = 00610f01 APIC 00: ** Enter AmdInitReset [00020007] Fch OEM config in INIT RESET AmdInitReset() returned AGESA_SUCCESS APIC 00: Heap in LocalCache (2) at 0x00400000 APIC 00: ** Exit AmdInitReset [00020007] APIC 00: ** Enter AmdInitEarly [00020002] AmdInitEarly() returned AGESA_SUCCESS APIC 00: Heap in LocalCache (2) at 0x00400000 APIC 00: ** Exit AmdInitEarly [00020002] APIC 00: ** Enter AmdInitPost [00020006] -------------READING SPD----------- iobase: 0x00000B00, SmbusSlave: 0x000000A4, count: 256 -------------FINISHED READING SPD----------- -------------READING SPD----------- iobase: 0x00000B00, SmbusSlave: 0x000000A6, count: 256 -------------SPD READ ERROR----------- ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmExcludeDimm.c', line 236 AmdInitPost() returned AGESA_FATAL ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c', line 606 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEventLog.c', line 288 ASSERTION ERROR: file 'src/drivers/amd/agesa/state_machine.c', line 275 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c', line 606 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c', line 477 ASSERTION ERROR: file 'src/drivers/amd/agesa/state_machine.c', line 278 APIC 00: Heap in TempMem (3) at 0x00000000 APIC 00: ** Exit AmdInitPost [00020006] RAM INIT FAILURE! Change-Id: Icba25c1066cbbb461a5d3ef22d68e8c89357f425 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/gigabyte/ga-f2a55m-hd2/BiosCallOuts.c A src/mainboard/gigabyte/ga-f2a55m-hd2/Kconfig A src/mainboard/gigabyte/ga-f2a55m-hd2/Kconfig.name A src/mainboard/gigabyte/ga-f2a55m-hd2/Makefile.inc A src/mainboard/gigabyte/ga-f2a55m-hd2/OemCustomize.c A src/mainboard/gigabyte/ga-f2a55m-hd2/OptionsIds.h A src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/cpstate.asl A src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/gpe.asl A src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/routing.asl A src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/sata.asl A src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/si.asl A src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/sleep.asl A src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/superio.asl A src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/thermal.asl A src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/usb_oc.asl A src/mainboard/gigabyte/ga-f2a55m-hd2/acpi_tables.c A src/mainboard/gigabyte/ga-f2a55m-hd2/board_info.txt A src/mainboard/gigabyte/ga-f2a55m-hd2/bootblock.c A src/mainboard/gigabyte/ga-f2a55m-hd2/buildOpts.c A src/mainboard/gigabyte/ga-f2a55m-hd2/cmos.layout A src/mainboard/gigabyte/ga-f2a55m-hd2/devicetree.cb A src/mainboard/gigabyte/ga-f2a55m-hd2/dsdt.asl A src/mainboard/gigabyte/ga-f2a55m-hd2/irq_tables.c A src/mainboard/gigabyte/ga-f2a55m-hd2/mainboard.c A src/mainboard/gigabyte/ga-f2a55m-hd2/mptable.c A src/mainboard/gigabyte/ga-f2a55m-hd2/romstage.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnregtn.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c 28 files changed, 1,445 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/54000/1 diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/BiosCallOuts.c b/src/mainboard/gigabyte/ga-f2a55m-hd2/BiosCallOuts.c new file mode 100644 index 0000000..24a7208 --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/BiosCallOuts.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <AGESA.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include <northbridge/amd/agesa/state_machine.h> + +#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> + +const BIOS_CALLOUT_STRUCT BiosCallouts[] = { + {AGESA_DO_RESET, agesa_Reset }, + {AGESA_READ_SPD, agesa_ReadSpd }, + {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, + {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } +}; +const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); + +/** + * ASUS A88XM-E board ALC887-VD Verb Table + * + * Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running + * the vendor BIOS. + */ +const CODEC_ENTRY a88xm_e_alc887_VerbTbl[] = { + {0x11, 0x90460130}, + {0x12, 0x40330000}, + {0x14, 0x01014010}, + {0x15, 0x411111f0}, + {0x16, 0x411111f0}, + {0x17, 0x411111f0}, + {0x18, 0x01a19040}, + {0x19, 0x02a19050}, + {0x1a, 0x0181304f}, + {0x1b, 0x02214020}, + {0x1c, 0x411111f0}, + {0x1d, 0x4044c601}, + {0x1e, 0x411111f0}, + {0x1f, 0x411111f0} +}; + +static const CODEC_TBL_LIST CodecTableList[] = { + {0x10ec0887, (CODEC_ENTRY *)&a88xm_e_alc887_VerbTbl[0]}, + {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY *)0x0FFFFFFFFUL} +}; + +void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) +{ + FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); +} + +void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) +{ + /* Azalia Controller OEM Codec Table Pointer */ + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); + + /* Fan Control */ + FchParams_env->Imc.ImcEnable = FALSE; + FchParams_env->Hwm.HwMonitorEnable = FALSE; + FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */ +} diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/Kconfig b/src/mainboard/gigabyte/ga-f2a55m-hd2/Kconfig new file mode 100644 index 0000000..55232ac --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/Kconfig @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_GIGABYTE_GA_F2A55M_HD2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_AMD_AGESA_FAMILY15_TN + select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN + select SOUTHBRIDGE_AMD_AGESA_HUDSON + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select SUPERIO_ITE_IT8728F + select BOARD_ROMSIZE_KB_4096 + select GFXUMA + +config MAINBOARD_DIR + string + default "gigabyte/ga-f2a55m-hd2" + +config MAINBOARD_PART_NUMBER + string + default "GA-F2A55M-HD2" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config HUDSON_XHCI_FWM + bool + default n + +config HUDSON_IMC_FWM + bool + default n + +config IRQ_SLOT_COUNT + int + default 11 + +config VGA_BIOS_ID + string + default "1002,9904" + +config HUDSON_XHCI_ENABLE + bool + default n + +config HUDSON_LEGACY_FREE + bool + default n + +endif # BOARD_GIGABYTE_GA_F2A55M_HD2 diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/Kconfig.name b/src/mainboard/gigabyte/ga-f2a55m-hd2/Kconfig.name new file mode 100644 index 0000000..9787bf1 --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GIGABYTE_GA_F2A55M_HD2 + bool "GA-F2A55M-HD2" diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/Makefile.inc b/src/mainboard/gigabyte/ga-f2a55m-hd2/Makefile.inc new file mode 100644 index 0000000..549801d --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/Makefile.inc @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +romstage-y += buildOpts.c +romstage-y += BiosCallOuts.c +romstage-y += OemCustomize.c + +ramstage-y += buildOpts.c +ramstage-y += BiosCallOuts.c +ramstage-y += OemCustomize.c diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/OemCustomize.c b/src/mainboard/gigabyte/ga-f2a55m-hd2/OemCustomize.c new file mode 100644 index 0000000..7762457 --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/OemCustomize.c @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <Porting.h> +#include <AGESA.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <PlatformMemoryConfiguration.h> + +/* + * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) + * + * Lane Id + * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8 + * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8 + * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8 + * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8 + * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7 + * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7 + * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7 + * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7 + * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI + * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI + * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI + * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI + * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI + * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI + * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI + * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI + * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI + * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI + * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI + * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI + * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI + * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI + * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI + * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI + * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs) + * 25 DP0_TX[P,N]1 + * 26 DP0_TX[P,N]2 + * 27 DP0_TX[P,N]3 + * 28 DP1_TX[P,N]0 + * 29 DP1_TX[P,N]1 + * 30 DP1_TX[P,N]2 + * 31 DP1_TX[P,N]3 + * 32 DP2_TX[P,N]0 + * 33 DP2_TX[P,N]1 + * 34 DP2_TX[P,N]2 + * 35 DP2_TX[P,N]3 + * 36 DP2_TX[P,N]4 + * 37 DP2_TX[P,N]5 + * 38 DP2_TX[P,N]6 + */ + +static const PCIe_PORT_DESCRIPTOR PortList[] = { + /* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23), + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) + }, + /* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) + }, + /* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0) + }, +}; + +/* + * It is not known, if the setup is complete. + * + * Tested and works: VGA/DVI, HDMI + */ +static const PCIe_DDI_DESCRIPTOR DdiList[] = { + // DP0 to HDMI0/DP + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1) + }, + // DP1 to FCH + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2) + }, + // DP2 to HDMI1/DP + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3) + }, +}; + +static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = PortList, + .DdiLinkList = DdiList, +}; + +void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ + FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; + FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); + FchReset->Xhci1Enable = CONFIG(HUDSON_XHCI_ENABLE); +} + +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) +{ + InitEarly->GnbConfig.PcieComplexList = &PcieComplex; + InitEarly->GnbConfig.PsppPolicy = 0; +} + +/* CUSTOMER OVERRIDES MEMORY TABLE */ +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ + +static CONST PSO_ENTRY ROMDATA MemoryTable_XM_E[] = { + + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), + /*MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00), + ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x00, 0x00), + CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),*/ + PSO_END +}; + +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_XM_E; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/OptionsIds.h b/src/mainboard/gigabyte/ga-f2a55m-hd2/OptionsIds.h new file mode 100644 index 0000000..2afbdc0 --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/OptionsIds.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + **/ + +#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_CONTROL_ENABLED TRUE +#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE +#define IDSOPT_ASSERT_ENABLED TRUE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/cpstate.asl b/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/cpstate.asl new file mode 100644 index 0000000..35583de --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/cpstate.asl @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. + */ + +/* + * P-state support: the maximum number of P-states supported + * by the CPUs that we'll use - is 6. Taken from AMI BIOS. + */ +Name(_PSS, Package(){ + Package() + { + 0x00000D48, + 0x00011170, + 0x00000004, + 0x00000004, + 0x00000000, + 0x00000000 + }, + + Package() + { + 0x00000AF0, + 0x0000C544, + 0x00000004, + 0x00000004, + 0x00000001, + 0x00000001 + }, + + Package() + { + 0x000009C4, + 0x0000B3B0, + 0x00000004, + 0x00000004, + 0x00000002, + 0x00000002 + }, + + Package() + { + 0x00000898, + 0x0000ABE0, + 0x00000004, + 0x00000004, + 0x00000003, + 0x00000003 + }, + + Package() + { + 0x00000708, + 0x0000A410, + 0x00000004, + 0x00000004, + 0x00000004, + 0x00000004 + }, + + Package() + { + 0x00000578, + 0x00006F54, + 0x00000004, + 0x00000004, + 0x00000005, + 0x00000005 + } +}) + +Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} +}) + +Method(_PPC, 0){ + Return(0) +} diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/gpe.asl b/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/gpe.asl new file mode 100644 index 0000000..9f01c7a --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/gpe.asl @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + } + + /* Legacy PM event */ + Method(_L08) { + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + } + + /* USB controller PME# */ + Method(_L0B) { + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + } + + /* ExtEvent1 SCI event */ + Method(_L11) { + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/routing.asl b/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/routing.asl new file mode 100644 index 0000000..99511c5 --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/routing.asl @@ -0,0 +1,246 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + /* Routing is in System Bus scope */ + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F15 Host Controller */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x16 slot */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + + /* Bus 0, Dev 4 - PCIe Bridge for 4x slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ + + /* Bus 0, Dev 20 - + * F0: SMBus/ACPI, F1: IDE, F2: HDAudio, F3: LPC, F4: PCIBridge, F5: USB + */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0, EHCI @ func 2 */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* SB devices */ + /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + + /* Bus 0, Dev 21 PCIe Bridge */ + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 17 }, + Package(){0x0001FFFF, 1, 0, 18 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */ + Package(){0x0002FFFF, 0, 0, 18 }, + Package(){0x0002FFFF, 1, 0, 19 }, + Package(){0x0002FFFF, 2, 0, 16 }, + Package(){0x0002FFFF, 3, 0, 17 }, + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + + /* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */ + Package(){0x0004FFFF, 0, 0, 16 }, + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ + + /* Bus 0, Dev 20 - + * F0: SMBus/ACPI, F1: IDE, F2: HDAudio, F3: LPC, F4: PCIBridge, F5: USB + */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* SB devices in APIC mode */ + /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0, EHCI @ func 2 */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 0x12}, + Package(){0x0010FFFF, 1, 0, 0x11}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* Bus 0, Dev 21 PCIE Bridge */ + Package(){0x0015FFFF, 0, 0, 17 }, + Package(){0x0015FFFF, 1, 0, 18 }, + Package(){0x0015FFFF, 2, 0, 19 }, + Package(){0x0015FFFF, 3, 0, 16 }, + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + /* black slot */ + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PBR0, Package(){ + /* PCIx1 on SB */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(ABR0, Package(){ + /* PCIx1 on SB */ + Package(){0x0000FFFF, 0, 0, 0x10 }, + Package(){0x0000FFFF, 1, 0, 0x11 }, + Package(){0x0000FFFF, 2, 0, 0x12 }, + Package(){0x0000FFFF, 3, 0, 0x13 }, + }) + + Name(PBR1, Package(){ + /* Onboard network */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(ABR1, Package(){ + /* Onboard network */ + Package(){0x0000FFFF, 0, 0, 0x11 }, + Package(){0x0000FFFF, 1, 0, 0x12 }, + Package(){0x0000FFFF, 2, 0, 0x13 }, + Package(){0x0000FFFF, 3, 0, 0x10 }, + }) + + /* SB PCI Bridge */ + Name(PCIB, Package(){ + /* PCI slots: slot 0 behind Dev14, Fun4. */ + Package(){0x0005FFFF, 0, 0, 0x14 }, + Package(){0x0005FFFF, 1, 0, 0x15 }, + Package(){0x0005FFFF, 2, 0, 0x16 }, + Package(){0x0005FFFF, 3, 0, 0x17 }, + }) diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/sata.asl b/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/sata.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/sata.asl diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/si.asl b/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/si.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/si.asl diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/sleep.asl b/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/sleep.asl new file mode 100644 index 0000000..46f37f3 --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/sleep.asl @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ +Method(\_PTS, 1) { + + /* Clear wake status structure. */ + WKST [0] = 0 + WKST [1] = 0 + + UPWS = 0x07 +} /* End Method(\_PTS) */ + +/* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ +Method(\_WAK, 1) { + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/superio.asl b/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/superio.asl diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/thermal.asl b/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/thermal.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/thermal.asl diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/usb_oc.asl b/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/usb_oc.asl new file mode 100644 index 0000000..d90fffd --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi/usb_oc.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi_tables.c b/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi_tables.c new file mode 100644 index 0000000..ff4a3b9 --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/acpi_tables.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <arch/ioapic.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write Hudson IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/board_info.txt b/src/mainboard/gigabyte/ga-f2a55m-hd2/board_info.txt new file mode 100644 index 0000000..579dce6 --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/A88XME/ +ROM package: DIP8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y (without AmdSpiRomProtect modules) +Release year: 2014 diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/bootblock.c b/src/mainboard/gigabyte/ga-f2a55m-hd2/bootblock.c new file mode 100644 index 0000000..9157ada --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/bootblock.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/acpimmio.h> +#include <bootblock_common.h> +#include <cf9_reset.h> +#include <device/pnp_type.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8728f/it8728f.h> + +static void sbxxx_enable_48mhzout(void) +{ + /* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */ + u32 reg32; + reg32 = misc_read32(0x28); + reg32 &= ~(7 << 19); + reg32 |= (2 << 19); + misc_write32(0x28, reg32); + + /* Enable Auxiliary OSCOUT2 */ + misc_write32(0x40, misc_read32(0x40) & ~(1 << 7)); + + misc_write32(0x28, 0x00120118); + misc_write32(0x40, 0x020c4840); +} + +static void superio_init_m(void) +{ + const pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1); + const pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO); + + ite_kill_watchdog(gpio); + ite_enable_serial(uart, CONFIG_TTYS0_BASE); + ite_enable_3vsbsw(gpio); + + /* Disable SIO WDT which kicks in DualBIOS */ + ite_reg_write(gpio, 0xef, 0x7e); +} + +void bootblock_mainboard_early_init(void) +{ + sbxxx_enable_48mhzout(); + + superio_init_m(); +} + +void bootblock_mainboard_init(void) +{ + //full_reset(); +} diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/buildOpts.c b/src/mainboard/gigabyte/ga-f2a55m-hd2/buildOpts.c new file mode 100644 index 0000000..0166d947 --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/buildOpts.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <vendorcode/amd/agesa/f15tn/AGESA.h> + +/* Include the files that instantiate the configuration definitions. */ +#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> +/* AGESA nonsense: the next two headers depend on heapManager.h */ +#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h> +/* These tables are optional and may be used to adjust memory timing settings */ +#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h> +#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h> + +/* Select the CPU family */ +#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE + +/* Select the CPU socket type */ +#define INSTALL_FM2_SOCKET_SUPPORT TRUE + +#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_WHEA FALSE +#define BLDOPT_REMOVE_CRAT TRUE + +/* Build configuration values here. */ +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_DESKTOP + +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_ENABLE_ECC_FEATURE FALSE +#define BLDCFG_ECC_SYNC_FLOOD FALSE + +#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto + +#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000 /* (0x2000 << 16) = 512M */ + +#define BLDCFG_IOMMU_SUPPORT TRUE + +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE + +/* Customized OEM build configurations for FCH component */ +#define BLDCFG_FCH_GPP_LINK_CONFIG PortA1B1C1D1 +#define BLDCFG_FCH_GPP_PORT0_PRESENT TRUE +#define BLDCFG_FCH_GPP_PORT1_PRESENT TRUE +#define BLDCFG_FCH_GPP_PORT2_PRESENT TRUE + +GPIO_CONTROL ga_f2a55m_hd2_gpio[] = { + {-1} +}; +#define BLDCFG_FCH_GPIO_CONTROL_LIST (ga_f2a55m_hd2_gpio) + +/* Moving this include up will break AGESA. */ +#include <PlatformInstall.h> diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/cmos.layout b/src/mainboard/gigabyte/ga-f2a55m-hd2/cmos.layout new file mode 100644 index 0000000..efaa386 --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/cmos.layout @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0-only + +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +444 1 e 1 nmi +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/devicetree.cb b/src/mainboard/gigabyte/ga-f2a55m-hd2/devicetree.cb new file mode 100644 index 0000000..6f325a9 --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/devicetree.cb @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/amd/agesa/family15tn/root_complex + + device cpu_cluster 0 on + chip cpu/amd/agesa/family15tn + device lapic 10 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + + chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia (iGPU Audio) + device pci 2.0 on end # PCIEX16 + device pci 3.0 off end # - + device pci 4.0 on end # PCIe bridge (LAN) + device pci 5.0 off end # PCIe x1 (?) + device pci 6.0 off end # PCIe x1 (?) + device pci 7.0 off end # PCIe x1 (?) + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn + + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 off end # XHCI HC0 + device pci 10.1 off end # XHCI HC1 + device pci 11.0 on end # SATA AHCI + device pci 12.0 on end # USB OHCI + device pci 12.2 on end # USB EHCI + device pci 13.0 on end # USB OHCI + device pci 13.2 on end # USB EHCI + device pci 14.0 on end # SMBUS + device pci 14.1 on end # IDE (unusable?) + device pci 14.2 on end # HDA + device pci 14.3 on # LPC + chip superio/ite/it8728f + register "TMPIN1.mode" = "THERMAL_RESISTOR" + register "TMPIN2.mode" = "THERMAL_RESISTOR" + register "TMPIN3.mode" = "THERMAL_RESISTOR" + + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" + register "FAN1.smart.tmpin" = "1" + register "FAN1.smart.tmp_off" = "0x80" # never + register "FAN1.smart.tmp_start" = "20" + register "FAN1.smart.tmp_full" = "70" + register "FAN1.smart.tmp_delta" = "0" + register "FAN1.smart.smoothing" = "1" + register "FAN1.smart.pwm_start" = "20" + register "FAN1.smart.slope" = "32" + + # Enable tacho reading for chassis fan. + #register "FAN2.mode" = "FAN_MODE_OFF" + + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # Parallel Port + device pnp 2e.4 on # Env Controller + io 0x60 = 0x290 + io 0x62 = 0x220 + irq 0x70 = 0 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # CIR + end #superio/ite/it8728f + end #device pci 14.3 # LPC + device pci 14.4 on end # PCI bridge + device pci 14.5 on end # USB OHCI + device pci 14.6 off end # Gec + device pci 14.7 off end # SD + device pci 15.0 off end # PCIe RP0 + device pci 15.1 off end # PCIe RP1 + device pci 15.2 off end # PCIe RP2 + device pci 15.3 off end # PCIe RP3 + # MISSING 16.0 and 16.2 + end #chip southbridge/amd/agesa/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + + register "spdAddrLookup" = " + { + /* socket 0 - Channel 0 & 1 - 8-bit SPD addresses */ + { {0xA4, 0x00}, {0xA6, 0x00}, }, + }" + + end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + end #domain +end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/dsdt.asl b/src/mainboard/gigabyte/ga-f2a55m-hd2/dsdt.asl new file mode 100644 index 0000000..97e2d75 --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/dsdt.asl @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* DefinitionBlock Statement */ +#include <acpi/acpi.h> +DefinitionBlock ( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + #include <acpi/dsdt_top.asl> + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> + + /* Describe the processor tree (\_PR) */ + #include <cpu/amd/agesa/family15tn/acpi/cpu.asl> + + /* Describe the supported Sleep States for this Southbridge */ + #include <southbridge/amd/common/acpi/sleepstates.asl> + + /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */ + #include "acpi/sleep.asl" + + Scope(\_SB) { + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ + #include "acpi/routing.asl" + + Device(PCI0) { + /* Describe the AMD Northbridge */ + #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/fch.asl> + } + + /* Describe PCI INT[A-H] for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> + + } /* End Scope(_SB) */ + + /* Describe SMBUS for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" + + /* Define the Thermal zones and methods for the platform */ + #include "acpi/thermal.asl" + + /* Define the System Indicators for the platform */ + #include "acpi/si.asl" + +} +/* End of ASL file */ diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/irq_tables.c b/src/mainboard/gigabyte/ga-f2a55m-hd2/irq_tables.c new file mode 100644 index 0000000..7ca1c4b --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/irq_tables.c @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/pirq_routing.h> +#include <console/console.h> +#include <device/pci_def.h> +#include <string.h> + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + + u8 sum = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr = ALIGN_UP(addr, 16); + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->slots); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + { + const u8 *const v = (u8 *)(pirq); + for (i = 0; i < pirq->size; i++) + sum += v[i]; + } + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) + pirq->checksum = sum; + + printk(BIOS_INFO, "%s done.\n", __func__); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/mainboard.c b/src/mainboard/gigabyte/ga-f2a55m-hd2/mainboard.c new file mode 100644 index 0000000..26bbd0e --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/mainboard.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/msr.h> +#include <device/device.h> +#include <southbridge/amd/common/amd_pci_util.h> + +static const u8 mainboard_picr_data[] = { + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, + 0x1F, 0x1F, 0x09, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, +}; +static const u8 mainboard_intr_data[84] = { + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, + 0x1F, 0x1F, 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x12, 0x13, +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +/* dedicated "enable" function (taken from thatcher) */ +static void mainboard_enable(struct device *dev) +{ + msr_t msr; + + pirq_setup(); + + msr = rdmsr(LS_CFG_MSR); + /* Enable streaming store functionality. */ + msr.lo &= ~(1 << 28); + wrmsr(LS_CFG_MSR, msr); + + msr = rdmsr(DC_CFG_MSR); + /* Enable speculative TLB preloads. */ + msr.lo &= ~(1 << 4); + /* Enable the DC hardware prefetcher. */ + msr.lo &= ~(1 << 13); + wrmsr(DC_CFG_MSR, msr); + + msr = rdmsr(BU_CFG_MSR); + /* Disable the L2 way lock. */ + msr.lo &= ~(1 << 23); + wrmsr(BU_CFG_MSR, msr); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/mptable.c b/src/mainboard/gigabyte/ga-f2a55m-hd2/mptable.c new file mode 100644 index 0000000..b9e743c --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/mptable.c @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/ioapic.h> +#include <arch/smp/mpspec.h> +#include <string.h> +#include <southbridge/amd/common/amd_pci_util.h> +#include <southbridge/amd/agesa/hudson/hudson.h> + +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} + +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); + + smp_write_processors(mc); + + //mptable_write_buses(mc, NULL, &bus_isa); + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + bus_isa = 0x02; + my_smp_write_bus(mc, bus_isa, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,\ + bus_isa, (intr), (apicid), (pin)) + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\ + (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) + + /* IOMMU */ + PCI_INT(0x0, 0x0, 0x0, 0x10); + PCI_INT(0x0, 0x0, 0x1, 0x11); + PCI_INT(0x0, 0x0, 0x2, 0x12); + PCI_INT(0x0, 0x0, 0x3, 0x13); + + /* Internal VGA */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); + + /* SMBUS */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + + /* HD Audio */ + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); + + /* on board NIC & Slot PCIE. */ + + /* PCI slots */ + struct device *dev = pcidev_on_root(0x14, 4); + if (dev && dev->enabled) { + u8 bus_pci = dev->link_list->secondary; + /* PCI_SLOT 0. */ + PCI_INT(bus_pci, 0x5, 0x0, 0x14); + PCI_INT(bus_pci, 0x5, 0x1, 0x15); + PCI_INT(bus_pci, 0x5, 0x2, 0x16); + PCI_INT(bus_pci, 0x5, 0x3, 0x17); + } + + /* PCIe Lan */ + PCI_INT(0x0, 0x06, 0x0, 0x13); + + /* FCH PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, 0x10); + /* FCH PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, 0x11); + /* FCH PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, 0x12); + /* FCH PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, 0x13); + + /* Local Ints: Type IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/gigabyte/ga-f2a55m-hd2/romstage.c b/src/mainboard/gigabyte/ga-f2a55m-hd2/romstage.c new file mode 100644 index 0000000..a251955 --- /dev/null +++ b/src/mainboard/gigabyte/ga-f2a55m-hd2/romstage.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/acpimmio.h> +#include <console/console.h> +#include <northbridge/amd/agesa/state_machine.h> +#include <southbridge/amd/agesa/hudson/smbus.h> + +static void smbus_setup(void) +{ + post_code(0x30); + + /* turn on secondary smbus at b20 */ + pm_write8(0x28, pm_read8(0x28) | 0x01); +} + +void board_BeforeAgesa(struct sysinfo *cb) +{ + smbus_setup(); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnregtn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnregtn.c index 5bf1093..a1f00cb 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnregtn.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnregtn.c @@ -233,9 +233,9 @@ Address = PciAddr.AddressValue; LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctCfgSel)) { - IDS_HDT_CONSOLE (MEM_GETREG, "~Dev%x Dct%d Fn%d_%03x = %x\n", - NBPtr->PciAddr.Address.Device, NBPtr->Dct, - (Address >> 12) & 0x7, Address & 0xFFF, Value); + //IDS_HDT_CONSOLE (MEM_GETREG, "~Dev%x Dct%d Fn%d_%03x = %x\n", + // NBPtr->PciAddr.Address.Device, NBPtr->Dct, + // (Address >> 12) & 0x7, Address & 0xFFF, Value); } } else if (Type == DCT_PHY_ACCESS) { if (IsPhyDirectAccess && (NumOfInstances > 1)) { @@ -243,7 +243,7 @@ } MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); - IDS_HDT_CONSOLE (MEM_GETREG, "~Dev%x Dct%d Fn2_9C_%x = %x\n", NBPtr->PciAddr.Address.Device, NBPtr->Dct, Address & 0x0FFFFFFF, Value); + //IDS_HDT_CONSOLE (MEM_GETREG, "~Dev%x Dct%d Fn2_9C_%x = %x\n", NBPtr->PciAddr.Address.Device, NBPtr->Dct, Address & 0x0FFFFFFF, Value); } else { // DCT_EXTRA_ACCESS is not supported on TN ASSERT (FALSE); @@ -264,17 +264,17 @@ PciAddr.AddressValue = Address; LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctCfgSel)) { - IDS_HDT_CONSOLE (MEM_SETREG, "~Dev%x Dct%d Fn%d_%03x [%d:%d] = %x\n", - NBPtr->PciAddr.Address.Device, NBPtr->Dct, - (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); + //IDS_HDT_CONSOLE (MEM_SETREG, "~Dev%x Dct%d Fn%d_%03x [%d:%d] = %x\n", + // NBPtr->PciAddr.Address.Device, NBPtr->Dct, + // (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); Address |= DCT_ACCESS_WRITE; MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - IDS_HDT_CONSOLE (MEM_SETREG, "~Dev%x Dct%d Fn2_9C_%x [%d:%d] = %x\n", - NBPtr->PciAddr.Address.Device, NBPtr->Dct, - Address & 0x0FFFFFFF, Highbit, Lowbit, Field); + //IDS_HDT_CONSOLE (MEM_SETREG, "~Dev%x Dct%d Fn2_9C_%x [%d:%d] = %x\n", + // NBPtr->PciAddr.Address.Device, NBPtr->Dct, + // Address & 0x0FFFFFFF, Highbit, Lowbit, Field); } else { // DCT_EXTRA_ACCESS is not supported on TN ASSERT (FALSE); @@ -308,7 +308,7 @@ } } } else { - IDS_HDT_CONSOLE (MEM_UNDEF_BF, "\t\tUndefined BF enum: %x\n", FieldName); + //IDS_HDT_CONSOLE (MEM_UNDEF_BF, "\t\tUndefined BF enum: %x\n", FieldName); } } else { ASSERT (FALSE); // Invalid bit field index diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c index 46e591a..98cde1c 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c @@ -500,14 +500,14 @@ // There are no other breaks out of this loop. //------------------------------------------------------------------- while (MemTContinueSweep (TechPtr, &SweepData)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tByte Lane : 08 07 06 05 04 03 02 01 00\n"); + /*IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tByte Lane : 08 07 06 05 04 03 02 01 00\n"); IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tDQS Delays : %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[8]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[7]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[6]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[5]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[4]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[3]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[2]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[1]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[0]) - ); + );*/ // /// Set Step Value // @@ -547,7 +547,7 @@ } } /// End Chip Select Loop TechPtr->ChipSel = TechPtr->ChipSel - CsIndex; - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tResult : %c %c %c %c %c %c %c %c %c \n", + /*IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tResult : %c %c %c %c %c %c %c %c %c \n", (SweepData.ResultFound & ((UINT16) 1 << (8))) ? ' ':(CurrentResult & ((UINT16) 1 << (8))) ? 'P':'.', (SweepData.ResultFound & ((UINT16) 1 << (7))) ? ' ':(CurrentResult & ((UINT16) 1 << (7))) ? 'P':'.', (SweepData.ResultFound & ((UINT16) 1 << (6))) ? ' ':(CurrentResult & ((UINT16) 1 << (6))) ? 'P':'.', @@ -557,12 +557,13 @@ (SweepData.ResultFound & ((UINT16) 1 << (2))) ? ' ':(CurrentResult & ((UINT16) 1 << (2))) ? 'P':'.', (SweepData.ResultFound & ((UINT16) 1 << (1))) ? ' ':(CurrentResult & ((UINT16) 1 << (1))) ? 'P':'.', (SweepData.ResultFound & ((UINT16) 1 << (0))) ? ' ':(CurrentResult & ((UINT16) 1 << (0))) ? 'P':'.' - ); + );*/ // /// Merge current result into cumulative result and make it positive. // SweepData.ResultFound |= ~(CurrentResult ^ SweepData.EndResult); + /* IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tResultFound : %c %c %c %c %c %c %c %c %c \n\n", (SweepData.ResultFound & ((UINT16) 1 << (8))) ? 'Y':' ', (SweepData.ResultFound & ((UINT16) 1 << (7))) ? 'Y':' ', @@ -573,7 +574,7 @@ (SweepData.ResultFound & ((UINT16) 1 << (2))) ? 'Y':' ', (SweepData.ResultFound & ((UINT16) 1 << (1))) ? 'Y':' ', (SweepData.ResultFound & ((UINT16) 1 << (0))) ? 'Y':' ' - ); + );*/ } /// End of Delay Sweep // /// Place Final delay values at last passing delay. -- To view, visit https://review.coreboot.org/c/coreboot/+/54000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icba25c1066cbbb461a5d3ef22d68e8c89357f425 Gerrit-Change-Number: 54000 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Makefile: Don't run genbuild_h if not doing a build
by Martin Roth (Code Review) 09 May '21

09 May '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53997 ) Change subject: Makefile: Don't run genbuild_h if not doing a build ...................................................................... Makefile: Don't run genbuild_h if not doing a build genbuild_h was being run on every make invocation - clean, distclean, etc. to get the source date epoch value. This value isn't used unless a build is being done, so don't run it on non-compile make invocations. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I2afc0affc17116e0db849ea968474bc19dbb0ae1 --- M Makefile 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/53997/1 diff --git a/Makefile b/Makefile index 02c6288..21b889d 100644 --- a/Makefile +++ b/Makefile @@ -24,7 +24,9 @@ LANG:=C LC_ALL:=C TZ:=UTC0 +ifeq ($(NOCOMPILE),1) SOURCE_DATE_EPOCH := $(shell $(top)/util/genbuild_h/genbuild_h.sh . | sed -n 's/^.define COREBOOT_BUILD_EPOCH\>.*"$.*$".*/\1/p') +endif # don't use COREBOOT_EXPORTS to ensure build steps outside the coreboot build system # are reproducible export LANG LC_ALL TZ SOURCE_DATE_EPOCH -- To view, visit https://review.coreboot.org/c/coreboot/+/53997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2afc0affc17116e0db849ea968474bc19dbb0ae1 Gerrit-Change-Number: 53997 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: Documentation/gerrit: Document our Gerrit user roles and procedures
by Patrick Georgi (Code Review) 09 May '21

09 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52265 ) Change subject: Documentation/gerrit: Document our Gerrit user roles and procedures ...................................................................... Documentation/gerrit: Document our Gerrit user roles and procedures Document the roles we have on review.coreboot.org, the expectations associated with them, and how to become part of any of these groups. Change-Id: Ib31083f5a07bd89efd13ecd6aaf34a69d438d59d Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52265 Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/getting_started/gerrit_guidelines.md 1 file changed, 29 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/Documentation/getting_started/gerrit_guidelines.md b/Documentation/getting_started/gerrit_guidelines.md index 4547f91..a372ea8 100644 --- a/Documentation/getting_started/gerrit_guidelines.md +++ b/Documentation/getting_started/gerrit_guidelines.md @@ -320,6 +320,35 @@ codebase. Again, this also applies in the other direction: review code, criticize code, but don’t make it personal. +Gerrit user roles +----------------- +There are a few relevant roles a user can have on Gerrit: + +- The anonymous user can check out source code. +- A registered user can also comment and give "+1" and "-1" code reviews. +- A reviewer can also give "+2" code reviews. +- A core developer can also give "-2" (that is, blocking) code reviews + and submit changes. + +Anybody can register an account on our instance, using either an +OpenID provider or OAuth through GitHub or Google. + +The reviewer group is still quite open: Any core developer can add +registered users to that group and should do so once some activity +(commits, code reviews, and so on) has demonstrated rough knowledge +of how we handle things. + +A core developer should be sufficiently well established in the +community so that they feel comfortable when submitting good patches, +when asking for improvements to less good patches and reasonably +uncomfortable when -2'ing patches. They're typically the go-to +person for _some_ part of the coreboot tree and ideally listed as its +maintainer in our MAINTAINERS registry. To become part of this group, +a candidate developer who already demonstrated proficiency with the +code base as a reviewer should be nominated, by themselves or others, +at the regular [coreboot leadership meetings](../community/forums.md) +where a decision is made. + Requests for clarification and suggestions for updates to these guidelines should be sent to the coreboot mailing list at <coreboot(a)coreboot.org>. -- To view, visit https://review.coreboot.org/c/coreboot/+/52265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib31083f5a07bd89efd13ecd6aaf34a69d438d59d Gerrit-Change-Number: 52265 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit May 2021