coreboot-gerrit May 2021

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Change in coreboot[master]: nb/amd/agesa/family15tn: Enable RESOURCE_ALLOCATOR_V4
by Michał Żygowski (Code Review) 09 May '21

09 May '21

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53990 ) Change subject: nb/amd/agesa/family15tn: Enable RESOURCE_ALLOCATOR_V4 ...................................................................... nb/amd/agesa/family15tn: Enable RESOURCE_ALLOCATOR_V4 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Id895f664fd295f3818ffdf9cc3b68511a5f40df4 --- M src/northbridge/amd/agesa/family15tn/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/53990/1 diff --git a/src/northbridge/amd/agesa/family15tn/Kconfig b/src/northbridge/amd/agesa/family15tn/Kconfig index 60007a3..d5bebda 100644 --- a/src/northbridge/amd/agesa/family15tn/Kconfig +++ b/src/northbridge/amd/agesa/family15tn/Kconfig @@ -2,7 +2,6 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY15_TN bool - select RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_AGESA_FAMILY15_TN -- To view, visit https://review.coreboot.org/c/coreboot/+/53990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id895f664fd295f3818ffdf9cc3b68511a5f40df4 Gerrit-Change-Number: 53990 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/amd/agesa/family15tn/northbridge.c: Report missing resources
by Michał Żygowski (Code Review) 09 May '21

09 May '21

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53989 ) Change subject: nb/amd/agesa/family15tn/northbridge.c: Report missing resources ...................................................................... nb/amd/agesa/family15tn/northbridge.c: Report missing resources Not all resources were being reported, add them. TEST=not tested Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I5e7793a1239198a4accd92a95b4c43512db9bcbd --- M src/northbridge/amd/agesa/family15tn/northbridge.c 1 file changed, 32 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/53989/1 diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 015475b..64bddb0 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -119,6 +119,29 @@ } +static void add_fixed_resources(struct device *dev, int index) +{ + /* Reserve everything between A segment and 1MB: + * + * 0xa0000 - 0xbffff: legacy VGA + * 0xc0000 - 0xfffff: option ROMs and SeaBIOS (if used) + */ + mmio_resource(dev, index++, 0xa0000 >> 10, (0xc0000 - 0xa0000) >> 10); + reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); + + if (fx_devs == 0) + get_fx_devs(); + + /* Check if CC6 save area is enabled (bit 18 CC6SaveEn) */ + if (pci_read_config32(__f2_dev[0], 0x118) & (1 << 18)) { + /* Add CC6 DRAM UC resource residing at DRAM Limit of size 16MB as per BKDG */ + resource_t basek, limitk; + if (!get_dram_base_limit(0, &basek, &limitk)) + return; + mmio_resource(dev, index++, limitk, 16*1024); + } +} + static void nb_read_resources(struct device *dev) { /* @@ -127,6 +150,8 @@ * the CPU_CLUSTER. */ mmconf_resource(dev, MMIO_CONF_BASE); + + add_fixed_resources(dev, 0); } /** @@ -396,9 +421,7 @@ static void domain_read_resources(struct device *dev) { unsigned long mmio_basek; - u32 pci_tolm; int i, idx; - struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; u32 reset_memhole = 1; @@ -406,21 +429,8 @@ pci_domain_read_resources(dev); - pci_tolm = 0xffffffffUL; - for (link = dev->link_list; link; link = link->next) { - pci_tolm = find_pci_tolm(link); - } - - // FIXME handle interleaved nodes. If you fix this here, please fix - // amdk8, too. - mmio_basek = pci_tolm >> 10; - /* Round mmio_basek to something the processor can support */ - mmio_basek &= ~((1 << 6) -1); - - // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M - // MMIO hole. If you fix this here, please fix amdk8, too. - /* Round the mmio hole to 64M */ - mmio_basek &= ~((64*1024) - 1); + /* TOP_MEM MSR is our boundary between DRAM and MMIO under 4G */ + mmio_basek = bsp_topmem() >> 10; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 /* if the hw mem hole is already set in raminit stage, here we will compare @@ -447,13 +457,12 @@ sizek = limitk - basek; - /* see if we need a hole from 0xa0000 to 0xbffff */ - if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { - ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); + /* see if we need a hole from 0xa0000 to 0xfffff */ + if ((basek < (0xa0000 >> 10) && (sizek > (0x100000 >> 10)))) { + ram_resource(dev, (idx | i), basek, (0xa0000 >> 10) - basek); idx += 0x10; - basek = (8*64)+(16*16); - sizek = limitk - ((8*64)+(16*16)); - + basek = 0x100000 >> 10; + sizek = limitk - basek; } /* split the region to accommodate pci memory space */ -- To view, visit https://review.coreboot.org/c/coreboot/+/53989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e7793a1239198a4accd92a95b4c43512db9bcbd Gerrit-Change-Number: 53989 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/amd/agesa/family15tn: Use generic allocation functions for PCI domain
by Michał Żygowski (Code Review) 09 May '21

09 May '21

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53988 ) Change subject: nb/amd/agesa/family15tn: Use generic allocation functions for PCI domain ...................................................................... nb/amd/agesa/family15tn: Use generic allocation functions for PCI domain Move the DRAM reporting to read_resoures function before the resources are being set. Use generic PCI domain resource allocation functions to read and set domain resources. TEST=not tested Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Icb9c9d6b6d527127282073eb03a6ae9fbd242f5a --- M src/northbridge/amd/agesa/family15tn/northbridge.c 1 file changed, 4 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/53988/1 diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index d547df3..015475b 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -54,13 +54,6 @@ printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); } -static u32 f1_read_config32(unsigned int reg) -{ - if (fx_devs == 0) - get_fx_devs(); - return pci_read_config32(__f1_dev[0], reg); -} - static void f1_write_config32(unsigned int reg, u32 value) { int i; @@ -354,43 +347,6 @@ .enable_dev = 0, }; -static void domain_read_resources(struct device *dev) -{ - unsigned int reg; - - /* Find the already assigned resource pairs */ - get_fx_devs(); - for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { - u32 base, limit; - base = f1_read_config32(reg); - limit = f1_read_config32(reg + 0x04); - /* Is this register allocated? */ - if ((base & 3) != 0) { - unsigned int nodeid, reg_link; - struct device *reg_dev; - if (reg < 0xc0) { // mmio - nodeid = (limit & 0xf) + (base&0x30); - } else { // io - nodeid = (limit & 0xf) + ((base>>4)&0x30); - } - reg_link = (limit >> 4) & 7; - reg_dev = __f0_dev[nodeid]; - if (reg_dev) { - /* Reserve the resource */ - struct resource *res; - res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); - if (res) { - res->flags = 1; - } - } - } - } - /* FIXME: do we need to check extend conf space? - I don't believe that much preset value */ - - pci_domain_read_resources(dev); -} - #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { unsigned int hole_startk; @@ -437,7 +393,7 @@ } #endif -static void domain_set_resources(struct device *dev) +static void domain_read_resources(struct device *dev) { unsigned long mmio_basek; u32 pci_tolm; @@ -448,6 +404,8 @@ u32 reset_memhole = 1; #endif + pci_domain_read_resources(dev); + pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); @@ -527,17 +485,11 @@ } add_uma_resource_below_tolm(dev, 7); - - for (link = dev->link_list; link; link = link->next) { - if (link->children) { - assign_resources(link); - } - } } static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, - .set_resources = domain_set_resources, + .set_resources = pci_domain_set_resources, .scan_bus = pci_domain_scan_bus, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/53988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb9c9d6b6d527127282073eb03a6ae9fbd242f5a Gerrit-Change-Number: 53988 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/amd/agesa/family15tn:Use generic allocation functions for northbridge
by Michał Żygowski (Code Review) 09 May '21

09 May '21

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53987 ) Change subject: nb/amd/agesa/family15tn:Use generic allocation functions for northbridge ...................................................................... nb/amd/agesa/family15tn:Use generic allocation functions for northbridge Remove obsolete resource assigning functions. IO and MMIO address registers are currently set by amd_initcpuio to cover whole PCI hole under 4G to MMIO and IO 0x0000-0xFFFF is configured to be routed to southbridge already. Use generic PCI and resource allocation functions wherever possible to set northbridge resources. TEST=not tested Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ic9e407dfe61597f454fd0ebf5bde2ad467c14dea --- M src/northbridge/amd/agesa/family15tn/northbridge.c 1 file changed, 2 insertions(+), 225 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/53987/1 diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index fe56736..d547df3 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -32,33 +32,6 @@ static struct device *__f4_dev[MAX_NODE_NUMS]; static unsigned int fx_devs = 0; -static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, - u32 io_min, u32 io_max) -{ - u32 i; - u32 tempreg; - /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); -} - -static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) -{ - u32 i; - u32 tempreg; - /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit - for (i = 0; i < nodes; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); -} - static struct device *get_node_pci(u32 nodeid, u32 fn) { return pcidev_on_root(DEV_CDB + nodeid, fn); @@ -153,148 +126,8 @@ } -/** - * @return - * @retval 2 resource does not exist, usable - * @retval 0 resource exists, not usable - * @retval 1 resource exist, resource has been allocated before - */ -static int reg_useable(unsigned int reg, struct device *goal_dev, - unsigned int goal_nodeid, unsigned int goal_link) -{ - struct resource *res; - unsigned int nodeid, link = 0; - int result; - res = 0; - for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - struct device *dev; - dev = __f0_dev[nodeid]; - if (!dev) - continue; - for (link = 0; !res && (link < 8); link++) { - res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); - } - } - result = 2; - if (res) { - result = 0; - if ((goal_link == (link - 1)) && - (goal_nodeid == (nodeid - 1)) && - (res->flags <= 1)) { - result = 1; - } - } - return result; -} - -static struct resource *amdfam15_find_iopair(struct device *dev, - unsigned int nodeid, unsigned int link) -{ - struct resource *resource; - u32 free_reg, reg; - resource = 0; - free_reg = 0; - for (reg = 0xc0; reg <= 0xd8; reg += 0x8) { - int result; - result = reg_useable(reg, dev, nodeid, link); - if (result == 1) { - /* I have been allocated this one */ - break; - } - else if (result > 1) { - /* I have a free register pair */ - free_reg = reg; - } - } - if (reg > 0xd8) { - reg = free_reg; // if no free, the free_reg still be 0 - } - - resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); - - return resource; -} - -static struct resource *amdfam15_find_mempair(struct device *dev, u32 nodeid, u32 link) -{ - struct resource *resource; - u32 free_reg, reg; - resource = 0; - free_reg = 0; - for (reg = 0x80; reg <= 0xb8; reg += 0x8) { - int result; - result = reg_useable(reg, dev, nodeid, link); - if (result == 1) { - /* I have been allocated this one */ - break; - } - else if (result > 1) { - /* I have a free register pair */ - free_reg = reg; - } - } - if (reg > 0xb8) { - reg = free_reg; - } - - resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); - return resource; -} - -static void amdfam15_link_read_bases(struct device *dev, u32 nodeid, u32 link) -{ - struct resource *resource; - - /* Initialize the io space constraints on the current bus */ - resource = amdfam15_find_iopair(dev, nodeid, link); - if (resource) { - u32 align; - align = log2(HT_IO_HOST_ALIGN); - resource->base = 0; - resource->size = 0; - resource->align = align; - resource->gran = align; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; - } - - /* Initialize the prefetchable memory constraints on the current bus */ - resource = amdfam15_find_mempair(dev, nodeid, link); - if (resource) { - resource->base = 0; - resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); - resource->limit = 0xffffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - resource->flags |= IORESOURCE_BRIDGE; - } - - /* Initialize the memory constraints on the current bus */ - resource = amdfam15_find_mempair(dev, nodeid, link); - if (resource) { - resource->base = 0; - resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); - resource->limit = 0xffffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; - } - -} - static void nb_read_resources(struct device *dev) { - u32 nodeid; - struct bus *link; - - nodeid = amdfam15_nodeid(dev); - for (link = dev->link_list; link; link = link->next) { - if (link->children) { - amdfam15_link_read_bases(dev, nodeid, link->link_num); - } - } - /* * This MMCONF resource must be reserved in the PCI domain. * It is not honored by the coreboot resource allocator if it is in @@ -303,52 +136,6 @@ mmconf_resource(dev, MMIO_CONF_BASE); } -static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) -{ - resource_t rbase, rend; - unsigned int reg, link_num; - char buf[50]; - - /* Make certain the resource has actually been set */ - if (!(resource->flags & IORESOURCE_ASSIGNED)) { - return; - } - - /* If I have already stored this resource don't worry about it */ - if (resource->flags & IORESOURCE_STORED) { - return; - } - - /* Only handle PCI memory and IO resources */ - if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) - return; - - /* Ensure I am actually looking at a resource of function 1 */ - if ((resource->index & 0xffff) < 0x1000) { - return; - } - /* Get the base address */ - rbase = resource->base; - - /* Get the limit (rounded up) */ - rend = resource_end(resource); - - /* Get the register and link */ - reg = resource->index & 0xfff; // 4k - link_num = IOINDEX_LINK(resource->index); - - if (resource->flags & IORESOURCE_IO) { - set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); - } - else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums);// [39:8] - } - resource->flags |= IORESOURCE_STORED; - snprintf(buf, sizeof(buf), " <node %x link %x>", - nodeid, link_num); - report_resource_stored(dev, resource, buf); -} - /** * I tried to reuse the resource allocation code in set_resource() * but it is too difficult to deal with the resource allocation magic. @@ -385,24 +172,13 @@ static void nb_set_resources(struct device *dev) { unsigned int nodeid; - struct bus *bus; - struct resource *res; /* Find the nodeid */ nodeid = amdfam15_nodeid(dev); create_vga_resource(dev, nodeid); //TODO: do we need this? - /* Set each resource we have found */ - for (res = dev->resource_list; res; res = res->next) { - set_resource(dev, res, nodeid); - } - - for (bus = dev->link_list; bus; bus = bus->next) { - if (bus->children) { - assign_resources(bus); - } - } + pci_dev_set_resources(dev); } static unsigned long acpi_fill_hest(acpi_hest_t *hest) @@ -556,6 +332,7 @@ .read_resources = nb_read_resources, .set_resources = nb_set_resources, .enable_resources = pci_dev_enable_resources, + .ops_pci = &pci_dev_ops_pci, .acpi_fill_ssdt = northbridge_fill_ssdt_generator, .write_acpi_tables = agesa_write_acpi_tables, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/53987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9e407dfe61597f454fd0ebf5bde2ad467c14dea Gerrit-Change-Number: 53987 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: AGESA f15tn: Fix building IDS tracing support
by Angel Pons (Code Review) 09 May '21

09 May '21

Attention is currently required from: Arthur Heymans, Kyösti Mälkki. Hello Arthur Heymans, Kyösti Mälkki, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/53986 to review the following change. Change subject: AGESA f15tn: Fix building IDS tracing support ...................................................................... AGESA f15tn: Fix building IDS tracing support Also add a config file to ensure the code gets build-tested. Change-Id: I530eccd2a194bc79de5ee354d98260d93423cd5b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A configs/config.asus_a88xm-e.agesa_debug M src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c M src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitReset.c M src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c M src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c M src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitEnvDef.c M src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitResetDef.c M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c 17 files changed, 44 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/53986/1 diff --git a/configs/config.asus_a88xm-e.agesa_debug b/configs/config.asus_a88xm-e.agesa_debug new file mode 100644 index 0000000..c4ec6c66 --- /dev/null +++ b/configs/config.asus_a88xm-e.agesa_debug @@ -0,0 +1,7 @@ +CONFIG_VENDOR_ASUS=y +CONFIG_BOARD_ASUS_A88XM_E=y +CONFIG_ENABLE_MRC_CACHE=y +CONFIG_IDS_TRACING_ENABLED=y +CONFIG_AGESA_EXTRA_TIMESTAMPS=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +CONFIG_DEBUG_RESOURCES=y diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c index 1660c49..8735dac 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c @@ -147,10 +147,8 @@ MmioRange[MmioPair].RangeNum = MmioPair; MmioRange[MmioPair].Modified = FALSE; IDS_HDT_CONSOLE (MAIN_FLOW, " %02d ", MmioPair); - IDS_HDT_CONSOLE (MAIN_FLOW, "%08x%08x %08x%08x", (MmioRange[MmioPair].Base >> 32) & 0xFFFFFFFF, - MmioRange[MmioPair].Base & 0xFFFFFFFF, - (MmioRange[MmioPair].Limit >> 32) & 0xFFFFFFFF, - MmioRange[MmioPair].Limit & 0xFFFFFFFF); + IDS_HDT_CONSOLE (MAIN_FLOW, "%016llx %016llx", MmioRange[MmioPair].Base, + MmioRange[MmioPair].Limit); IDS_HDT_CONSOLE (MAIN_FLOW, " %s %s %s %s", MmioRange[MmioPair].Attribute.MmioPostedRange ? "Y" : "N", MmioRange[MmioPair].Attribute.MmioReadableRange ? "Y" : "N", MmioRange[MmioPair].Attribute.MmioWritableRange ? "Y" : "N", @@ -164,10 +162,8 @@ NewMmioRange.Base = AmdAddMmioParams.BaseAddress; NewMmioRange.Limit = AmdAddMmioParams.BaseAddress + AmdAddMmioParams.Length + 0x10000; NewMmioRange.Attribute = AmdAddMmioParams.Attributes; - IDS_HDT_CONSOLE (MAIN_FLOW, "req %08x%08x %08x%08x\n", (NewMmioRange.Base >> 32) & 0xFFFFFFFF, - NewMmioRange.Base & 0xFFFFFFFF, - (NewMmioRange.Limit >> 32) & 0xFFFFFFFF, - NewMmioRange.Limit & 0xFFFFFFFF); + IDS_HDT_CONSOLE (MAIN_FLOW, "req %016llx %016llx\n", NewMmioRange.Base, + NewMmioRange.Limit); for (ConfMapRange = 0; ConfMapRange < CONF_MAP_NUM; ConfMapRange++) { PciAddress.Address.Register = (CONF_MAP_RANGE_0 + ConfMapRange * 4); LibAmdPciRead (AccessWidth32, PciAddress, &ConfMapRegister, &(AmdAddMmioParams.StdHeader)); @@ -298,10 +294,8 @@ PciAddress.Address.Function = FUNC_1; for (MmioPair = 0; MmioPair < MMIO_REG_PAIR_NUM; MmioPair++) { IDS_HDT_CONSOLE (MAIN_FLOW, " %02d ", MmioPair); - IDS_HDT_CONSOLE (MAIN_FLOW, "%08x%08x %08x%08x", (MmioRange[MmioPair].Base >> 32) & 0xFFFFFFFF, - MmioRange[MmioPair].Base & 0xFFFFFFFF, - (MmioRange[MmioPair].Limit >> 32) & 0xFFFFFFFF, - MmioRange[MmioPair].Limit & 0xFFFFFFFF); + IDS_HDT_CONSOLE (MAIN_FLOW, "%016llx %016llx", MmioRange[MmioPair].Base, + MmioRange[MmioPair].Limit); IDS_HDT_CONSOLE (MAIN_FLOW, " %s %s %s %s", MmioRange[MmioPair].Attribute.MmioPostedRange ? "Y" : "N", MmioRange[MmioPair].Attribute.MmioReadableRange ? "Y" : "N", MmioRange[MmioPair].Attribute.MmioWritableRange ? "Y" : "N", diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitReset.c index 5cb2adc..ce4c8d1 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitReset.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitReset.c @@ -155,7 +155,7 @@ IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitReset: Start\n\n"); - IDS_HDT_CONSOLE (MAIN_FLOW, "\n*** %s ***\n\n", &UserOptions.VersionString); + IDS_HDT_CONSOLE (MAIN_FLOW, "\n*** %s ***\n\n", (char *)&UserOptions.VersionString); AGESA_TESTPOINT (TpIfAmdInitResetEntry, &ResetParams->StdHeader); ASSERT (ResetParams != NULL); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c index b8716f2..747b283 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c @@ -165,7 +165,7 @@ PCI_ADDR PciAddress; UINTN Index; S3SaveTableRecordPtr = (UINT8 *) S3SaveTablePtr + sizeof (S3_SAVE_TABLE_HEADER); - IDS_HDT_CONSOLE (S3_TRACE, "Start S3 restore\n", ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address); + IDS_HDT_CONSOLE (S3_TRACE, "Start S3 restore\n"); while ((UINT8 *) S3SaveTableRecordPtr < ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset)) { switch (*(UINT16 *) S3SaveTableRecordPtr) { case SAVE_STATE_IO_WRITE_OPCODE: diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c index eaebdb1..94f5e12 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c @@ -268,7 +268,7 @@ } } S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); + IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%016llx Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); S3SaveDebugPrintHexArray (StdHeader, Buffer, Count, Width); IDS_HDT_CONSOLE (S3_TRACE, "\n"); ); @@ -333,7 +333,7 @@ } } S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); + IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%016llx Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width); IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width); @@ -409,7 +409,7 @@ } } S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); + IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%016llx Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width); IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width); @@ -481,7 +481,7 @@ SaveOffsetPtr->OpCode = OpCode; SaveOffsetPtr->Length = InformationLength; S3_SCRIPT_DEBUG_CODE ( - IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %s \n", Information); + IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %p\n", Information); ); LibAmdMemCopy ( (UINT8 *) SaveOffsetPtr + sizeof (S3_INFO_OP_HEADER), diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitEnvDef.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitEnvDef.c index ba45bd7..da2bf93 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitEnvDef.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitEnvDef.c @@ -139,7 +139,7 @@ FchParams = (FCH_DATA_BLOCK *) AllocHeapParams.BufferPtr; ASSERT (FchParams != NULL); - IDS_HDT_CONSOLE (FCH_TRACE, " FCH Data Block Allocation: [0x%x], Ptr = 0x%08x\n", AgesaStatus, FchParams); + IDS_HDT_CONSOLE (FCH_TRACE, " FCH Data Block Allocation: [0x%x], Ptr = %p\n", AgesaStatus, FchParams); // Load private data block with default *FchParams = InitEnvCfgDefault; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitResetDef.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitResetDef.c index 3d8f093..9be08b7 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitResetDef.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitResetDef.c @@ -71,7 +71,7 @@ FchParams = (FCH_RESET_DATA_BLOCK *) AllocHeapParams.BufferPtr; ASSERT (FchParams != NULL); - IDS_HDT_CONSOLE (FCH_TRACE, " FCH Reset Data Block Allocation: [0x%x], Ptr = 0x%08x\n", AgesaStatus, FchParams); + IDS_HDT_CONSOLE (FCH_TRACE, " FCH Reset Data Block Allocation: [0x%x], Ptr = %p\n", AgesaStatus, FchParams); *FchParams = InitResetCfgDefault; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c index 7f701f0..69137a0 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c @@ -473,7 +473,7 @@ Index += 4; break; case 4: - IDS_HDT_CONSOLE (GNB_TRACE, "%08x%08", *(UINT32 *) ((UINT8 *) Buffer + Index), *(UINT32 *) ((UINT8 *) Buffer + Index + 4)); + IDS_HDT_CONSOLE (GNB_TRACE, "%016llx", *(UINT64 *) ((UINT8 *) Buffer + Index)); Index += 8; break; default: diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c index 8befb2c..05b11fe 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c @@ -223,7 +223,7 @@ ); IDS_HDT_CONSOLE (GFX_MISC, " UmaMode - %s\n", (Gfx->UmaInfo.UmaMode == UMA_NONE) ? "No UMA" : "UMA"); if (Gfx->UmaInfo.UmaMode != UMA_NONE) { - IDS_HDT_CONSOLE (GFX_MISC, " UmaBase - 0x%x\n", Gfx->UmaInfo.UmaBase); + IDS_HDT_CONSOLE (GFX_MISC, " UmaBase - 0x%llx\n", Gfx->UmaInfo.UmaBase); IDS_HDT_CONSOLE (GFX_MISC, " UmaSize - 0x%x\n", Gfx->UmaInfo.UmaSize); IDS_HDT_CONSOLE (GFX_MISC, " UmaAttributes - 0x%x\n", Gfx->UmaInfo.UmaAttributes); } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c index 422cbae..7cb69fd 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c @@ -895,7 +895,7 @@ ClockInfoArrayPtr = (CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usClockInfoArrayOffset); IDS_HDT_CONSOLE (GFX_MISC, " < --- SW State Table ---------> \n"); for (Index = 0; Index < StateArray->ucNumEntries; Index++) { - IDS_HDT_CONSOLE (GFX_MISC, " State #%d\n", Index + 1 + IDS_HDT_CONSOLE (GFX_MISC, " State #%ld\n", Index + 1 ); IDS_HDT_CONSOLE (GFX_MISC, " Classification 0x%x\n", NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].usClassification @@ -922,7 +922,7 @@ for (Index = 0; Index < ClockInfoArrayPtr->ucNumEntries; Index++) { UINT32 Sclk; Sclk = ClockInfoArrayPtr->ClockInfo[Index].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[Index].ucEngineClockHigh << 16); - IDS_HDT_CONSOLE (GFX_MISC, " DPM State #%d\n", + IDS_HDT_CONSOLE (GFX_MISC, " DPM State #%ld\n", Index ); IDS_HDT_CONSOLE (GFX_MISC, " SCLK = %d\n", @@ -951,7 +951,7 @@ for (Index = 0; Index < VceStateTable->numEntries; Index++) { SclkIndex = VceStateTable->entries[Index].ucClockInfoIndex & 0x3F; EclkIndex = VceStateTable->entries[Index].ucVCEClockInfoIndex; - IDS_HDT_CONSOLE (GFX_MISC, " VCE State #%d\n", Index + IDS_HDT_CONSOLE (GFX_MISC, " VCE State #%ld\n", Index ); if ((VceClockInfoArray->entries[EclkIndex].usECClkLow | (VceClockInfoArray->entries[EclkIndex].ucECClkHigh << 16)) == 0) { IDS_HDT_CONSOLE (GFX_MISC, " Disable\n"); @@ -973,7 +973,7 @@ IDS_HDT_CONSOLE (GFX_MISC, " < --- VCE Voltage Record Table ---> \n"); for (Index = 0; Index < VceClockVoltageLimitTable->numEntries; Index++) { EclkIndex = VceClockVoltageLimitTable->entries[Index].ucVCEClockInfoIndex; - IDS_HDT_CONSOLE (GFX_MISC, " VCE Voltage Record #%d\n", Index + IDS_HDT_CONSOLE (GFX_MISC, " VCE Voltage Record #%ld\n", Index ); IDS_HDT_CONSOLE (GFX_MISC, " ECLK = %d\n", VceClockInfoArray->entries[EclkIndex].usECClkLow | (VceClockInfoArray->entries[EclkIndex].ucECClkHigh << 16) diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c index 8b388d5..15c0679 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c @@ -337,7 +337,7 @@ ASSERT (GnbHandle != NULL); GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, StdHeader); if ((LogicalId.Revision & 0x0000000000000100ull ) != 0x0000000000000100ull ) { - IDS_HDT_CONSOLE (GNB_TRACE, "CPU Rev = %x, Skip GnbTjOffsetUpdateTN\n", LogicalId.Revision); + IDS_HDT_CONSOLE (GNB_TRACE, "CPU Rev = %llx, Skip GnbTjOffsetUpdateTN\n", LogicalId.Revision); return; } GnbRegisterReadTN (D0F0xBC_xE0104040_TYPE, D0F0xBC_xE0104040_ADDRESS, &D0F0xBC_xE0104040, 0, StdHeader); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c index 8c580a0..d5dcdad 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c @@ -888,7 +888,7 @@ IN AMD_CONFIG_PARAMS *StdHeader ) { - UINTN Index; + UINT32 Index; IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE TABLE------------>\n"); for (Index = 0; Index < 4; Index++) { @@ -945,7 +945,7 @@ ); IDS_HDT_CONSOLE ( NB_MISC, - " VCE Flags[ % d] - 0x % 02x\n", + " VCE Flags[%d] - 0x%02x\n", Index, PpFuseArray->VceFlags[Index] ); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c index b6b98e0..1eb8d9b 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c @@ -292,7 +292,7 @@ Entry = Entry + 4; break; default: - IDS_HDT_CONSOLE (GNB_TRACE, " Unsupported entry type [%d]\n"); + IDS_HDT_CONSOLE (GNB_TRACE, " Unsupported entry type [%d]\n", *Entry); ASSERT (FALSE); } } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c index 84a02d1..b67d3c5 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c @@ -578,7 +578,7 @@ BaseAddress |= Value; if ((BaseAddress & 0xfffffffffffffffe) != 0x0) { - IDS_HDT_CONSOLE (GNB_TRACE, " Enable IOMMU MMIO at address %x for Socket %d Silicon %d\n", BaseAddress, GnbGetSocketId (GnbHandle) , GnbGetSiliconId (GnbHandle)); + IDS_HDT_CONSOLE (GNB_TRACE, " Enable IOMMU MMIO at address %llx for Socket %d Silicon %d\n", BaseAddress, GnbGetSocketId (GnbHandle) , GnbGetSiliconId (GnbHandle)); GnbLibPciRMW (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x8), AccessS3SaveWidth32, 0xFFFFFFFF, 0x0, StdHeader); GnbLibPciRMW (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x4), AccessS3SaveWidth32, 0xFFFFFFFE, 0x1, StdHeader); } else { diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c index 9b7bcbd..e839a1d 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c @@ -557,7 +557,10 @@ EngineList->Type.Port.Address.Address.Device, EngineList->Type.Port.Address.Address.Function ); - IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control - 0x%02x\n", EngineList->Type.Port.PortData.MiscControls); + IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control, Compliance Mode - %u\n", EngineList->Type.Port.PortData.MiscControls.LinkComplianceMode); + IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control, Safe Mode - %u\n", EngineList->Type.Port.PortData.MiscControls.LinkSafeMode); + IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control, SB Link - %u\n", EngineList->Type.Port.PortData.MiscControls.SbLink); + IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control, CLK PM Support - %u\n", EngineList->Type.Port.PortData.MiscControls.ClkPmSupport); IDS_HDT_CONSOLE (PCIE_MISC, " Native PCI Dev Number - %d\n", EngineList->Type.Port.NativeDevNumber); IDS_HDT_CONSOLE (PCIE_MISC, " Native PCI Func Number - %d\n", EngineList->Type.Port.NativeFunNumber); IDS_HDT_CONSOLE (PCIE_MISC, " Hotplug - %s\n", @@ -737,7 +740,7 @@ EngineDescriptor->EngineData.EndLane ); if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { - IDS_HDT_CONSOLE (PCIE_MISC, " PortPresent - %d\n ChannelType - %d\n DeviceNumber - %d\n FunctionNumber - %d\n LinkSpeedCapability - %d\n LinkAspm - %d\n LinkHotplug - %d\n ResetId - %d\n SB link - %d\n MiscControls - 0x%02x\n" , + IDS_HDT_CONSOLE (PCIE_MISC, " PortPresent - %d\n ChannelType - %d\n DeviceNumber - %d\n FunctionNumber - %d\n LinkSpeedCapability - %d\n LinkAspm - %d\n LinkHotplug - %d\n ResetId - %d\n Compliance Mode - %d\n Safe Mode - %d\n SB link - %d\n CLK PM Support - %d\n" , ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.PortPresent, ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ChannelType, ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.DeviceNumber, @@ -746,8 +749,10 @@ ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkAspm, ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkHotplug, ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ResetId, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.LinkComplianceMode, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.LinkSafeMode, ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.SbLink, - ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.ClkPmSupport ); } if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) { @@ -785,7 +790,7 @@ for (ComplexIndex = 0; ComplexIndex < NumberOfComplexes; ++ComplexIndex) { CurrentComplexDescriptor = PcieInputParserGetComplexDescriptor (ComplexDescriptor, ComplexIndex); NumberOfEngines = PcieInputParserGetNumberOfEngines (CurrentComplexDescriptor); - IDS_HDT_CONSOLE (PCIE_MISC, " ComplexDescriptor SocketId - %d\n NumberOfEngines - %d\n", + IDS_HDT_CONSOLE (PCIE_MISC, " ComplexDescriptor SocketId - %d\n NumberOfEngines - %ld\n", ComplexDescriptor->SocketId, NumberOfEngines ); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c index 2a40c09..9873154 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c @@ -167,7 +167,7 @@ for (Index = 0; Index < 4; Index++) { if ((ActiveLanesBitmap & (0xF << (Index * 4))) != 0) { if (LaneGroupExitLatency [Index] > LinkLatencyInfo.MaxL1ExitLatency) { - IDS_HDT_CONSOLE (GNB_TRACE, " Index %d Latency %d\n", Index, LinkLatencyInfo.MaxL1ExitLatency); + IDS_HDT_CONSOLE (GNB_TRACE, " Index %ld Latency %d\n", Index, LinkLatencyInfo.MaxL1ExitLatency); LaneGroupExitLatency [Index] = LinkLatencyInfo.MaxL1ExitLatency; } } @@ -177,7 +177,7 @@ } LaneBitmapForPllOffInL1 = 0; for (Index = 0; Index < 4; Index++) { - IDS_HDT_CONSOLE (GNB_TRACE, " Index %d Final Latency %d\n", Index, LaneGroupExitLatency[Index]); + IDS_HDT_CONSOLE (GNB_TRACE, " Index %ld Final Latency %d\n", Index, LaneGroupExitLatency[Index]); if (LaneGroupExitLatency[Index] > PllPowerUpLatency) { LaneBitmapForPllOffInL1 |= (0xF << (Index * 4)); } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c index 1030d7a..eaf5b49 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c @@ -442,7 +442,7 @@ AGESA_TESTPOINT (TpProcMemAfterAgesaReadSpd, &MemPtr->StdHeader); if (AgesaStatus == AGESA_SUCCESS) { DimmSPDPtr->DimmPresent = TRUE; - IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer); + IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %p\n", Socket, Channel, Dimm, SpdParam.Buffer); #if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) AgesaCustomMemoryProfileSPD(SpdParam.Buffer); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/53986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I530eccd2a194bc79de5ee354d98260d93423cd5b Gerrit-Change-Number: 53986 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: AGESA f15tn: Drop `IDSOPT_ASSERT_ENABLED`
by Angel Pons (Code Review) 09 May '21

09 May '21

Attention is currently required from: Arthur Heymans, Alexander Couzens, Kyösti Mälkki, Patrick Rudolph. Hello build bot (Jenkins), Arthur Heymans, Alexander Couzens, Kyösti Mälkki, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/53983 to look at the new patch set (#2). Change subject: AGESA f15tn: Drop `IDSOPT_ASSERT_ENABLED` ...................................................................... AGESA f15tn: Drop `IDSOPT_ASSERT_ENABLED` The `ASSERT` macro is already defined in `src/include/assert.h`, and AGESA's definition is never used. On Asus A88XM-E, toggling the value of the `IDSOPT_ASSERT_ENABLED` macro does not change the resulting binary when using reproducible builds. Attempting to use AGESA's definition of the `ASSERT` macro results in build errors: In file included from src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c:56: src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c: In function 'GetType4Type7Info': src/vendorcode/amd/agesa/f15tn/Include/Ids.h:371:33: error: statement with no effect [-Werror=unused-value] #define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE)); Given that coreboot's definition of `ASSERT` is more useful, drop AGESA's broken definition and the useless `IDSOPT_ASSERT_ENABLED` macro. Also remove the `IdsAssert` function, as it is no longer used anywhere. Tested with BUILD_TIMELESS=1, Asus A88XM-E remains identical. Change-Id: Ia4e5dbfd3d2e5cec979b8b16fbc11d1ca8a0661e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/amd/parmer/OptionsIds.h M src/mainboard/amd/thatcher/OptionsIds.h M src/mainboard/asus/a88xm-e/OptionsIds.h M src/mainboard/asus/f2a85-m/OptionsIds.h M src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h M src/mainboard/lenovo/g505s/OptionsIds.h M src/mainboard/msi/ms7721/OptionsIds.h M src/vendorcode/amd/agesa/f15tn/Include/Ids.h M src/vendorcode/amd/agesa/f15tn/MainPage.h M src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebug.c 10 files changed, 0 insertions(+), 94 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/53983/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/53983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4e5dbfd3d2e5cec979b8b16fbc11d1ca8a0661e Gerrit-Change-Number: 53983 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src: Drop "This file is part of the coreboot project" lines
by Nico Huber (Code Review) 09 May '21

09 May '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Angel Pons, Morgan Jang, Andrey Petrov, Kyösti Mälkki, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53976 ) Change subject: src: Drop "This file is part of the coreboot project" lines ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/53976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8e7ab26a74b52f86d91faeba77df3331531763f Gerrit-Change-Number: 53976 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 09 May 2021 14:08:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: device: Drop unused `uma_memory_{base,size}` globals
by Arthur Heymans (Code Review) 09 May '21

09 May '21

Attention is currently required from: Angel Pons, Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53977 ) Change subject: device: Drop unused `uma_memory_{base,size}` globals ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/53977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fe60b970153d913ae7b005257e2b53647d6f343 Gerrit-Change-Number: 53977 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sun, 09 May 2021 13:37:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src: Drop "This file is part of the coreboot project" lines
by Arthur Heymans (Code Review) 09 May '21

09 May '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Angel Pons, Morgan Jang, Andrey Petrov, Kyösti Mälkki, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53976 ) Change subject: src: Drop "This file is part of the coreboot project" lines ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/53976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8e7ab26a74b52f86d91faeba77df3331531763f Gerrit-Change-Number: 53976 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 09 May 2021 13:36:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/amd/agesa/family14/northbridge.c: Report missing resources
by Nico Huber (Code Review) 09 May '21

09 May '21

Attention is currently required from: Michał Żygowski, Angel Pons, Kyösti Mälkki, Felix Held. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52935 ) Change subject: nb/amd/agesa/family14/northbridge.c: Report missing resources ...................................................................... Patch Set 4: (1 comment) File src/northbridge/amd/agesa/family14/northbridge.c: https://review.coreboot.org/c/coreboot/+/52935/comment/13cdb8e6_91bf7597 PS2, Line 382: resource_t > I don't know why the API uses `unsigned long` values nor takes values in KiB (it was like this befor […] Generally `resource_t` is used for resource offsets and sizes *in bytes*. If used for anything else, it makes the code very confusing. -- To view, visit https://review.coreboot.org/c/coreboot/+/52935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b1b5f585ff6e0c7aecad250a75600e0c76331e1 Gerrit-Change-Number: 52935 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 09 May 2021 13:30:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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