coreboot-gerrit May 2021

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Change in coreboot[master]: src: Match array format in function declarations and definitions
by Patrick Georgi (Code Review) 13 May '21

13 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54094 ) Change subject: src: Match array format in function declarations and definitions ...................................................................... src: Match array format in function declarations and definitions gcc 11.1 complains when we're passing a type* into a function that was declared to get a type[], even if the ABI has identical parameter passing for both. To prepare for newer compilers, adapt to this added constraint. Change-Id: I5a1b3824a85a178431177620c4c0d5fddc993b4f Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54094 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/lenovo/t400/romstage.c M src/mainboard/lenovo/x200/romstage.c M src/mainboard/roda/rk9/romstage.c M src/soc/intel/alderlake/espi.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/xeon_sp/lpc.c M src/vendorcode/mediatek/mt8192/dramc/dramc_top.c 12 files changed, 12 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index b4766ed..aa3462a 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -15,7 +15,7 @@ sysinfo->enable_peg = peg; } -void get_mb_spd_addrmap(u8 *spd_addrmap) +void get_mb_spd_addrmap(u8 spd_addrmap[4]) { spd_addrmap[0] = 0x50; spd_addrmap[2] = 0x51; diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index 46cedfb..6764644 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -3,7 +3,7 @@ #include <southbridge/intel/common/gpio.h> #include <northbridge/intel/gm45/gm45.h> -void get_mb_spd_addrmap(u8 *spd_addrmap) +void get_mb_spd_addrmap(u8 spd_addrmap[4]) { spd_addrmap[0] = 0x50; spd_addrmap[2] = 0x51; diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index be8ba5d..dabef34 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -2,7 +2,7 @@ #include <northbridge/intel/gm45/gm45.h> -void get_mb_spd_addrmap(u8 *spd_addrmap) +void get_mb_spd_addrmap(u8 spd_addrmap[4]) { spd_addrmap[0] = 0x50; spd_addrmap[2] = 0x52; diff --git a/src/soc/intel/alderlake/espi.c b/src/soc/intel/alderlake/espi.c index feec465..dd0edcd 100644 --- a/src/soc/intel/alderlake/espi.c +++ b/src/soc/intel/alderlake/espi.c @@ -20,7 +20,7 @@ #include <soc/pcr_ids.h> #include <soc/soc_chip.h> -void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) { const config_t *config = config_of_soc(); diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index 20704e5..0e63e0d 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -17,7 +17,7 @@ #include "chip.h" -void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) { const config_t *config = config_of_soc(); diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c index 1737a47..46646d8 100644 --- a/src/soc/intel/elkhartlake/espi.c +++ b/src/soc/intel/elkhartlake/espi.c @@ -16,7 +16,7 @@ #include <soc/pcr_ids.h> #include <soc/soc_chip.h> -void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) { const config_t *config = config_of_soc(); diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index 489fe34..d634cf8 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -16,7 +16,7 @@ #include <soc/pcr_ids.h> #include <soc/soc_chip.h> -void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) { const config_t *config = config_of_soc(); diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c index c3b50de..1d1f94e 100644 --- a/src/soc/intel/jasperlake/espi.c +++ b/src/soc/intel/jasperlake/espi.c @@ -16,7 +16,7 @@ #include <soc/pcr_ids.h> #include <soc/soc_chip.h> -void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) { const config_t *config = config_of_soc(); diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index 5abae76..5d38bb8 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -14,7 +14,7 @@ #include "chip.h" -void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) { const config_t *config = config_of_soc(); diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index 8386cd9..4278676 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -22,7 +22,7 @@ #include <soc/pcr_ids.h> #include <soc/soc_chip.h> -void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) { const config_t *config = config_of_soc(); diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c index f0cb6db..dad0a49 100644 --- a/src/soc/intel/xeon_sp/lpc.c +++ b/src/soc/intel/xeon_sp/lpc.c @@ -8,7 +8,7 @@ #include <chip.h> -void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) { const config_t *config = config_of_soc(); diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_top.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_top.c index 8af6a36..04fd62a 100644 --- a/src/vendorcode/mediatek/mt8192/dramc/dramc_top.c +++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_top.c @@ -475,7 +475,7 @@ #if (FOR_DV_SIMULATION_USED==0) #if !__FLASH_TOOL_DA__ && !__ETT__ -void get_dram_rank_size(u64 dram_rank_size[DRAMC_MAX_RK]) +void get_dram_rank_size(u64 dram_rank_size[]) { #ifdef COMBO_MCP int index, rank_nr, i; -- To view, visit https://review.coreboot.org/c/coreboot/+/54094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a1b3824a85a178431177620c4c0d5fddc993b4f Gerrit-Change-Number: 54094 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: amd/cezanne: adding support for the changed AMD FSP API for USB PHY
by build bot (Jenkins) (Code Review) 13 May '21

13 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54065 ) Change subject: amd/cezanne: adding support for the changed AMD FSP API for USB PHY ...................................................................... Patch Set 6: (4 comments) File src/soc/amd/cezanne/fsp_m_params.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119269): https://review.coreboot.org/c/coreboot/+/54065/comment/51b29545_8517ebe5 PS6, Line 131: if (config->usb_phy_custom) { suspect code indent for conditional statements (8, 12) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119269): https://review.coreboot.org/c/coreboot/+/54065/comment/ff60381b_51d2f455 PS6, Line 131: if (config->usb_phy_custom) { braces {} are not necessary for any arm of this statement Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119269): https://review.coreboot.org/c/coreboot/+/54065/comment/3cceb533_eb8140c9 PS6, Line 134: else { suspect code indent for conditional statements (8, 12) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119269): https://review.coreboot.org/c/coreboot/+/54065/comment/c1555879_d0c601e1 PS6, Line 134: else { else should follow close brace '}' -- To view, visit https://review.coreboot.org/c/coreboot/+/54065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b Gerrit-Change-Number: 54065 Gerrit-PatchSet: 6 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 13 May 2021 18:26:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amd/cezanne: adding support for the changed AMD FSP API for USB PHY
by Julian Schroeder (Code Review) 13 May '21

13 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Julian Schroeder, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54065 to look at the new patch set (#6). Change subject: amd/cezanne: adding support for the changed AMD FSP API for USB PHY ...................................................................... amd/cezanne: adding support for the changed AMD FSP API for USB PHY The AMD FSP is using a new structure for USB and USB C phy settings. This patch removes old, unused structures, adds the new one and enables the devicetree interface for it. Signed-off-by: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/fsp_m_params.c A src/vendorcode/amd/fsp/cezanne/FspUsb.h M src/vendorcode/amd/fsp/cezanne/FspmUpd.h 5 files changed, 184 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/54065/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/54065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b Gerrit-Change-Number: 54065 Gerrit-PatchSet: 6 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/acpi: Add device tree driver to generate thermal zone
by Raul Rangel (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54132 ) Change subject: drivers/acpi: Add device tree driver to generate thermal zone ...................................................................... Patch Set 1: (1 comment) File src/drivers/acpi/thermal_zone/thermal_zone.c: https://review.coreboot.org/c/coreboot/+/54132/comment/7d174945_192b0ca7 PS1, Line 76: dev_count_cpu sigh.... Apparently the linux kernel can only handle 10 items: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi…, if we exceed that limit the passive threshold gets ignored. I will need to limit it here :( -- To view, visit https://review.coreboot.org/c/coreboot/+/54132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee2a42db749f18eef6c3f73cdbb3441567301e5d Gerrit-Change-Number: 54132 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 13 May 2021 18:21:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cbfs: Increase mcache size defaults
by Aaron Durbin (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh, Julius Werner. Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54146 ) Change subject: cbfs: Increase mcache size defaults ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I046ae18c9db9a5d682384edde303c07e0be9d790 Gerrit-Change-Number: 54146 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 13 May 2021 18:19:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: amd/cezanne: adding support for the changed AMD FSP API for USB PHY
by build bot (Jenkins) (Code Review) 13 May '21

13 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54065 ) Change subject: amd/cezanne: adding support for the changed AMD FSP API for USB PHY ...................................................................... Patch Set 5: (6 comments) File src/soc/amd/cezanne/chip.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119268): https://review.coreboot.org/c/coreboot/+/54065/comment/531e4d1e_17b4d5a9 PS5, Line 79: uint8_t usb_phy_custom; please, no space before tabs File src/soc/amd/cezanne/fsp_m_params.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119268): https://review.coreboot.org/c/coreboot/+/54065/comment/7c0be774_34f0b6f3 PS5, Line 131: if(config->usb_phy_custom) suspect code indent for conditional statements (8, 12) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119268): https://review.coreboot.org/c/coreboot/+/54065/comment/04bfa020_6bd43166 PS5, Line 131: if(config->usb_phy_custom) space required before the open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119268): https://review.coreboot.org/c/coreboot/+/54065/comment/1f01606e_34d8496b PS5, Line 132: mcfg->usb_phy=(struct usb_phy_config *) &config->usb_phy; spaces required around that '=' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119268): https://review.coreboot.org/c/coreboot/+/54065/comment/772acab6_6f19f0ba PS5, Line 133: else suspect code indent for conditional statements (8, 12) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119268): https://review.coreboot.org/c/coreboot/+/54065/comment/161b698f_84217127 PS5, Line 134: mcfg->usb_phy=NULL; spaces required around that '=' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/54065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b Gerrit-Change-Number: 54065 Gerrit-PatchSet: 5 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 13 May 2021 18:17:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Add SoC thermal zone
by Raul Rangel (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Tim Wawrzynczak, Rob Barnes. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54134 ) Change subject: mb/google/guybrush: Add SoC thermal zone ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/guybrush/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/54134/comment/12439bf9_512f238c PS1, Line 55: chip drivers/acpi/thermal_zone : register "name" = ""SOC"" : : register "temperature_sensor_id" = "0" : : register "polling_period" = "10000" : : # EC is configured to power off the system at 92C, so add one degree of buffer : # so the OS can gracefully shutdown : register "critical_temperature" = "91" : : # EC is configured to assert PROCHOT at 90C. That drastically lowers : # performance. Instead we will tell the OS to start throttling the CPUs at : # 85C in hopes that we don't hit the PROCHOT limit. : register "passive_config" = "{ : .temperature = 85, : .time_constant_1 = 2, : .time_constant_2 = 5, : .time_sampling_period = 2000, : }" : : device generic 0 on end : end > > Though, I wonder if a `Notify(EC0, 0x80)` would cause the OS to reevaluate the child ThermalZones. […] Sorry if I wasn't clear. I meant a new callback. -- To view, visit https://review.coreboot.org/c/coreboot/+/54134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaeed75bdaa16b117d0fa7144ede98db1388f74f3 Gerrit-Change-Number: 54134 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Thu, 13 May 2021 18:17:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: amd/cezanne: adding support for the changed AMD FSP API for USB PHY
by Julian Schroeder (Code Review) 13 May '21

13 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54065 to look at the new patch set (#5). Change subject: amd/cezanne: adding support for the changed AMD FSP API for USB PHY ...................................................................... amd/cezanne: adding support for the changed AMD FSP API for USB PHY The AMD FSP is using a new structure for USB and USB C phy settings. This patch removes old, unused structures, adds the new one and enables the devicetree interface for it. Signed-off-by: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/fsp_m_params.c A src/vendorcode/amd/fsp/cezanne/FspUsb.h M src/vendorcode/amd/fsp/cezanne/FspmUpd.h 5 files changed, 182 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/54065/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/54065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b Gerrit-Change-Number: 54065 Gerrit-PatchSet: 5 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush: Add SoC thermal zone
by Tim Wawrzynczak (Code Review) 13 May '21

13 May '21

Attention is currently required from: Raul Rangel, Furquan Shaikh, Martin Roth, Rob Barnes. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54134 ) Change subject: mb/google/guybrush: Add SoC thermal zone ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/guybrush/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/54134/comment/d0fb0ae6_d10ec7a1 PS1, Line 55: chip drivers/acpi/thermal_zone : register "name" = ""SOC"" : : register "temperature_sensor_id" = "0" : : register "polling_period" = "10000" : : # EC is configured to power off the system at 92C, so add one degree of buffer : # so the OS can gracefully shutdown : register "critical_temperature" = "91" : : # EC is configured to assert PROCHOT at 90C. That drastically lowers : # performance. Instead we will tell the OS to start throttling the CPUs at : # 85C in hopes that we don't hit the PROCHOT limit. : register "passive_config" = "{ : .temperature = 85, : .time_constant_1 = 2, : .time_constant_2 = 5, : .time_sampling_period = 2000, : }" : : device generic 0 on end : end > Though, I wonder if a `Notify(EC0, 0x80)` would cause the OS to reevaluate the child ThermalZones... The CrOS EC already has a `notify` handler in the kernel which is currently for MKBP processing, so I'm not sure that would work. I need to read up on the thermal zones in ACPI... Intel uses DPTF which borrows a lot from it but is still quite different. > acpigen_write_TMP method into `struct device_operations`. you mean as a new callback, or assigned to which one? the SSDT generation? -- To view, visit https://review.coreboot.org/c/coreboot/+/54134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaeed75bdaa16b117d0fa7144ede98db1388f74f3 Gerrit-Change-Number: 54134 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Thu, 13 May 2021 17:50:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: TEST: Add OEM variables functionality
by Sumeet R Pawnikar (Code Review) 13 May '21

13 May '21

Sumeet R Pawnikar has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/54279 ) Change subject: TEST: Add OEM variables functionality ...................................................................... TEST: Add OEM variables functionality Add OEM variable values for it's functionality test. This makes easy for OEMs to define and use any OEM variable. Change-Id: I0fe600b2be66a33726c0de79b9a67bdcc9ad8235 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/54279/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fe600b2be66a33726c0de79b9a67bdcc9ad8235 Gerrit-Change-Number: 54279 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021