coreboot-gerrit May 2021

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Change in coreboot[master]: drivers/intel/dptf: Add OEM variables support
by Sumeet R Pawnikar (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh, Justin TerAvest, Tim Wawrzynczak, Todd Broch, Aaron Durbin, Patrick Rudolph, Karthik Ramasubramanian. Hello Lance Zhao, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Justin TerAvest, Tim Wawrzynczak, Todd Broch, Aaron Durbin, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50127 to look at the new patch set (#11). Change subject: drivers/intel/dptf: Add OEM variables support ...................................................................... drivers/intel/dptf: Add OEM variables support This adds OEM variables feature under DPTF as per BWG doc #541817. Using this, platform vendors can expose an array of OEM-specific values to be used in determining DPTF policy. These are obtained via the ODVP method, and then simply exposed under sysfs. In addition, these gets updated when a notification is received or when the DPTF policy is changed by userspace. BRANCH=None BUG=b:187253038 TEST=Built and tested on dedede board Change-Id: Iaf3cf7b40e9a441b41d0c659d76895a58669c2fb Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/acpi/acpigen_dptf.c M src/drivers/intel/dptf/chip.h M src/drivers/intel/dptf/dptf.c M src/include/acpi/acpigen_dptf.h 4 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/50127/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/50127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf3cf7b40e9a441b41d0c659d76895a58669c2fb Gerrit-Change-Number: 50127 Gerrit-PatchSet: 11 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Todd Broch <tbroch(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Justin TerAvest <teravest(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Todd Broch <tbroch(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/dptf: Add OEM variables support
by Sumeet R Pawnikar (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh, Justin TerAvest, Tim Wawrzynczak, Todd Broch, Aaron Durbin, Patrick Rudolph, Karthik Ramasubramanian. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50127 ) Change subject: drivers/intel/dptf: Add OEM variables support ...................................................................... Patch Set 10: (1 comment) File src/include/acpi/acpigen_dptf.h: https://review.coreboot.org/c/coreboot/+/50127/comment/0521463c_3c22369f PS8, Line 117: uint8_t oem0; : uint8_t oem1; : uint8_t oem2; : uint8_t oem3; : uint8_t oem4; : uint8_t oem5; : }; > Also why is it part of IETM? As per the BWG doc, I don't see any scope being mentioned for ODVP pack […] I wanted to make simple implementation as per https://review.coreboot.org/c/coreboot/+/54279/1 to define and use these variables under override. -- To view, visit https://review.coreboot.org/c/coreboot/+/50127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf3cf7b40e9a441b41d0c659d76895a58669c2fb Gerrit-Change-Number: 50127 Gerrit-PatchSet: 10 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Todd Broch <tbroch(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Justin TerAvest <teravest(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Todd Broch <tbroch(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 13 May 2021 17:25:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: OEM variables support for DPTF
by Tim Wawrzynczak (Code Review) 13 May '21

13 May '21

Attention is currently required from: Sumeet R Pawnikar, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54098 ) Change subject: ec/google/chromeec: OEM variables support for DPTF ...................................................................... Patch Set 1: (1 comment) File src/ec/google/chromeec/ec_dptf_helpers.c: https://review.coreboot.org/c/coreboot/+/54098/comment/152f0b99_a70bdd35 PS1, Line 136: acpigen_pop_len(); > Can you please add a comment regarding which scope you are trying to pop? Also shouldn't this be don […] Actually I recently noticed there are some new `acpigen_*_end` inline functions... for example, acpigen_write_package_end -- To view, visit https://review.coreboot.org/c/coreboot/+/54098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79fbf00521d54e66b6cd7d95b026a76fd3a4394b Gerrit-Change-Number: 54098 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 13 May 2021 17:25:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/espi_util: Workaround in-band reset race condition
by Raul Rangel (Code Review) 13 May '21

13 May '21

Attention is currently required from: Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54070 ) Change subject: soc/amd/common/block/espi_util: Workaround in-band reset race condition ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: PTAL, I lost the previous +2. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/54070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71271377f20eaf29032214be98794e1645d9b70a Gerrit-Change-Number: 54070 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 13 May 2021 17:22:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/amd/pi/00730F01/model_16_init.c: create correct MTRR solution
by Michał Żygowski (Code Review) 13 May '21

13 May '21

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52762 ) Change subject: cpu/amd/pi/00730F01/model_16_init.c: create correct MTRR solution ...................................................................... cpu/amd/pi/00730F01/model_16_init.c: create correct MTRR solution Create the correct MTRR solution based on the physical address space provided by RESOURCE_ALLOCATOR_V4. Previously CPU initialization did not account for lost C6 DRAM storage MTRR during postcar frame creation. The BSP on 2GB has been stripped from UC MTRR covering C6 DRAM and overlapping with usable DRAM WB MTRR. However this UC MTRR remained on APs which caused inconsistent MTRRs warning in Linux. Use generic MTRR function to create correct MTRR solution that propagates to APs. This also fixes the inconsistent MTRRs warning. TEST=boot Debian with Linux 4.14 on apu2 4GB ECC and apu3 2GB no-ECC Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ie2d7a75affd7d3d3a1bc6327fb423e206b28562f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52762 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/amd/pi/00730F01/model_16_init.c 1 file changed, 28 insertions(+), 37 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 2883b17..358f83b 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cbmem.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <cpu/amd/microcode.h> #include <cpu/x86/msr.h> @@ -12,6 +14,7 @@ #include <cpu/x86/lapic.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> +#include <smp/node.h> static void model_16_init(struct device *dev) { @@ -20,36 +23,22 @@ u8 i; msr_t msr; int num_banks; - int msrno; -#if CONFIG(LOGICAL_CPUS) u32 siblings; -#endif - disable_cache(); - /* Enable access to AMD RdDram and WrDram extension bits */ - msr = rdmsr(SYSCFG_MSR); - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; - wrmsr(SYSCFG_MSR, msr); - - /* BSP: make a0000-bffff UC, c0000-fffff WB, - * same as OntarioApMtrrSettingsList for APs + /* + * All cores are initialized sequentially, so the solution for APs will be created + * before they start. */ - msr.lo = msr.hi = 0; - wrmsr(MTRR_FIX_16K_A0000, msr); - msr.lo = msr.hi = 0x1e1e1e1e; - wrmsr(MTRR_FIX_64K_00000, msr); - wrmsr(MTRR_FIX_16K_80000, msr); - for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++) - wrmsr(msrno, msr); - - msr = rdmsr(SYSCFG_MSR); - msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - msr.lo |= SYSCFG_MSR_MtrrFixDramEn; - wrmsr(SYSCFG_MSR, msr); - + x86_setup_mtrrs_with_detect(); + /* + * Enable ROM caching on BSP we just lost when creating MTRR solution, for faster + * execution of e.g. AmdInitLate + */ + if (boot_cpu()) { + mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); + } x86_mtrr_check(); - x86_enable_cache(); /* zero the machine check error status registers */ msr = rdmsr(IA32_MCG_CAP); @@ -62,20 +51,20 @@ /* Enable the local CPU APICs */ setup_lapic(); -#if CONFIG(LOGICAL_CPUS) - siblings = cpuid_ecx(0x80000008) & 0xff; + if (CONFIG(LOGICAL_CPUS)) { + siblings = cpuid_ecx(0x80000008) & 0xff; - if (siblings > 0) { - msr = rdmsr_amd(CPU_ID_FEATURES_MSR); - msr.lo |= 1 << 28; - wrmsr_amd(CPU_ID_FEATURES_MSR, msr); + if (siblings > 0) { + msr = rdmsr_amd(CPU_ID_FEATURES_MSR); + msr.lo |= 1 << 28; + wrmsr_amd(CPU_ID_FEATURES_MSR, msr); - msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); - msr.hi |= 1 << (33 - 32); - wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + msr.hi |= 1 << (33 - 32); + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + } + printk(BIOS_DEBUG, "siblings = %02d, ", siblings); } - printk(BIOS_DEBUG, "siblings = %02d, ", siblings); -#endif /* DisableCf8ExtCfg */ msr = rdmsr(NB_CFG_MSR); @@ -88,6 +77,8 @@ wrmsr(HWCR_MSR, msr); amd_update_microcode_from_cbfs(); + + display_mtrrs(); } static struct device_operations cpu_dev_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/52762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2d7a75affd7d3d3a1bc6327fb423e206b28562f Gerrit-Change-Number: 52762 Gerrit-PatchSet: 8 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/amd/pi/00730F01: enable RESOURCE_ALLOCATOR_V4
by Michał Żygowski (Code Review) 13 May '21

13 May '21

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52761 ) Change subject: nb/amd/pi/00730F01: enable RESOURCE_ALLOCATOR_V4 ...................................................................... nb/amd/pi/00730F01: enable RESOURCE_ALLOCATOR_V4 TEST=boot Debian with Linux 4.14 on apu2 4GB ECC and apu3 2GB no-ECC Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I0387071748262fdeaa5f4d9a71bb87d4d83241b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52761 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/amd/pi/00730F01/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/northbridge/amd/pi/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig index 0aaaf49..6d321e9 100644 --- a/src/northbridge/amd/pi/00730F01/Kconfig +++ b/src/northbridge/amd/pi/00730F01/Kconfig @@ -2,7 +2,6 @@ config NORTHBRIDGE_AMD_PI_00730F01 bool - select RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_PI_00730F01 -- To view, visit https://review.coreboot.org/c/coreboot/+/52761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0387071748262fdeaa5f4d9a71bb87d4d83241b6 Gerrit-Change-Number: 52761 Gerrit-PatchSet: 8 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/amd/pi/00730F01/northbridge.c: Report missing resources
by Michał Żygowski (Code Review) 13 May '21

13 May '21

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52927 ) Change subject: nb/amd/pi/00730F01/northbridge.c: Report missing resources ...................................................................... nb/amd/pi/00730F01/northbridge.c: Report missing resources Not all resources were being reported, add them. TEST=boot Debian with Linux 4.14 on apu2 4GB ECC and apu3 2GB no ECC Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ia57ab026218f4aae0a98c2081412c4a9ebb7f57a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52927 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/amd/pi/00730F01/northbridge.c 1 file changed, 37 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index ef28011..f1c5e23 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -118,6 +118,29 @@ } +static void add_fixed_resources(struct device *dev, int index) +{ + /* Reserve everything between A segment and 1MB: + * + * 0xa0000 - 0xbffff: legacy VGA + * 0xc0000 - 0xfffff: option ROMs and SeaBIOS (if used) + */ + mmio_resource(dev, index++, 0xa0000 >> 10, (0xc0000 - 0xa0000) >> 10); + reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); + + if (fx_devs == 0) + get_fx_devs(); + + /* Check if CC6 save area is enabled (bit 18 CC6SaveEn) */ + if (pci_read_config32(__f2_dev[0], 0x118) & (1 << 18)) { + /* Add CC6 DRAM UC resource residing at DRAM Limit of size 16MB as per BKDG */ + resource_t basek, limitk; + if (!get_dram_base_limit(0, &basek, &limitk)) + return; + mmio_resource(dev, index++, limitk, 16*1024); + } +} + static void nb_read_resources(struct device *dev) { struct resource *res; @@ -134,6 +157,8 @@ res->base = IO_APIC2_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + add_fixed_resources(dev, 0); } static void create_vga_resource(struct device *dev, unsigned int nodeid) @@ -737,30 +762,15 @@ static void domain_read_resources(struct device *dev) { unsigned long mmio_basek; - u32 pci_tolm; int i, idx; - struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; #endif pci_domain_read_resources(dev); - pci_tolm = 0xffffffffUL; - for (link = dev->link_list; link; link = link->next) { - pci_tolm = find_pci_tolm(link); - } - - // FIXME handle interleaved nodes. If you fix this here, please fix - // amdk8, too. - mmio_basek = pci_tolm >> 10; - /* Round mmio_basek to something the processor can support */ - mmio_basek &= ~((1 << 6) -1); - - // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M - // MMIO hole. If you fix this here, please fix amdk8, too. - /* Round the mmio hole to 64M */ - mmio_basek &= ~((64*1024) - 1); + /* TOP_MEM MSR is our boundary between DRAM and MMIO under 4G */ + mmio_basek = bsp_topmem() >> 10; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 /* if the hw mem hole is already set in raminit stage, here we will compare @@ -786,16 +796,19 @@ sizek = limitk - basek; - /* see if we need a hole from 0xa0000 to 0xbffff */ - if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { - ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); - idx += 0x10; - basek = (8*64)+(16*16); - sizek = limitk - ((8*64)+(16*16)); + printk(BIOS_DEBUG, "node %d: basek=%08llx, limitk=%08llx, sizek=%08llx,\n", + i, basek, limitk, sizek); + /* see if we need a hole from 0xa0000 to 0xfffff */ + if ((basek < (0xa0000 >> 10) && (sizek > (0x100000 >> 10)))) { + ram_resource(dev, (idx | i), basek, (0xa0000 >> 10) - basek); + idx += 0x10; + basek = 0x100000 >> 10; + sizek = limitk - basek; } - //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); + printk(BIOS_DEBUG, "node %d: basek=%08llx, limitk=%08llx, sizek=%08llx,\n", + i, basek, limitk, sizek); /* split the region to accommodate pci memory space */ if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/52927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia57ab026218f4aae0a98c2081412c4a9ebb7f57a Gerrit-Change-Number: 52927 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/amd/pi/00730F01: Use generic allocation functions for PCI domain
by Michał Żygowski (Code Review) 13 May '21

13 May '21

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53955 ) Change subject: nb/amd/pi/00730F01: Use generic allocation functions for PCI domain ...................................................................... nb/amd/pi/00730F01: Use generic allocation functions for PCI domain Move the DRAM reporting to read_resoures function before the resources are being set. Use generic PCI domain resource allocation functions to read and set domain resources. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I9605f7fad30eb093bddf9bc34e31dea9f5f846ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/53955 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/amd/pi/00730F01/northbridge.c 1 file changed, 4 insertions(+), 56 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 1d050b5..ef28011 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -59,13 +59,6 @@ printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); } -static u32 f1_read_config32(unsigned int reg) -{ - if (fx_devs == 0) - get_fx_devs(); - return pci_read_config32(__f1_dev[0], reg); -} - static void f1_write_config32(unsigned int reg, u32 value) { int i; @@ -695,46 +688,6 @@ .final = fam16_finalize, }; -static void domain_read_resources(struct device *dev) -{ - unsigned int reg; - - /* Find the already assigned resource pairs */ - get_fx_devs(); - for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { - u32 base, limit; - base = f1_read_config32(reg); - limit = f1_read_config32(reg + 0x04); - /* Is this register allocated? */ - if ((base & 3) != 0) { - unsigned int nodeid, reg_link; - struct device *reg_dev; - if (reg < 0xc0) { // mmio - nodeid = (limit & 0xf) + (base&0x30); - } else { // io - nodeid = (limit & 0xf) + ((base>>4)&0x30); - } - reg_link = (limit >> 4) & 7; - reg_dev = __f0_dev[nodeid]; - if (reg_dev) { - /* Reserve the resource */ - struct resource *res; - res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); - if (res) { - res->flags = 1; - } - } - } - } - /* FIXME: do we need to check extend conf space? - I don't believe that much preset value */ - pci_domain_read_resources(dev); -} - -static void domain_enable_resources(struct device *dev) -{ -} - #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { unsigned int hole_startk; @@ -781,7 +734,7 @@ } #endif -static void domain_set_resources(struct device *dev) +static void domain_read_resources(struct device *dev) { unsigned long mmio_basek; u32 pci_tolm; @@ -791,6 +744,8 @@ struct hw_mem_hole_info mem_hole; #endif + pci_domain_read_resources(dev); + pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); @@ -871,12 +826,6 @@ } add_uma_resource_below_tolm(dev, 7); - - for (link = dev->link_list; link; link = link->next) { - if (link->children) { - assign_resources(link); - } - } } static const char *domain_acpi_name(const struct device *dev) @@ -889,8 +838,7 @@ static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, - .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, + .set_resources = pci_domain_set_resources, .scan_bus = pci_domain_scan_bus, .acpi_name = domain_acpi_name, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/53955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9605f7fad30eb093bddf9bc34e31dea9f5f846ec Gerrit-Change-Number: 53955 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/boten: Modify DPTF parameters
by Karthik Ramasubramanian (Code Review) 13 May '21

13 May '21

Attention is currently required from: Henry Sun, Sumeet R Pawnikar, Stanley Wu, Paul Fagerburg. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52755 ) Change subject: mb/google/dedede/var/boten: Modify DPTF parameters ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52755/comment/e27712f4_90819dc8 PS2, Line 9: paramerters Nit: parameters -- To view, visit https://review.coreboot.org/c/coreboot/+/52755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43002db61de650d29cd85944a4eaea1b2f99aec4 Gerrit-Change-Number: 52755 Gerrit-PatchSet: 2 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Comment-Date: Thu, 13 May 2021 17:14:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/var/shuboz: update USB OC pin mapping
by chris wang (Code Review) 13 May '21

13 May '21

Attention is currently required from: Paul Menzel, Kane Chen, Chris Wang. chris wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51523 ) Change subject: mb/google/zork/var/shuboz: update USB OC pin mapping ...................................................................... Patch Set 15: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/51523/comment/135b7062_704fba33 PS5, Line 9: modify USB OC pin setting for Shuboz, as follow: > Dear Paul, […] Done File src/mainboard/google/zork/variants/shuboz/overridetree.cb: https://review.coreboot.org/c/coreboot/+/51523/comment/6347204f_fe0d88da PS5, Line 28: register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0" # USB A0 > Hi Kangheui, […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/51523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc1fa090109e6be54e2a5f49e364f5502f53aca2 Gerrit-Change-Number: 51523 Gerrit-PatchSet: 15 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Thu, 13 May 2021 17:12:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kangheui Won <khwon(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit May 2021