coreboot-gerrit May 2021

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Change in coreboot[master]: drivers/intel/dptf: Add OEM variables support
by Tim Wawrzynczak (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh, Justin TerAvest, Sumeet R Pawnikar, Todd Broch, Aaron Durbin, Patrick Rudolph, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50127 ) Change subject: drivers/intel/dptf: Add OEM variables support ...................................................................... Patch Set 11: (2 comments) File src/acpi/acpigen_dptf.c: https://review.coreboot.org/c/coreboot/+/50127/comment/0e3097bd_79371701 PS11, Line 392: <= 6 `<` File src/include/acpi/acpigen_dptf.h: https://review.coreboot.org/c/coreboot/+/50127/comment/883e9540_a7efc562 PS11, Line 117: 6 Please use a `#define`, e.g. `DPTF_OEM_VARIABLE_COUNT` or similar -- To view, visit https://review.coreboot.org/c/coreboot/+/50127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf3cf7b40e9a441b41d0c659d76895a58669c2fb Gerrit-Change-Number: 50127 Gerrit-PatchSet: 11 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Todd Broch <tbroch(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Justin TerAvest <teravest(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Todd Broch <tbroch(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 13 May 2021 20:12:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/acpi: Add device tree driver to generate thermal zone
by Tim Wawrzynczak (Code Review) 13 May '21

13 May '21

Attention is currently required from: Raul Rangel, Furquan Shaikh. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54132 ) Change subject: drivers/acpi: Add device tree driver to generate thermal zone ...................................................................... Patch Set 1: (1 comment) File src/drivers/acpi/thermal_zone/thermal_zone.c: https://review.coreboot.org/c/coreboot/+/54132/comment/60567dd5_cad47804 PS1, Line 76: dev_count_cpu > sigh.... Apparently the linux kernel can only handle 10 items: https://source.chromium. […] ``` /* TBD: Make dynamic */ #define ACPI_MAX_HANDLES 10 ``` well, that really sucks. Push a patch to the kernel? 😉 -- To view, visit https://review.coreboot.org/c/coreboot/+/54132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee2a42db749f18eef6c3f73cdbb3441567301e5d Gerrit-Change-Number: 54132 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Thu, 13 May 2021 20:10:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Add SoC thermal zone
by Tim Wawrzynczak (Code Review) 13 May '21

13 May '21

Attention is currently required from: Raul Rangel, Furquan Shaikh, Martin Roth, Rob Barnes. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54134 ) Change subject: mb/google/guybrush: Add SoC thermal zone ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/guybrush/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/54134/comment/5f0d9de1_8738e0e6 PS1, Line 55: chip drivers/acpi/thermal_zone : register "name" = ""SOC"" : : register "temperature_sensor_id" = "0" : : register "polling_period" = "10000" : : # EC is configured to power off the system at 92C, so add one degree of buffer : # so the OS can gracefully shutdown : register "critical_temperature" = "91" : : # EC is configured to assert PROCHOT at 90C. That drastically lowers : # performance. Instead we will tell the OS to start throttling the CPUs at : # 85C in hopes that we don't hit the PROCHOT limit. : register "passive_config" = "{ : .temperature = 85, : .time_constant_1 = 2, : .time_constant_2 = 5, : .time_sampling_period = 2000, : }" : : device generic 0 on end : end > Sorry if I wasn't clear. I meant a new callback. Sorry I don't follow what the additional callback is for... You could still support multiple controllers with an array, e.g.: ``` #define MAX_TEMP_CONTROLLERS 4 struct drivers_acpi_thermal_zone_config { /* Name of the thermal zone */ const char *name; ... DEVTREE_CONST struct device *temp_controllers[MAX_TEMP_CONTROLLERS]; ``` ``` chip drivers/acpi/thermal_zone use chrome_ec as temp_controller[0] use temp_cntrl1 as temp_controller[1] register "name" = ""SOC"" ... end ... device ref foobar alias temp_cntrl1 on end device ref lpc_bridge on chip ec/google/chromeec device pnp 0c09.0 alias chrome_ec on end end end ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/54134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaeed75bdaa16b117d0fa7144ede98db1388f74f3 Gerrit-Change-Number: 54134 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Thu, 13 May 2021 20:08:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/var/shuboz: update USB OC pin mapping
by Patrick Georgi (Code Review) 13 May '21

13 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51523 ) Change subject: mb/google/zork/var/shuboz: update USB OC pin mapping ...................................................................... mb/google/zork/var/shuboz: update USB OC pin mapping modify USB OC pin setting for Shuboz/Jelboz/Jelboz360 Shuboz/Jelboz: usb_port_overcurrent_pin[0] = "USB_OC_PIN_0" # USB C0 usb_port_overcurrent_pin[1] = "USB_OC_PIN_0" # USB A0 usb_port_overcurrent_pin[2] = "USB_OC_PIN_1" # USB A1 usb_port_overcurrent_pin[3] = "USB_OC_PIN_1" # USB C1 Jelboz360: usb_port_overcurrent_pin[0] = "USB_OC_PIN_0" # USB C0 usb_port_overcurrent_pin[1] = "USB_OC_PIN_0" # USB A0 usb_port_overcurrent_pin[2] = "USB_OC_NONE" # NONE usb_port_overcurrent_pin[3] = "USB_OC_PIN_1" # USB C1 BUG=b:182879559 BRANCH=zork TEST=emerge-zork coreboot, validate the OC mapping. Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: Icc1fa090109e6be54e2a5f49e364f5502f53aca2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51523 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> --- M src/mainboard/google/zork/variants/baseboard/helpers.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/variants/shuboz/overridetree.cb M src/mainboard/google/zork/variants/shuboz/variant.c 4 files changed, 41 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kane Chen: Looks good to me, but someone else must approve Kangheui Won: Looks good to me, approved diff --git a/src/mainboard/google/zork/variants/baseboard/helpers.c b/src/mainboard/google/zork/variants/baseboard/helpers.c index 9af0159..d6c5e48 100644 --- a/src/mainboard/google/zork/variants/baseboard/helpers.c +++ b/src/mainboard/google/zork/variants/baseboard/helpers.c @@ -112,6 +112,12 @@ return !!extract_field(FW_CONFIG_MASK_WWAN, FW_CONFIG_SHIFT_WWAN); } +int variant_is_convertible(void) +{ + return !!extract_field(FW_CONFIG_MASK_LID_ANGLE_TABLET_MODE, + FW_CONFIG_LID_ANGLE_TABLET_MODE_SHIFT); +} + bool variant_uses_v3_schematics(void) { uint32_t board_version; diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index c8873ab..43ae715 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -72,6 +72,8 @@ int variant_has_nvme(void); /* Return 0 if non-existent, 1 if present. */ int variant_has_wwan(void); +/* Add variant is_convertible to identify convertible sku */ +int variant_is_convertible(void); /* Determine if booting in factory by using CROS_SKU_UNPROVISIONED. */ int boot_is_factory_unprovisioned(void); diff --git a/src/mainboard/google/zork/variants/shuboz/overridetree.cb b/src/mainboard/google/zork/variants/shuboz/overridetree.cb index 6eb761e..7047062 100644 --- a/src/mainboard/google/zork/variants/shuboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/shuboz/overridetree.cb @@ -23,6 +23,13 @@ register "telemetry_vddcr_soc_slope_mA" = "24063" register "telemetry_vddcr_soc_offset" = "105" + # USB OC pin mapping + + register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" # USB C0 + register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0" # USB A0 + register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_1" # USB C1 + register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_1" # USB C1 + # I2C2 for touchscreen and trackpad register "i2c[2]" = "{ diff --git a/src/mainboard/google/zork/variants/shuboz/variant.c b/src/mainboard/google/zork/variants/shuboz/variant.c index 8a84a75..9907c72 100644 --- a/src/mainboard/google/zork/variants/shuboz/variant.c +++ b/src/mainboard/google/zork/variants/shuboz/variant.c @@ -2,6 +2,16 @@ #include <baseboard/variants.h> #include <soc/pci_devs.h> +#include "chip.h" + +uint32_t usb_oc_map_override[USB_PORT_COUNT] = { + USB_OC_PIN_0, + USB_OC_PIN_0, + USB_OC_NONE, //for camera + USB_OC_PIN_1, + USB_OC_NONE, + USB_OC_NONE +}; static const fsp_ddi_descriptor hdmi_ddi_descriptors[] = { { // DDI0, DP0, eDP @@ -31,3 +41,19 @@ *ddi_descs = &hdmi_ddi_descriptors[0]; *ddi_num = ARRAY_SIZE(hdmi_ddi_descriptors); } + +void variant_devtree_update(void) +{ + struct soc_amd_picasso_config *soc_cfg; + soc_cfg = config_of_soc(); + uint8_t i; + + /* + For convertible SKU, it will support additional camera on USB1, + so we need the different OC map to support. + */ + if (variant_is_convertible()) { + for (i = 0; i < USB_PORT_COUNT; i++) + soc_cfg->usb_port_overcurrent_pin[i] = usb_oc_map_override[i]; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/51523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc1fa090109e6be54e2a5f49e364f5502f53aca2 Gerrit-Change-Number: 51523 Gerrit-PatchSet: 16 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: chris wang <Chris.Wang(a)amd.com> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/gm45: Guard even more macro parameters
by Nico Huber (Code Review) 13 May '21

13 May '21

Attention is currently required from: Angel Pons, Arthur Heymans, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54280 ) Change subject: nb/intel/gm45: Guard even more macro parameters ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb9d6e8bdafdac7ad820b1629d04e7bdfbcd4b3f Gerrit-Change-Number: 54280 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 13 May 2021 19:09:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OC
by Nick Vaccaro (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Zhuohao Lee, Patrick Rudolph. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54075 ) Change subject: soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OC ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/tigerlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/54075/comment/6fe953f0_f9650ee7 PS1, Line 275: config->tcss_ports[i].ocpin; > nit: This probably fits on the previous line within the 96-column limit? If it's 96-column limit, checkpatch needs to be fixed. If the limit should be 96, I'll fix checkpatch next, so please confirm. Thanks. Running checkpatch WARNING: line over 80 characters #11: FILE: src/soc/intel/tigerlake/fsp_params.c:274: + params->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin; -- To view, visit https://review.coreboot.org/c/coreboot/+/54075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5058a18b1f4d11701cebbba85734fbc279539e52 Gerrit-Change-Number: 54075 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 13 May 2021 19:02:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Configure TCSS OC pins
by Nick Vaccaro (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54076 ) Change subject: mb/google/volteer: Configure TCSS OC pins ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54076/comment/776d2741_239e54b1 PS3, Line 9: volteer > It does look like the vast majority of the variants used the same pad for OC3 ( I see lillipup doesn […] It's been confirmed that all variants use the same pads for oc. Resolving this comment. -- To view, visit https://review.coreboot.org/c/coreboot/+/54076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12da755a1d3b9ec3ed0a2dbfb0782313dd49c7e9 Gerrit-Change-Number: 54076 Gerrit-PatchSet: 5 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Thu, 13 May 2021 18:55:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: vc/mediatek: Align code indent with code flow
by Patrick Georgi (Code Review) 13 May '21

13 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54096 ) Change subject: vc/mediatek: Align code indent with code flow ...................................................................... vc/mediatek: Align code indent with code flow gcc 11 suspects missing braces here, but it seems the line should be executed in all cases, so unindent it. Change-Id: I7b8cacd48e86284c5145c4e8ffb6add75a743108 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54096 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jacob Garber <jgarber1(a)ualberta.ca> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Jacob Garber: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c index cd897ed..ffdf3d6 100644 --- a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c +++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c @@ -3097,8 +3097,8 @@ else u2COMB_TX_SEL[1] = (u4DQ_OEN_final > u2Shift_DQ_Div[1])? ((u4DQ_OEN_final - u2Shift_DQ_Div[1]) >> u1Div_ratio): 0; - vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL), P_Fld(u2COMB_TX_SEL[0], SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0) - | P_Fld(u2COMB_TX_SEL[1], SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL), P_Fld(u2COMB_TX_SEL[0], SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0) + | P_Fld(u2COMB_TX_SEL[1], SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1)); } vSetRank(p, u1Rank_bak); } -- To view, visit https://review.coreboot.org/c/coreboot/+/54096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b8cacd48e86284c5145c4e8ffb6add75a743108 Gerrit-Change-Number: 54096 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: amd/cezanne: adding support for the changed AMD FSP API for USB PHY
by Matt Papageorge (Code Review) 13 May '21

13 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Julian Schroeder, Felix Held. Matt Papageorge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54065 ) Change subject: amd/cezanne: adding support for the changed AMD FSP API for USB PHY ...................................................................... Patch Set 6: (1 comment) File src/vendorcode/amd/fsp/cezanne/FspmUpd.h: https://review.coreboot.org/c/coreboot/+/54065/comment/6f587fbd_29265181 PS6, Line 95: /** Offset 0x04D8**/ struct usb_phy_config *usb_phy; should we just leave this as array of bytes and then cast to it later? -- To view, visit https://review.coreboot.org/c/coreboot/+/54065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b Gerrit-Change-Number: 54065 Gerrit-PatchSet: 6 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 13 May 2021 18:39:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/security/tpm: Deal with zero length tlcl writes
by Patrick Georgi (Code Review) 13 May '21

13 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54095 ) Change subject: src/security/tpm: Deal with zero length tlcl writes ...................................................................... src/security/tpm: Deal with zero length tlcl writes While memcpy(foo, bar, 0) should be a no-op, that's hard to prove for a compiler and so gcc 11.1 complains about the use of an uninitialized "bar" even though it's harmless in this case. Change-Id: Idbffa508c2cd68790efbc0b4ab97ae1b4d85ad51 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54095 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jacob Garber <jgarber1(a)ualberta.ca> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/security/tpm/tss/tcg-1.2/tss.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Jacob Garber: Looks good to me, approved diff --git a/src/security/tpm/tss/tcg-1.2/tss.c b/src/security/tpm/tss/tcg-1.2/tss.c index 8b7778d..413b681 100644 --- a/src/security/tpm/tss/tcg-1.2/tss.c +++ b/src/security/tpm/tss/tcg-1.2/tss.c @@ -215,7 +215,8 @@ to_tpm_uint32(cmd.buffer + tpm_nv_write_cmd.index, index); to_tpm_uint32(cmd.buffer + tpm_nv_write_cmd.length, length); - memcpy(cmd.buffer + tpm_nv_write_cmd.data, data, length); + if (length > 0) + memcpy(cmd.buffer + tpm_nv_write_cmd.data, data, length); return tlcl_send_receive(cmd.buffer, response, sizeof(response)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/54095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbffa508c2cd68790efbc0b4ab97ae1b4d85ad51 Gerrit-Change-Number: 54095 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit May 2021