coreboot-gerrit May 2021

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Change in coreboot[master]: drivers/acpi: Add device tree driver to generate thermal zone
by Tim Wawrzynczak (Code Review) 13 May '21

13 May '21

Attention is currently required from: Raul Rangel, Furquan Shaikh. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54132 ) Change subject: drivers/acpi: Add device tree driver to generate thermal zone ...................................................................... Patch Set 2: (2 comments) File src/drivers/acpi/thermal_zone/thermal_zone.c: https://review.coreboot.org/c/coreboot/+/54132/comment/99890fe3_3407d1c9 PS2, Line 98: !config->passive_config.time_constant_1 : || !config->passive_config.time_constant_2 : || !config->passive_config.time_sampling_period) { : acpigen_write_name_integer("_TC1", 2); : acpigen_write_name_integer("_TC2", 5); : acpigen_write_name_integer("_TSP", SECONDS_TO_DECI_SECONDS(10)); Should there be an error instead of emitting defaults? https://review.coreboot.org/c/coreboot/+/54132/comment/a2c2b2ac_5de7ab4f PS2, Line 114: : config->temperature_controller->ops->acpigen_write_TMP(dev); Hmm... I'm not a big fan of adding a new callback to `struct device *`... I see where the tricky part of this, how to get the right acpigen calls when emitting `_TMP`. What do you think about just writing a `_TMP` that forwards the call to the `_TMP` of the temperature_controller device instead? e.g. ``` /* Method (_TMP, 1) { Return acpi_path(temperature_controller)._TMP(Arg0) } */ acpigen_write_method("_TMP", 0); acpigen_emit_byte(RETURN_OP); acpigen_emit_namestring(acpi_device_path_join(config->temperature_controller), "_TMP"); acpigen_emit_byte(ARG0_OP); acpigen_write_method_end(); ``` ? -- To view, visit https://review.coreboot.org/c/coreboot/+/54132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee2a42db749f18eef6c3f73cdbb3441567301e5d Gerrit-Change-Number: 54132 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Thu, 13 May 2021 22:52:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Add SoC thermal zone
by Raul Rangel (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Tim Wawrzynczak, Rob Barnes. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54134 ) Change subject: mb/google/guybrush: Add SoC thermal zone ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/guybrush/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/54134/comment/30d711a8_561eefea PS1, Line 55: chip drivers/acpi/thermal_zone : register "name" = ""SOC"" : : register "temperature_sensor_id" = "0" : : register "polling_period" = "10000" : : # EC is configured to power off the system at 92C, so add one degree of buffer : # so the OS can gracefully shutdown : register "critical_temperature" = "91" : : # EC is configured to assert PROCHOT at 90C. That drastically lowers : # performance. Instead we will tell the OS to start throttling the CPUs at : # 85C in hopes that we don't hit the PROCHOT limit. : register "passive_config" = "{ : .temperature = 85, : .time_constant_1 = 2, : .time_constant_2 = 5, : .time_sampling_period = 2000, : }" : : device generic 0 on end : end > Sorry I don't follow what the additional callback is for... […] Pushed a new patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/54134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaeed75bdaa16b117d0fa7144ede98db1388f74f3 Gerrit-Change-Number: 54134 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Thu, 13 May 2021 21:59:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: Implement support for DRIVERS_ACPI_THERMAL_ZONE
by Raul Rangel (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54133 to look at the new patch set (#2). Change subject: ec/google/chromeec: Implement support for DRIVERS_ACPI_THERMAL_ZONE ...................................................................... ec/google/chromeec: Implement support for DRIVERS_ACPI_THERMAL_ZONE This generates the required method to access temperature data from the ChromeEC. BUG=b:186166365 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I418b6691a7d00a4c2d89c9c1fe8f9416602be0f1 --- M src/ec/google/chromeec/ec.h M src/ec/google/chromeec/ec_acpi.c M src/ec/google/chromeec/ec_lpc.c 3 files changed, 40 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/54133/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I418b6691a7d00a4c2d89c9c1fe8f9416602be0f1 Gerrit-Change-Number: 54133 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush: Add SoC thermal zone
by Raul Rangel (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Tim Wawrzynczak, Rob Barnes. Hello build bot (Jenkins), Furquan Shaikh, Martin Roth, Rob Barnes, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54134 to look at the new patch set (#2). Change subject: mb/google/guybrush: Add SoC thermal zone ...................................................................... mb/google/guybrush: Add SoC thermal zone The time constant values were taken from the zork thermal.asl. BUG=b:186166365 TEST=Boot guybrush to OS and verify logs look correct thermal-0294 thermal_trips_update : Found critical threshold [3641] thermal-0321 thermal_trips_update : No hot threshold thermal-0200 thermal_get_temperatur: Temperature is 3060 dK thermal-0219 thermal_get_polling_fr: Polling frequency is 100 dS thermal-0200 thermal_get_temperatur: Temperature is 3060 dK thermal LNXTHERM:00: registered as thermal_zone0 ACPI: Thermal Zone [TM00] (33 C) thermal-0200 thermal_get_temperatur: Temperature is 3070 dK Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Iaeed75bdaa16b117d0fa7144ede98db1388f74f3 --- M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb 2 files changed, 25 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/54134/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaeed75bdaa16b117d0fa7144ede98db1388f74f3 Gerrit-Change-Number: 54134 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/acpi: Add device tree driver to generate thermal zone
by Raul Rangel (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54132 ) Change subject: drivers/acpi: Add device tree driver to generate thermal zone ...................................................................... Patch Set 2: (6 comments) File src/drivers/acpi/thermal_zone/chip.h: https://review.coreboot.org/c/coreboot/+/54132/comment/a977d786_61776e57 PS1, Line 13: /* Name of the thermal zone */ : const char *name; > suggestion: since this is for _STR, maybe use `description` instead of `name` ? My first thought was […] Done https://review.coreboot.org/c/coreboot/+/54132/comment/bcc01e7c_3fe77459 PS1, Line 28: acpi_thermal_zone_passive_config > I don't think the struct name is required Reworked the units to be seconds. ms doesn't really make sense. https://review.coreboot.org/c/coreboot/+/54132/comment/c09b5c42_1b230f36 PS1, Line 51: acpigen_write_thermal_zone_get_temperature > Having had a bad nights sleep ;) […] Done File src/drivers/acpi/thermal_zone/thermal_zone.c: https://review.coreboot.org/c/coreboot/+/54132/comment/f18012eb_6c283692 PS1, Line 57: K > deci-kelvin Done https://review.coreboot.org/c/coreboot/+/54132/comment/12822244_f0cd5cfb PS1, Line 76: dev_count_cpu > ``` […] lol, maybe I'll file a bug :) https://review.coreboot.org/c/coreboot/+/54132/comment/89662769_8c565caa PS1, Line 87: if (acpigen_write_thermal_zone_get_temperature(config) != CB_SUCCESS) : printk(BIOS_ERR, "Failed to write _TMP for %s.%s\n", scope, name); > Does this callback need to have a return value? […] Nope. -- To view, visit https://review.coreboot.org/c/coreboot/+/54132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee2a42db749f18eef6c3f73cdbb3441567301e5d Gerrit-Change-Number: 54132 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 13 May 2021 21:59:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/acpi: Add device tree driver to generate thermal zone
by Raul Rangel (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54132 to look at the new patch set (#2). Change subject: drivers/acpi: Add device tree driver to generate thermal zone ...................................................................... drivers/acpi: Add device tree driver to generate thermal zone Given the following device tree entry: chip drivers/acpi/thermal_zone register "description" = ""SOC"" use chrome_ec as temperature_controller register "sensor_id" = "0" register "polling_period" = "10" # EC is configured to power off the system at 92C, so add one degree of buffer # so the OS can gracefully shutdown register "critical_temperature" = "91" # EC is configured to assert PROCHOT at 90C. That drastically lowers # performance. Instead we will tell the OS to start throttling the CPUs at # 85C in hopes that we don't hit the PROCHOT limit. register "passive_config" = "{ .temperature = 85, }" device generic 0 on end end It will generate the following: Scope (\_TZ) { ThermalZone (TM00) { Name (_STR, "CPU") // _STR: Description String Name (_RTV, Zero) // _RTV: Relative Temperature Values Name (_TZP, 0x64) // _TZP: Thermal Zone Polling Name (_CRT, 0x0E39) // _CRT: Critical Temperature Name (_PSV, 0x0DFD) // _PSV: Passive Temperature Name (_PSL, Package (0x10) // _PSL: Passive List { \_SB.CP00, \_SB.CP01, \_SB.CP02, \_SB.CP03, \_SB.CP04, \_SB.CP05, \_SB.CP06, \_SB.CP07, \_SB.CP08, \_SB.CP09, }) Name (_TC1, 0x02) // _TC1: Thermal Constant 1 Name (_TC2, 0x05) // _TC2: Thermal Constant 2 Name (_TSP, 0x14) // _TSP: Thermal Sampling Period Method (_TMP, 0, Serialized) // _TMP: Temperature { Return (\_SB.PCI0.LPCB.EC0.TSRD (Zero)) } } } BUG=b:186166365 TEST=Boot guybrush to OS and verify thermal zone works Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Iee2a42db749f18eef6c3f73cdbb3441567301e5d --- A src/drivers/acpi/thermal_zone/Kconfig A src/drivers/acpi/thermal_zone/Makefile.inc A src/drivers/acpi/thermal_zone/chip.h A src/drivers/acpi/thermal_zone/thermal_zone.c M src/include/device/device.h 5 files changed, 200 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/54132/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee2a42db749f18eef6c3f73cdbb3441567301e5d Gerrit-Change-Number: 54132 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/cret: Enable/disable LTE function based on FW_CO...
by Tim Wawrzynczak (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh, Dtrain Hsu, Henry Sun, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54057 ) Change subject: mb/google/dedede/var/cret: Enable/disable LTE function based on FW_CONFIG ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Furquan, we need your ACPI shutdown patches 😭 What about implementing a `\_SB.MPTS` and perform the power sequence when entering S5 instead of SMM? -- To view, visit https://review.coreboot.org/c/coreboot/+/54057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib926e99aaf9df433a7cff71180ee55431d69f718 Gerrit-Change-Number: 54057 Gerrit-PatchSet: 3 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 13 May 2021 21:04:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: UNTESTED mb/google/guybrush : Enable PCIe Power Management Features
by Matt Papageorge (Code Review) 13 May '21

13 May '21

Matt Papageorge has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54282 ) Change subject: UNTESTED mb/google/guybrush : Enable PCIe Power Management Features ...................................................................... UNTESTED mb/google/guybrush : Enable PCIe Power Management Features Enable ASPM and L1SS BUG=b:187743927 TEST=WIP Change-Id: Iefc4b5b489cb8caf59f21dd4333d7af66ba47c32 Signed-off-by: Matt Papageorge <matthewpapa07(a)gmail.com> --- M src/mainboard/google/guybrush/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/54282/1 diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index 9a69dd0..21b1f3c 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -33,6 +33,10 @@ select PSP_DISABLE_POSTCODES select SOC_AMD_CEZANNE select SOC_AMD_COMMON_BLOCK_USE_ESPI + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select PCIEXP_COMMON_CLOCK + select PCIEXP_L1_SUB_STATE config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES -- To view, visit https://review.coreboot.org/c/coreboot/+/54282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefc4b5b489cb8caf59f21dd4333d7af66ba47c32 Gerrit-Change-Number: 54282 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: enable DPTF functionality for brya
by Tim Wawrzynczak (Code Review) 13 May '21

13 May '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52859 ) Change subject: mb/google/brya: enable DPTF functionality for brya ...................................................................... mb/google/brya: enable DPTF functionality for brya Enable DPTF functionality for Alder Lake based brya BRANCH=None BUG=b:188028732 TEST=Built and tested on brya board Change-Id: I33266c85aa30869466034ccbab04a3c7820ae2b0 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52859 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/baseboard/devicetree.cb M src/mainboard/google/brya/variants/brya0/overridetree.cb 3 files changed, 88 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index a910cc7..faa5335 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -5,6 +5,7 @@ select DRIVERS_I2C_HID select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_SX9324 + select DRIVERS_INTEL_DPTF select DRIVERS_INTEL_PMC select DRIVERS_SPI_ACPI select DRIVERS_WIFI_GENERIC diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index e7a6ed3..16678cb 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -17,6 +17,14 @@ # S0ix enable register "s0ix_enable" = "1" + # DPTF enable + register "dptf_enable" = "1" + + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 55, + }" + # This disabled autonomous GPIO power management, otherwise # old cr50 FW only supports short pulses; need to clarify # the minimum PCH IRQ pulse width with Intel, b/180111628 diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index b5679c8..f56b8d6 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -6,6 +6,85 @@ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM"" + register "options.tsr[1].desc" = ""Charger"" + + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(85, 90), + TEMP_PCT(80, 80), + TEMP_PCT(75, 70), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" -- To view, visit https://review.coreboot.org/c/coreboot/+/52859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33266c85aa30869466034ccbab04a3c7820ae2b0 Gerrit-Change-Number: 52859 Gerrit-PatchSet: 7 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Update meminit code due to upd changes FSP 2147 ...
by Tim Wawrzynczak (Code Review) 13 May '21

13 May '21

Attention is currently required from: Bora Guvendik, Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Ronak Kanabar, Tim Wawrzynczak, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54036 ) Change subject: soc/intel/alderlake: Update meminit code due to upd changes FSP 2147 onwards ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54036/comment/de2b84f0_9abe0668 PS4, Line 19: Will also need the same Cq-Depend as its parent -- To view, visit https://review.coreboot.org/c/coreboot/+/54036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5af11ae99db3bbe3373a9bd4ce36453b58d62fec Gerrit-Change-Number: 54036 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 13 May 2021 20:21:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2021