coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: drivers/intel/usb4: Update driver to support Retimer firmware upgrade
by John Zhao (Code Review) 13 May '21

13 May '21

Attention is currently required from: John Zhao, Duncan Laurie. Hello build bot (Jenkins), Tim Wawrzynczak, Duncan Laurie, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52712 to look at the new patch set (#4). Change subject: drivers/intel/usb4: Update driver to support Retimer firmware upgrade ...................................................................... drivers/intel/usb4: Update driver to support Retimer firmware upgrade Along with upstream kernel for Retimer firmware upgrade, coreboot provides DFPx under host router where each DFP has its PLD and DSM. The DFPx's functions encapsulates power control through GPIO, PD suspend/resume and modes setting for Retimer firmware update under NDA scenario. BUG=b:186521258 TEST=Booted to kernel and validated host router's DFPx properties after decomposing SSDT table. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I81bef80729f6df57119f5523358620cb015e5406 --- M src/drivers/intel/usb4/retimer/chip.h M src/drivers/intel/usb4/retimer/retimer.c M src/drivers/intel/usb4/retimer/retimer.h 3 files changed, 376 insertions(+), 82 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/52712/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/52712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81bef80729f6df57119f5523358620cb015e5406 Gerrit-Change-Number: 52712 Gerrit-PatchSet: 4 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Duncan Laurie Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Duncan Laurie Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Update arm-trusted-firmware submodule to upstream master
by Hung-Te Lin (Code Review) 13 May '21

13 May '21

Attention is currently required from: Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54289 ) Change subject: Update arm-trusted-firmware submodule to upstream master ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I912545022e4320b86ab8a382144c02e315d0c835 Gerrit-Change-Number: 54289 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 14 May 2021 04:40:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: edk2-stable202005: Update MdePkg/Include/IndustryStandard/SmBios.h
by Werner Zeh (Code Review) 13 May '21

13 May '21

Attention is currently required from: Ronak Kanabar. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45906 ) Change subject: edk2-stable202005: Update MdePkg/Include/IndustryStandard/SmBios.h ...................................................................... Patch Set 8: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/45906/comment/19120b82_a5a05b84 PS8, Line 15: the patch "the patches" if there are more than one. https://review.coreboot.org/c/coreboot/+/45906/comment/182235ae_bddd63c3 PS8, Line 17: couple Please start a new sentence with capital letter. -- To view, visit https://review.coreboot.org/c/coreboot/+/45906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9698861be1f969ddca7f171767a54ac486502c74 Gerrit-Change-Number: 45906 Gerrit-PatchSet: 8 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Fri, 14 May 2021 04:38:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/mancomb: Update HUB_RST_L setting in GPIO
by Werner Zeh (Code Review) 13 May '21

13 May '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54078 ) Change subject: mb/google/mancomb: Update HUB_RST_L setting in GPIO ...................................................................... mb/google/mancomb: Update HUB_RST_L setting in GPIO Configure USB HUB_RESET_L gpio to high. BUG=b:187485847 TEST=Build and boot from USB to OS, check the USB function. Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Change-Id: I94e4806c7463030df31f8d819510f9533a622f2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/54078 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/mancomb/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/mancomb/variants/baseboard/gpio.c b/src/mainboard/google/mancomb/variants/baseboard/gpio.c index f829117..5ccbc10 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/gpio.c +++ b/src/mainboard/google/mancomb/variants/baseboard/gpio.c @@ -51,7 +51,7 @@ /* AC_PRES */ PAD_NF(GPIO_23, AC_PRES, PULL_UP), /* HUB_RST_L */ - PAD_GPO(GPIO_24, LOW), + PAD_GPO(GPIO_24, HIGH), /* GPIO_25: Not available */ /* TODO: change back to PCIE_RST_L when we figure out why PCIE_RST doesn't go high. */ PAD_GPO(GPIO_26, HIGH), -- To view, visit https://review.coreboot.org/c/coreboot/+/54078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94e4806c7463030df31f8d819510f9533a622f2a Gerrit-Change-Number: 54078 Gerrit-PatchSet: 2 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/cherry: Add fast calibration support
by Hung-Te Lin (Code Review) 13 May '21

13 May '21

Attention is currently required from: Rex-BC Chen. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54269 ) Change subject: mb/google/cherry: Add fast calibration support ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/54269/comment/9e28967c_852abe19 PS4, Line 7: Add fast calibration support We're not just doing fast calibration right? mb/google/cherry: Initialize DRAM Initialize DRAM in romstage. File src/mainboard/google/cherry/sdram_configs.c: https://review.coreboot.org/c/coreboot/+/54269/comment/1a12e3da_34f03215 PS4, Line 8: Currently ddr_geometry and ddr_type are not used in Cherry. Do we need those info in future? If not, we should put some default values to make it clear "what current code will initialize". -- To view, visit https://review.coreboot.org/c/coreboot/+/54269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7677baef126ee60bf35da3a4eaf720eaa118a27 Gerrit-Change-Number: 54269 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Fri, 14 May 2021 04:29:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush,mancomb: select GOOGLE_SMBIOS_MAINBOARD_VERSION
by Werner Zeh (Code Review) 13 May '21

13 May '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54084 ) Change subject: mb/google/guybrush,mancomb: select GOOGLE_SMBIOS_MAINBOARD_VERSION ...................................................................... mb/google/guybrush,mancomb: select GOOGLE_SMBIOS_MAINBOARD_VERSION Select GOOGLE_SMBIOS_MAINBOARD_VERSION allows querying board revision from the EC. BUG=b:187904819 TEST=1. emerge-guybrush coreboot chromeos-bootimage 2. flash the image to the device and check board rev by using command `dmidecode -t 1 | grep Version` Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Change-Id: I48dc83d85cfc49e2e4155e389814fce08693c4bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/54084 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Peers <epeers(a)google.com> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/mancomb/Kconfig 2 files changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved Eric Peers: Looks good to me, but someone else must approve Rob Barnes: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index 9a69dd0..fc515af 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -24,6 +24,7 @@ select ELOG select ELOG_GSMI select FW_CONFIG + select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_EM100_SUPPORT select HAVE_SPD_IN_CBFS diff --git a/src/mainboard/google/mancomb/Kconfig b/src/mainboard/google/mancomb/Kconfig index 91ec169..938382e 100644 --- a/src/mainboard/google/mancomb/Kconfig +++ b/src/mainboard/google/mancomb/Kconfig @@ -21,6 +21,7 @@ select ELOG select ELOG_GSMI select FW_CONFIG + select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_EM100_SUPPORT select MAINBOARD_HAS_CHROMEOS -- To view, visit https://review.coreboot.org/c/coreboot/+/54084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48dc83d85cfc49e2e4155e389814fce08693c4bd Gerrit-Change-Number: 54084 Gerrit-PatchSet: 2 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: util/crossgcc: Update gcc to 11.1
by Werner Zeh (Code Review) 13 May '21

13 May '21

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54050 ) Change subject: util/crossgcc: Update gcc to 11.1 ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/54050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdee2a8beedd109ee1f0eef6f32f7accbf66674b Gerrit-Change-Number: 54050 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 14 May 2021 04:13:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/shadowmountain: Remove power_gpio from baseboard
by John Zhao (Code Review) 13 May '21

13 May '21

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54290 ) Change subject: mb/intel/shadowmountain: Remove power_gpio from baseboard ...................................................................... mb/intel/shadowmountain: Remove power_gpio from baseboard Along with upstream kernel for Retimer firmware update, coreboot defines power control for each DFP respectively under host router. This change removes the power_gpio from the baseboard. Individual DFPx power_gpio will be added once the dependent definition is complete. BUG=b:186521258 TEST=Build image successfully. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I819d2900afabbfdb2713fa8eee35d3c90cb904fd --- M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb 1 file changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/54290/1 diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index beaf8fd..02b4586 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -189,12 +189,6 @@ device pci 0a.0 off end # Crash-log SRAM device pci 0d.0 on end # USB xHCI device pci 0d.1 off end # USB xDCI (OTG) - device pci 0d.2 on - chip drivers/intel/usb4/retimer - register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H19)" - device generic 0 on end - end - end device pci 0d.3 on end # TBT DMA1 device pci 0e.0 off end # VMD device pci 10.0 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/54290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I819d2900afabbfdb2713fa8eee35d3c90cb904fd Gerrit-Change-Number: 54290 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendor/mediatek: Add MT8195 dram initialization code
by Hung-Te Lin (Code Review) 13 May '21

13 May '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54230 ) Change subject: vendor/mediatek: Add MT8195 dram initialization code ...................................................................... vendor/mediatek: Add MT8195 dram initialization code This is the DRAM initialization code from the reference implementation released by Mediatek for MT8195. The DRAM calibration code can be taken as a standalone library, used by different boot loaders for initializing DRAM and following a different coding style (coreboot was using Linux Kernel coding style), so we have to put it in vendor code folder. Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.com> Change-Id: Iada3ec5ae8a39a8e9253caba550c834d486dddcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/54230 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/vendorcode/mediatek/Makefile.inc A src/vendorcode/mediatek/mt8195/Makefile.inc A src/vendorcode/mediatek/mt8195/dramc/ANA_init_config.c A src/vendorcode/mediatek/mt8195/dramc/DIG_NONSHUF_config.c A src/vendorcode/mediatek/mt8195/dramc/DIG_SHUF_config.c A src/vendorcode/mediatek/mt8195/dramc/DRAMC_SUBSYS_config.c A src/vendorcode/mediatek/mt8195/dramc/DRAM_config_collctioin.c A src/vendorcode/mediatek/mt8195/dramc/Hal_io.c A src/vendorcode/mediatek/mt8195/dramc/LP4_dram_init.c A src/vendorcode/mediatek/mt8195/dramc/Makefile.inc A src/vendorcode/mediatek/mt8195/dramc/dramc_actiming.c A src/vendorcode/mediatek/mt8195/dramc/dramc_debug.c A src/vendorcode/mediatek/mt8195/dramc/dramc_dv_freq_related.c A src/vendorcode/mediatek/mt8195/dramc/dramc_dvfs.c A src/vendorcode/mediatek/mt8195/dramc/dramc_lowpower.c A src/vendorcode/mediatek/mt8195/dramc/dramc_pi_basic_api.c A src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c A src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c A src/vendorcode/mediatek/mt8195/dramc/dramc_top.c A src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c A src/vendorcode/mediatek/mt8195/dramc/dramc_utility.c A src/vendorcode/mediatek/mt8195/dramc/emi.c A src/vendorcode/mediatek/mt8195/include/8195_Register_DDRPHY_AO.h A src/vendorcode/mediatek/mt8195/include/8195_Register_DDRPHY_MD32.h A src/vendorcode/mediatek/mt8195/include/8195_Register_DDRPHY_NAO.h A src/vendorcode/mediatek/mt8195/include/8195_Register_DRAMC_AO.h A src/vendorcode/mediatek/mt8195/include/8195_Register_DRAMC_NAO.h A src/vendorcode/mediatek/mt8195/include/dramc_actiming.h A src/vendorcode/mediatek/mt8195/include/dramc_common.h A src/vendorcode/mediatek/mt8195/include/dramc_custom.h A src/vendorcode/mediatek/mt8195/include/dramc_dv_init.h A src/vendorcode/mediatek/mt8195/include/dramc_int_global.h A src/vendorcode/mediatek/mt8195/include/dramc_int_slt.h A src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h A src/vendorcode/mediatek/mt8195/include/dramc_register.h A src/vendorcode/mediatek/mt8195/include/dramc_top.h A src/vendorcode/mediatek/mt8195/include/dramc_typedefs.h A src/vendorcode/mediatek/mt8195/include/emi.h A src/vendorcode/mediatek/mt8195/include/emi_hw.h A src/vendorcode/mediatek/mt8195/include/emi_mpu_mt.h A src/vendorcode/mediatek/mt8195/include/mt8195.h A src/vendorcode/mediatek/mt8195/include/pll.h A src/vendorcode/mediatek/mt8195/include/print.h A src/vendorcode/mediatek/mt8195/include/reg.h A src/vendorcode/mediatek/mt8195/include/sv_c_data_traffic.h A src/vendorcode/mediatek/mt8195/include/x_hal_io.h 46 files changed, 96,771 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved -- To view, visit https://review.coreboot.org/c/coreboot/+/54230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iada3ec5ae8a39a8e9253caba550c834d486dddcd Gerrit-Change-Number: 54230 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8195: Initialize DRAM in romstage
by Hung-Te Lin (Code Review) 13 May '21

13 May '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54229 ) Change subject: soc/mediatek/mt8195: Initialize DRAM in romstage ...................................................................... soc/mediatek/mt8195: Initialize DRAM in romstage Initialize DRAM in romstage and configure to support fast calibration. Change-Id: I89b87be62c8e88ae4a620d56aa7a35e47f97952d Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54229 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8195/Kconfig M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/include/soc/dramc_soc.h D src/soc/mediatek/mt8195/include/soc/emi.h 4 files changed, 66 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8195/Kconfig b/src/soc/mediatek/mt8195/Kconfig index bed3e04..203e925 100644 --- a/src/soc/mediatek/mt8195/Kconfig +++ b/src/soc/mediatek/mt8195/Kconfig @@ -5,6 +5,7 @@ select ARCH_VERSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_RAMSTAGE_ARMV8_64 + select CACHE_MRC_SETTINGS select HAVE_UART_SPECIAL select SOC_MEDIATEK_COMMON select CLEAR_WDT_MODE_REG diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index a04ccf4..7cbfa8e 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -22,10 +22,14 @@ romstage-y += ../common/cbmem.c romstage-y += ../common/clkbuf.c +romstage-y += ../common/dram_init.c +romstage-y += ../common/dramc_param.c romstage-y += emi.c romstage-y += ../common/flash_controller.c romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/i2c.c i2c.c +romstage-y += ../common/memory.c +romstage-y += ../common/memory_test.c romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-y += ../common/pll.c pll.c romstage-y += scp.c @@ -55,8 +59,19 @@ ramstage-y += ../common/wdt.c ramstage-y += mt6360.c +MT8195_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8195 + +DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram +$(DRAM_CBFS)-file := $(MT8195_BLOB_DIR)/dram.elf +$(DRAM_CBFS)-type := stage +$(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +ifneq ($(wildcard $($(DRAM_CBFS)-file)),) + cbfs-files-y += $(DRAM_CBFS) +endif + CPPFLAGS_common += -Isrc/soc/mediatek/mt8195/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include +CPPFLAGS_common += -Isrc/vendorcode/mediatek/mt8195/include $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin ./util/mtkheader/gen-bl-img.py mt8183 sf $< $@ diff --git a/src/soc/mediatek/mt8195/include/soc/dramc_soc.h b/src/soc/mediatek/mt8195/include/soc/dramc_soc.h new file mode 100644 index 0000000..6040297 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/dramc_soc.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8195_DRAMC_SOC_H__ +#define __SOC_MEDIATEK_MT8195_DRAMC_SOC_H__ + +typedef enum { + CHANNEL_A = 0, + CHANNEL_B, + CHANNEL_C, + CHANNEL_D, + CHANNEL_MAX, +} DRAM_CHANNEL_T; + +typedef enum { + RANK_0 = 0, + RANK_1, + RANK_MAX, +} DRAM_RANK_T; + +/* DRAM SHUFFLE register type */ +typedef enum { + DRAM_DFS_SHUFFLE_1 = 0, + DRAM_DFS_SHUFFLE_2, + DRAM_DFS_SHUFFLE_3, + DRAM_DFS_SHUFFLE_4, + DRAM_DFS_SHUFFLE_5, + DRAM_DFS_SHUFFLE_6, + DRAM_DFS_SHUFFLE_7, + DRAM_DFS_SHUFFLE_MAX, +} DRAM_DFS_SHUFFLE_TYPE_T; + +/* + * Internal CBT mode enum + * 1. Calibration flow uses vGet_Dram_CBT_Mode to + * differentiate between mixed vs non-mixed LP4 + * 2. Declared as dram_cbt_mode[RANK_MAX] internally to + * store each rank's CBT mode type + */ +typedef enum { + CBT_NORMAL_MODE = 0, + CBT_BYTE_MODE1, +} DRAM_CBT_MODE_T; + +#define DRAM_DFS_SHU_MAX DRAM_DFS_SHUFFLE_MAX + +#define DQS_NUMBER_LP4 2 +#define DQS_BIT_NUMBER 8 +#define DQ_DATA_WIDTH_LP4 16 + +#endif /* __SOC_MEDIATEK_MT8195_DRAMC_SOC_H__ */ diff --git a/src/soc/mediatek/mt8195/include/soc/emi.h b/src/soc/mediatek/mt8195/include/soc/emi.h deleted file mode 100644 index 33ff1bf..0000000 --- a/src/soc/mediatek/mt8195/include/soc/emi.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef SOC_MEDIATEK_MT8195_EMI_H -#define SOC_MEDIATEK_MT8195_EMI_H - -#include <stddef.h> - -size_t sdram_size(void); - -#endif /* SOC_MEDIATEK_MT8195_EMI_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/54229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89b87be62c8e88ae4a620d56aa7a35e47f97952d Gerrit-Change-Number: 54229 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit May 2021