coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: [WIP]amdfwtool: Move the reset image outside the BIOS directory
by Bao Zheng (Code Review) 14 May '21

14 May '21

Attention is currently required from: ritul guru, Zheng Bao. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54293 ) Change subject: [WIP]amdfwtool: Move the reset image outside the BIOS directory ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Quick upload for testing. -- To view, visit https://review.coreboot.org/c/coreboot/+/54293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c511267c3ab23208151f19d39c78be2d26fd6b6 Gerrit-Change-Number: 54293 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Fri, 14 May 2021 07:16:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cherry: Add DRAM calibration support
by Rex-BC Chen (Code Review) 14 May '21

14 May '21

Attention is currently required from: Rex-BC Chen. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54269 to look at the new patch set (#9). Change subject: mb/google/cherry: Add DRAM calibration support ...................................................................... mb/google/cherry: Add DRAM calibration support Initialize and calibrate DRAM in romstage. Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.com> Change-Id: Ib7677baef126ee60bf35da3a4eaf720eaa118a27 --- M src/mainboard/google/cherry/Makefile.inc A src/mainboard/google/cherry/boardid.c M src/mainboard/google/cherry/romstage.c A src/mainboard/google/cherry/sdram_configs.c 4 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/54269/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/54269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7677baef126ee60bf35da3a4eaf720eaa118a27 Gerrit-Change-Number: 54269 Gerrit-PatchSet: 9 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/cherry: Add DRAM calibration support
by Rex-BC Chen (Code Review) 14 May '21

14 May '21

Attention is currently required from: Rex-BC Chen. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54269 to look at the new patch set (#8). Change subject: mb/google/cherry: Add DRAM calibration support ...................................................................... mb/google/cherry: Add DRAM calibration support Initialize and calibrate DRAM in romstage. Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.com> Change-Id: Ib7677baef126ee60bf35da3a4eaf720eaa118a27 --- M src/mainboard/google/cherry/Makefile.inc A src/mainboard/google/cherry/boardid.c M src/mainboard/google/cherry/romstage.c A src/mainboard/google/cherry/sdram_configs.c 4 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/54269/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/54269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7677baef126ee60bf35da3a4eaf720eaa118a27 Gerrit-Change-Number: 54269 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer/v/volteer2: Add config for passive USB-C DB on C1
by Caveh Jalali (Code Review) 14 May '21

14 May '21

Attention is currently required from: Kevin Chang. Hello build bot (Jenkins), Kevin Chang, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Nick Vaccaro, Brandon Breitenstein, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47501 to look at the new patch set (#15). Change subject: mb/google/volteer/v/volteer2: Add config for passive USB-C DB on C1 ...................................................................... mb/google/volteer/v/volteer2: Add config for passive USB-C DB on C1 This enables support for a passive USB-C daughterboard on volteer. This board has no retimers or redrivers which makes it functionally very similar to the USB-C port on the MLB. Since there is no external logic, all mux-ing happens in the TCSS. Also, the AUX DC biasing is controlled by SoC GPIO pins which must also be explicitly enabled. BRANCH=volteer BUG=b:163476857 Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/mainboard/google/volteer/fw_config.c M src/mainboard/google/volteer/mainboard.c M src/mainboard/google/volteer/variants/baseboard/gpio.c M src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/volteer/variants/volteer2/gpio.c M src/mainboard/google/volteer/variants/volteer2/variant.c 6 files changed, 54 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/47501/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/47501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Gerrit-Change-Number: 47501 Gerrit-PatchSet: 15 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/cherry: Add DRAM calibration support
by build bot (Jenkins) (Code Review) 14 May '21

14 May '21

Attention is currently required from: Rex-BC Chen. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54269 ) Change subject: mb/google/cherry: Add DRAM calibration support ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/cherry/sdram_configs.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119303): https://review.coreboot.org/c/coreboot/+/54269/comment/46c7da7d_e3ee4d24 PS7, Line 9: * automatically detect dram information, including channel, rank, die size..., trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/54269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7677baef126ee60bf35da3a4eaf720eaa118a27 Gerrit-Change-Number: 54269 Gerrit-PatchSet: 7 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Fri, 14 May 2021 07:09:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cherry: Add DRAM calibration support
by Rex-BC Chen (Code Review) 14 May '21

14 May '21

Attention is currently required from: Rex-BC Chen. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54269 to look at the new patch set (#7). Change subject: mb/google/cherry: Add DRAM calibration support ...................................................................... mb/google/cherry: Add DRAM calibration support Initialize and calibrate DRAM in romstage. Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.com> Change-Id: Ib7677baef126ee60bf35da3a4eaf720eaa118a27 --- M src/mainboard/google/cherry/Makefile.inc A src/mainboard/google/cherry/boardid.c M src/mainboard/google/cherry/romstage.c A src/mainboard/google/cherry/sdram_configs.c 4 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/54269/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/54269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7677baef126ee60bf35da3a4eaf720eaa118a27 Gerrit-Change-Number: 54269 Gerrit-PatchSet: 7 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: payload/tianocore: Drop TIANOCORE_TARGET_IA32
by Lance Zhao (Code Review) 14 May '21

14 May '21

Attention is currently required from: Bora Guvendik, Lijian Zhao, Martin Roth, Matt DeVillier, John Zhao, Stefan Reinauer, Angel Pons. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54189 ) Change subject: payload/tianocore: Drop TIANOCORE_TARGET_IA32 ...................................................................... Patch Set 7: (1 comment) File payloads/external/tianocore/Makefile: https://review.coreboot.org/c/coreboot/+/54189/comment/20153f05_4ad2a085 PS6, Line 35: ARCH=-a IA32 -a X64 > Ack Done. -- To view, visit https://review.coreboot.org/c/coreboot/+/54189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadd9a3c455fad4eede8a0a017415acd2c57fba04 Gerrit-Change-Number: 54189 Gerrit-PatchSet: 7 Gerrit-Owner: Lance Zhao Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 14 May 2021 07:08:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lance Zhao Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: payload/tianocore: Drop TIANOCORE_TARGET_IA32
by Arthur Heymans (Code Review) 14 May '21

14 May '21

Attention is currently required from: Lance Zhao, Bora Guvendik, Lijian Zhao, Martin Roth, Matt DeVillier, John Zhao, Stefan Reinauer, Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54189 ) Change subject: payload/tianocore: Drop TIANOCORE_TARGET_IA32 ...................................................................... Patch Set 7: (1 comment) File payloads/external/tianocore/Kconfig: https://review.coreboot.org/c/coreboot/+/54189/comment/8530f806_b1740cf8 PS7, Line 37: choice : prompt "Target architecture" : default TIANOCORE_TARGET_X64 : help : The Tianocore coreboot Payload Package binary can be : built for either only IA32 or both X64 and IA32 architectures. : Select which architecture(s) to build for; default is to build : for both X64 and IA32. : : config TIANOCORE_TARGET_X64 : bool "X64" : help : By selecting this option, the target architecture will be built : for X64 and IA32. : : endchoice Does it make sense to keep this? -- To view, visit https://review.coreboot.org/c/coreboot/+/54189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadd9a3c455fad4eede8a0a017415acd2c57fba04 Gerrit-Change-Number: 54189 Gerrit-PatchSet: 7 Gerrit-Owner: Lance Zhao Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lance Zhao Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 14 May 2021 07:08:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/v/volteer2: Add config for passive USB-C DB on C1
by Caveh Jalali (Code Review) 14 May '21

14 May '21

Attention is currently required from: Kevin Chang, Caveh Jalali. Hello build bot (Jenkins), Kevin Chang, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Nick Vaccaro, Brandon Breitenstein, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47501 to look at the new patch set (#14). Change subject: mb/google/volteer/v/volteer2: Add config for passive USB-C DB on C1 ...................................................................... mb/google/volteer/v/volteer2: Add config for passive USB-C DB on C1 This enables support for a passive USB-C daughterboard on volteer. This board has no retimers or redrivers which makes it functionally very similar to the USB-C port on the MLB. Since there is no external logic, all mux-ing happens in the TCSS. Also, the AUX DC biasing is controlled by SoC GPIO pins which must also be explicitly enabled. BRANCH=volteer BUG=b:163476857 Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/mainboard/google/volteer/fw_config.c M src/mainboard/google/volteer/mainboard.c M src/mainboard/google/volteer/variants/baseboard/gpio.c M src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/volteer/variants/volteer2/gpio.c M src/mainboard/google/volteer/variants/volteer2/variant.c 6 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/47501/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/47501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Gerrit-Change-Number: 47501 Gerrit-PatchSet: 14 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/cherry: Add DRAM calibration support
by Yu-Ping Wu (Code Review) 14 May '21

14 May '21

Attention is currently required from: Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54269 ) Change subject: mb/google/cherry: Add DRAM calibration support ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/cherry/sdram_configs.c: https://review.coreboot.org/c/coreboot/+/54269/comment/f8f64f55_0fb8bad8 PS6, Line 7: /* : * Currently ddr_geometry and ddr_type are not used in Cherry. : * This function is declared for common dram init flow. : */ : static struct sdram_info params; : : params.ddr_geometry = DDR_TYPE_2CH_2RK_6GB_3_3; : params.ddr_type = DDR_TYPE_EMCP; : > If MT8195 really won't use these features, then I think we should say […] s/dummy/placeholder -- To view, visit https://review.coreboot.org/c/coreboot/+/54269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7677baef126ee60bf35da3a4eaf720eaa118a27 Gerrit-Change-Number: 54269 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Fri, 14 May 2021 07:02:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit May 2021