coreboot-gerrit May 2021

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Change in coreboot[master]: mb/google/brya: Use FW_CONFIG LTE_PCIE to turn on/off the PCIE6
by Patrick Georgi (Code Review) 14 May '21

14 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54173 ) Change subject: mb/google/brya: Use FW_CONFIG LTE_PCIE to turn on/off the PCIE6 ...................................................................... mb/google/brya: Use FW_CONFIG LTE_PCIE to turn on/off the PCIE6 PCIE6 only needed when use the PCIE LTE. BUG=b:180166408 BRANCH=none TEST=FM350 can/can't be detected when enable/disable this config. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I9dce05fdb6eb956a054d3815ff706b94f0d3fc37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54173 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/brya0/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index ccc0384..452e1d8 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -122,6 +122,9 @@ device generic 0 on end end end + device ref pcie_rp6 on + probe DB_LTE LTE_PCIE + end device ref pcie_rp8 on chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" -- To view, visit https://review.coreboot.org/c/coreboot/+/54173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dce05fdb6eb956a054d3815ff706b94f0d3fc37 Gerrit-Change-Number: 54173 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Add the first FW_CONFIG fields to brya0
by Patrick Georgi (Code Review) 14 May '21

14 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54097 ) Change subject: mb/google/brya: Add the first FW_CONFIG fields to brya0 ...................................................................... mb/google/brya: Add the first FW_CONFIG fields to brya0 1) USB sub-board 2) SD sub-board 3) GSC 4) Keyboard backlight 5) Audio sub-board 6) LTE module Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I74ca5ab5366a17e9e1784ec872b9cd77f8663c7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54097 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Zhuohao Lee <zhuohao(a)google.com> Reviewed-by: YH Lin <yueherngl(a)google.com> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/brya0/overridetree.cb 2 files changed, 33 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved YH Lin: Looks good to me, but someone else must approve Zhuohao Lee: Looks good to me, but someone else must approve EricR Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index faa5335..c28c293 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -14,6 +14,8 @@ select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_SKUID + select FW_CONFIG + select FW_CONFIG_SOURCE_CHROMEEC_CBI select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index f56b8d6..ccc0384 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -1,3 +1,34 @@ +fw_config + field DB_USB 0 3 + option USB_ABSENT 0 + option USB3_PS8815 1 + end + field DB_SD 4 5 + option SD_ABSENT 0 + option SD_GL9755S 1 + end + field GSC 6 6 + option H1D 0 + option H1B 1 + end + field KB_BL 7 7 + option KB_BL_ABSENT 0 + option KB_BL_PRESENT 1 + end + field AUDIO 8 10 + option AUDIO_UNKNOWN 0 + option MAX98357_ALC5682I_I2S 1 + option MAX98373_ALC5682_SNDW 2 + option MAX98373_NAU88L25B_I2S 3 + option ALC1019_NAU88L25B_I2S 4 + end + field DB_LTE 11 12 + option LTE_ABSENT 0 + option LTE_USB 1 + option LTE_PCIE 2 + end +end + chip soc/intel/alderlake register "SaGv" = "SaGv_Disabled" -- To view, visit https://review.coreboot.org/c/coreboot/+/54097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74ca5ab5366a17e9e1784ec872b9cd77f8663c7f Gerrit-Change-Number: 54097 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Add the first FW_CONFIG fields to brya0
by Patrick Georgi (Code Review) 14 May '21

14 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, EricR Lai. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54097 ) Change subject: mb/google/brya: Add the first FW_CONFIG fields to brya0 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74ca5ab5366a17e9e1784ec872b9cd77f8663c7f Gerrit-Change-Number: 54097 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Fri, 14 May 2021 08:55:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: acpi: Add acpigen_write_thermal_zone
by Patrick Georgi (Code Review) 14 May '21

14 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54131 ) Change subject: acpi: Add acpigen_write_thermal_zone ...................................................................... acpi: Add acpigen_write_thermal_zone BUG=b:186166365 TEST=Compiles Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Icf88477143049119036c00276f9a01985dc0b4d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54131 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/acpi/acpigen.c M src/include/acpi/acpigen.h 2 files changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Lance Zhao: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 5c8c1b9..9818dc2 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -781,6 +781,13 @@ acpigen_emit_namestring(name); } +void acpigen_write_thermal_zone(const char *name) +{ + acpigen_emit_ext_op(THERMAL_ZONE_OP); + acpigen_write_len_f(); + acpigen_emit_namestring(name); +} + void acpigen_write_STA(uint8_t status) { /* diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index 0e8d29a..2d0bb77 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -338,6 +338,11 @@ { acpigen_pop_len(); } +void acpigen_write_thermal_zone(const char *name); +inline void acpigen_write_thermal_zone_end(void) +{ + acpigen_pop_len(); +} void acpigen_write_LPI_package(u64 level, const struct acpi_lpi_state *states, u16 nentries); void acpigen_write_PPC(u8 nr); void acpigen_write_PPC_NVS(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/54131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf88477143049119036c00276f9a01985dc0b4d3 Gerrit-Change-Number: 54131 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: security/intel/txt: Split of microcode error type printing
by build bot (Jenkins) (Code Review) 14 May '21

14 May '21

Attention is currently required from: Angel Pons. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54092 ) Change subject: security/intel/txt: Split of microcode error type printing ...................................................................... Patch Set 4: (40 comments) File src/security/intel/txt/logging.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/5f06cbe4_f0dd1e54 PS4, Line 15: [0] = "Legacy Shutdown", code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/c7883912_aaf2a2bc PS4, Line 15: [0] = "Legacy Shutdown", please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/1d20aef0_75d6ab7b PS4, Line 15: [0] = "Legacy Shutdown", please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/d0546eda_9bff9f83 PS4, Line 16: [5] = "Load memory type error in ACM area", code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/ee31e429_c9438206 PS4, Line 16: [5] = "Load memory type error in ACM area", please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/4ab40231_fe0649a2 PS4, Line 16: [5] = "Load memory type error in ACM area", please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/6649859c_4732da5b PS4, Line 17: [6] = "Unrecognized ACM format", code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/0237722b_6daa6c7e PS4, Line 17: [6] = "Unrecognized ACM format", please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/14d1d172_a8280555 PS4, Line 17: [6] = "Unrecognized ACM format", please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/07bd2a1f_0d526349 PS4, Line 18: [7] = "Failure to authenticate", code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/8335606a_b92e9bd0 PS4, Line 18: [7] = "Failure to authenticate", please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/5e6c858e_f5f63204 PS4, Line 18: [7] = "Failure to authenticate", please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/ea70322b_25d9ac89 PS4, Line 19: [8] = "Invalid ACM format", code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/a33c30a8_e5cf6ee7 PS4, Line 19: [8] = "Invalid ACM format", please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/3db52e9f_222e53ac PS4, Line 19: [8] = "Invalid ACM format", please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/93d2e078_c4f6f741 PS4, Line 20: [9] = "Unexpected Snoop hit", code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/5bf15e1e_8513fcf1 PS4, Line 20: [9] = "Unexpected Snoop hit", please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/248d9185_42566193 PS4, Line 20: [9] = "Unexpected Snoop hit", please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/90becf0e_cb573e14 PS4, Line 21: [10] = "Invalid event", code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/93cfd00a_0a0bd921 PS4, Line 21: [10] = "Invalid event", please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/1eb3c83b_78696e4e PS4, Line 21: [10] = "Invalid event", please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/770f6b42_3425161b PS4, Line 22: [11] = "Invalid MLE", code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/53c8dd60_131b1632 PS4, Line 22: [11] = "Invalid MLE", please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/9b504824_1890ae8c PS4, Line 22: [11] = "Invalid MLE", please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/148f2876_0476a5df PS4, Line 23: [12] = "Machine check event", code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/0f2ae0eb_36b7ec09 PS4, Line 23: [12] = "Machine check event", please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/fe2684bd_3b14923e PS4, Line 23: [12] = "Machine check event", please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/bbde4841_0abab4a9 PS4, Line 24: [13] = "VMXAbort", code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/898128f4_589b5a9f PS4, Line 24: [13] = "VMXAbort", please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/d49ccf65_1b6a2de3 PS4, Line 24: [13] = "VMXAbort", please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/2fdc2e9e_96a7e05b PS4, Line 25: [14] = "AC memory corruption", code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/d459fd8c_26b29e09 PS4, Line 25: [14] = "AC memory corruption", please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/23ec6a5c_a02f3f0a PS4, Line 25: [14] = "AC memory corruption", please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/c72c4dc8_b0b38226 PS4, Line 26: [15] = "Illegal voltage/bus ratio", code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/154c1f58_e37129b1 PS4, Line 26: [15] = "Illegal voltage/bus ratio", please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/52d2e3d8_13b23e96 PS4, Line 26: [15] = "Illegal voltage/bus ratio", please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/475f0b31_b6bf8956 PS4, Line 27: }; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/98b22ef1_6f553598 PS4, Line 27: }; please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/40dd4911_c30d3196 PS4, Line 27: }; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119316): https://review.coreboot.org/c/coreboot/+/54092/comment/e6a1730c_7ba7b666 PS4, Line 50: printk(BIOS_ERR, "%s\n", intel_txt_processor_error_type(txt_error & TXT_ERROR_MASK)); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/54092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I435de402fef6d4702c9c7250c8bd31243a04a46e Gerrit-Change-Number: 54092 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 14 May 2021 08:38:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/cbnt: Add logging
by build bot (Jenkins) (Code Review) 14 May '21

14 May '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Morgan Jang, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54093 ) Change subject: security/intel/cbnt: Add logging ...................................................................... Patch Set 8: (8 comments) File src/security/intel/cbnt/logging.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119317): https://review.coreboot.org/c/coreboot/+/54093/comment/216ed477_b499f3be PS8, Line 21: uint64_t : 24; space prohibited before that ':' (ctx:WxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119317): https://review.coreboot.org/c/coreboot/+/54093/comment/365cceca_6d300120 PS8, Line 23: uint64_t : 1; space prohibited before that ':' (ctx:WxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119317): https://review.coreboot.org/c/coreboot/+/54093/comment/82c02cd1_1f7d9df6 PS8, Line 25: uint64_t : 29; space prohibited before that ':' (ctx:WxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119317): https://review.coreboot.org/c/coreboot/+/54093/comment/2552c5dd_89660b73 PS8, Line 42: uint64_t : 59; space prohibited before that ':' (ctx:WxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119317): https://review.coreboot.org/c/coreboot/+/54093/comment/c8d90ac1_c55f633d PS8, Line 57: uint32_t : 15; space prohibited before that ':' (ctx:WxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119317): https://review.coreboot.org/c/coreboot/+/54093/comment/1ccb3f1e_dfae0f0d PS8, Line 67: uint32_t : 5; space prohibited before that ':' (ctx:WxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119317): https://review.coreboot.org/c/coreboot/+/54093/comment/eee5cd1f_a8b17415 PS8, Line 84: uint32_t : 2; space prohibited before that ':' (ctx:WxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119317): https://review.coreboot.org/c/coreboot/+/54093/comment/64fcd1d1_c578b628 PS8, Line 95: uint32_t : 6; space prohibited before that ':' (ctx:WxW) -- To view, visit https://review.coreboot.org/c/coreboot/+/54093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b57132bedbd944b9861ab0e2e0d14723cb61635 Gerrit-Change-Number: 54093 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 14 May 2021 08:38:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/txt: Split of microcode error type printing
by Arthur Heymans (Code Review) 14 May '21

14 May '21

Attention is currently required from: Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54092 ) Change subject: security/intel/txt: Split of microcode error type printing ...................................................................... Patch Set 3: (3 comments) File src/security/intel/txt/logging.c: https://review.coreboot.org/c/coreboot/+/54092/comment/19245281_651a3852 PS3, Line 12: microcode > Document 315168-017 calls these "processor-initiated Intel TXT shutdowns". […] Done https://review.coreboot.org/c/coreboot/+/54092/comment/c0ce32d0_318235af PS3, Line 14: types > Maybe call this `names` to avoid confusion with the `type` parameter? Done https://review.coreboot.org/c/coreboot/+/54092/comment/fedd0921_95ff3dd3 PS3, Line 31: }; > There's a much better way to do this: > > const char *intel_txt_processor_error_type(uint8_t type) > { > static const char *const names[] = { > [0] = "Legacy Shutdown", > [5] = "Load memory type error in ACM area", > [6] = "Unrecognized ACM format", > [7] = "Failure to authenticate", > [8] = "Invalid ACM format", > [9] = "Unexpected Snoop hit", > [10] = "Invalid event", > [11] = "Invalid MLE", > [12] = "Machine check event", > [13] = "VMXAbort", > [14] = "AC memory corruption", > [15] = "Illegal voltage/bus ratio", > }; > return type < ARRAY_SIZE(names) && names[type] ? names[type] : "Unknown"; > } > Done > This can be improved even further if one makes the function print the strings directly, and return nothing: > > void intel_txt_log_processor_error(int loglevel, uint8_t type) > { > static const char *const names[] = { > [0] = "Legacy Shutdown", > [5] = "Load memory type error in ACM area", > [6] = "Unrecognized ACM format", > [7] = "Failure to authenticate", > [8] = "Invalid ACM format", > [9] = "Unexpected Snoop hit", > [10] = "Invalid event", > [11] = "Invalid MLE", > [12] = "Machine check event", > [13] = "VMXAbort", > [14] = "AC memory corruption", > [15] = "Illegal voltage/bus ratio", > }; > if (type < ARRAY_SIZE(names) && names[type]) > printk(loglevel, "Error condition: %s\n", names[type]); > else > printk(loglevel, "Error condition: Unknown %u\n", type); > } I prefer to just return strings as it makes it easier to reuse in different error logging parts (cbnt). -- To view, visit https://review.coreboot.org/c/coreboot/+/54092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I435de402fef6d4702c9c7250c8bd31243a04a46e Gerrit-Change-Number: 54092 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 14 May 2021 08:38:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/txt: Always build logginc.c
by Arthur Heymans (Code Review) 14 May '21

14 May '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54295 ) Change subject: security/intel/txt: Always build logginc.c ...................................................................... security/intel/txt: Always build logginc.c Always building makes sure this code gets buildtested. Calling this code already was guarded by "if CONFIG(INTEL_TXT_LOGGING)". Also build this in all stages as future code will use this in bootblock. Change-Id: I654adf16b47513e3279335c8a8ad48b9371d438e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/security/intel/txt/Makefile.inc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/54295/1 diff --git a/src/security/intel/txt/Makefile.inc b/src/security/intel/txt/Makefile.inc index d332341..7132ca8 100644 --- a/src/security/intel/txt/Makefile.inc +++ b/src/security/intel/txt/Makefile.inc @@ -1,17 +1,17 @@ ifeq ($(CONFIG_INTEL_TXT),y) +all-y += logging.c + romstage-y += romstage.c romstage-y += getsec_sclean.S romstage-y += getsec.c romstage-y += common.c -romstage-$(CONFIG_INTEL_TXT_LOGGING) += logging.c ramstage-y += common.c ramstage-y += getsec.c ramstage-y += getsec_enteraccs.S ramstage-y += ramstage.c -ramstage-$(CONFIG_INTEL_TXT_LOGGING) += logging.c cbfs-files-y += $(CONFIG_INTEL_TXT_CBFS_BIOS_ACM) $(CONFIG_INTEL_TXT_CBFS_BIOS_ACM)-file := $(CONFIG_INTEL_TXT_BIOSACM_FILE) -- To view, visit https://review.coreboot.org/c/coreboot/+/54295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I654adf16b47513e3279335c8a8ad48b9371d438e Gerrit-Change-Number: 54295 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/intel/cbnt: Add logging
by Arthur Heymans (Code Review) 14 May '21

14 May '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Morgan Jang, Patrick Rudolph. Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Angel Pons, Morgan Jang, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54093 to look at the new patch set (#8). Change subject: security/intel/cbnt: Add logging ...................................................................... security/intel/cbnt: Add logging This decodes and logs the CBnT status and error registers. Change-Id: I8b57132bedbd944b9861ab0e2e0d14723cb61635 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/security/intel/cbnt/Kconfig M src/security/intel/cbnt/Makefile.inc A src/security/intel/cbnt/cbnt.h A src/security/intel/cbnt/logging.c M src/security/intel/txt/ramstage.c M src/soc/intel/xeon_sp/bootblock.c 6 files changed, 245 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/54093/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/54093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b57132bedbd944b9861ab0e2e0d14723cb61635 Gerrit-Change-Number: 54093 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: security/intel/txt: Split of microcode error type printing
by Arthur Heymans (Code Review) 14 May '21

14 May '21

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54092 to look at the new patch set (#4). Change subject: security/intel/txt: Split of microcode error type printing ...................................................................... security/intel/txt: Split of microcode error type printing The purpose is to reuse the types string in CBnT error printing. Change-Id: I435de402fef6d4702c9c7250c8bd31243a04a46e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/security/intel/txt/logging.c M src/security/intel/txt/txt.h 2 files changed, 23 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/54092/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/54092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I435de402fef6d4702c9c7250c8bd31243a04a46e Gerrit-Change-Number: 54092 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021