coreboot-gerrit May 2021

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Change in coreboot[master]: mb/google/zork: update DRAM table for berknip/dirinboz/gumboz
by Patrick Georgi (Code Review) 14 May '21

14 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54250 ) Change subject: mb/google/zork: update DRAM table for berknip/dirinboz/gumboz ...................................................................... mb/google/zork: update DRAM table for berknip/dirinboz/gumboz Add Samsung DDR4 memory part K4AAG165WB-BCWE 16Gb index was generated by gen_part_id BUG=b:180986354 TEST=none Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> Change-Id: I94b950b51b41767676ab3ddf89e88860c42f5f1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54250 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> --- M src/mainboard/google/zork/variants/berknip/spd/Makefile.inc M src/mainboard/google/zork/variants/berknip/spd/dram_id.generated.txt M src/mainboard/google/zork/variants/berknip/spd/mem_parts_used.txt M src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc M src/mainboard/google/zork/variants/dirinboz/spd/dram_id.generated.txt M src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt M src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc M src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt M src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt 9 files changed, 9 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, approved diff --git a/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc b/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc index 9c66132..b584838 100644 --- a/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc @@ -6,7 +6,7 @@ SPD_SOURCES += ddr4-spd-8.hex # ID = 1(0b0001) Parts = K4AAG165WA-BCTD SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = MT40A512M16TB-062E:J SPD_SOURCES += ddr4-spd-1.hex # ID = 3(0b0011) Parts = H5AN8G6NDJR-XNC -SPD_SOURCES += ddr4-spd-9.hex # ID = 4(0b0100) Parts = H5ANAG6NCJR-XNC +SPD_SOURCES += ddr4-spd-9.hex # ID = 4(0b0100) Parts = H5ANAG6NCJR-XNC, K4AAG165WB-BCWE SPD_SOURCES += ddr4-spd-1.hex # ID = 5(0b0101) Parts = K4A8G165WC-BCWE SPD_SOURCES += ddr4-spd-7.hex # ID = 6(0b0110) Parts = MT40A1G16KD-062E:E SPD_SOURCES += ddr4-spd-2.hex # ID = 7(0b0111) Parts = H5ANAG6NCMR-XNC diff --git a/src/mainboard/google/zork/variants/berknip/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/berknip/spd/dram_id.generated.txt index f475d9f..090dc3e 100644 --- a/src/mainboard/google/zork/variants/berknip/spd/dram_id.generated.txt +++ b/src/mainboard/google/zork/variants/berknip/spd/dram_id.generated.txt @@ -8,3 +8,4 @@ K4AAG165WA-BCWE 8 (1000) K4AAG165WA-BCTD 1 (0001) H5ANAG6NCJR-XNC 4 (0100) +K4AAG165WB-BCWE 4 (0100) diff --git a/src/mainboard/google/zork/variants/berknip/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/berknip/spd/mem_parts_used.txt index 2af091f..e9803b5 100644 --- a/src/mainboard/google/zork/variants/berknip/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/berknip/spd/mem_parts_used.txt @@ -16,3 +16,4 @@ K4AAG165WA-BCWE, 8 K4AAG165WA-BCTD H5ANAG6NCJR-XNC +K4AAG165WB-BCWE diff --git a/src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc index 6d8a906..6d8e749 100644 --- a/src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc @@ -2,7 +2,7 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += ddr4-spd-9.hex # ID = 0(0b0000) Parts = H5ANAG6NCJR-XNC +SPD_SOURCES += ddr4-spd-9.hex # ID = 0(0b0000) Parts = H5ANAG6NCJR-XNC, K4AAG165WB-BCWE SPD_SOURCES += ddr4-spd-empty.hex # ID = 1(0b0001) SPD_SOURCES += ddr4-spd-3.hex # ID = 2(0b0010) Parts = K4A8G165WC-BCTD SPD_SOURCES += ddr4-spd-empty.hex # ID = 3(0b0011) diff --git a/src/mainboard/google/zork/variants/dirinboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/dirinboz/spd/dram_id.generated.txt index d6d5d09..9f9949c 100644 --- a/src/mainboard/google/zork/variants/dirinboz/spd/dram_id.generated.txt +++ b/src/mainboard/google/zork/variants/dirinboz/spd/dram_id.generated.txt @@ -8,3 +8,4 @@ K4AAG165WA-BCTD 9 (1001) K4AAG165WA-BCWE 10 (1010) H5ANAG6NCJR-XNC 0 (0000) +K4AAG165WB-BCWE 0 (0000) diff --git a/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt index 5a6541f..974addb 100644 --- a/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt @@ -16,3 +16,4 @@ K4AAG165WA-BCTD, 9 K4AAG165WA-BCWE, 10 H5ANAG6NCJR-XNC +K4AAG165WB-BCWE diff --git a/src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc index 6d8a906..6d8e749 100644 --- a/src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc @@ -2,7 +2,7 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += ddr4-spd-9.hex # ID = 0(0b0000) Parts = H5ANAG6NCJR-XNC +SPD_SOURCES += ddr4-spd-9.hex # ID = 0(0b0000) Parts = H5ANAG6NCJR-XNC, K4AAG165WB-BCWE SPD_SOURCES += ddr4-spd-empty.hex # ID = 1(0b0001) SPD_SOURCES += ddr4-spd-3.hex # ID = 2(0b0010) Parts = K4A8G165WC-BCTD SPD_SOURCES += ddr4-spd-empty.hex # ID = 3(0b0011) diff --git a/src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt index d6d5d09..9f9949c 100644 --- a/src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt +++ b/src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt @@ -8,3 +8,4 @@ K4AAG165WA-BCTD 9 (1001) K4AAG165WA-BCWE 10 (1010) H5ANAG6NCJR-XNC 0 (0000) +K4AAG165WB-BCWE 0 (0000) diff --git a/src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt index e5cd7e2..f220073 100644 --- a/src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt @@ -17,3 +17,4 @@ K4AAG165WA-BCTD, 9 K4AAG165WA-BCWE, 10 H5ANAG6NCJR-XNC +K4AAG165WB-BCWE -- To view, visit https://review.coreboot.org/c/coreboot/+/54250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94b950b51b41767676ab3ddf89e88860c42f5f1d Gerrit-Change-Number: 54250 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/amd/majolica: Disable IO ports 0x60/0x64
by Patrick Georgi (Code Review) 14 May '21

14 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54071 ) Change subject: mb/amd/majolica: Disable IO ports 0x60/0x64 ...................................................................... mb/amd/majolica: Disable IO ports 0x60/0x64 I suspect there is additional initialization required to enable the 8042 keyboard controller on the EC. By removing the range we no longer encounter long 20 second delays when reading the IO ports. Since depthcharge polls the IO ports it makes it seem like depthcharge locked up. BUG=b:182100027 TEST=Boot majolica with depthcharge to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I56a7eb4200e4615e1b4d9f14594d64f93e031a54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54071 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk(a)gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/amd/majolica/devicetree.cb 1 file changed, 1 insertion(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Jason Glenesk: Looks good to me, but someone else must approve diff --git a/src/mainboard/amd/majolica/devicetree.cb b/src/mainboard/amd/majolica/devicetree.cb index 422c009..0f540a1 100644 --- a/src/mainboard/amd/majolica/devicetree.cb +++ b/src/mainboard/amd/majolica/devicetree.cb @@ -2,8 +2,7 @@ chip soc/amd/cezanne register "common_config.espi_config" = "{ - .std_io_decode_bitmap = ESPI_DECODE_IO_0X60_0X64_EN | ESPI_DECODE_IO_0x80_EN - | ESPI_DECODE_IO_0X2E_0X2F_EN, + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN, .io_mode = ESPI_IO_MODE_QUAD, .op_freq_mhz = ESPI_OP_FREQ_16_MHZ, .crc_check_enable = 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/54071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56a7eb4200e4615e1b4d9f14594d64f93e031a54 Gerrit-Change-Number: 54071 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/clevo/n130wu: Use device alias names in devicetree
by Patrick Georgi (Code Review) 14 May '21

14 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53939 ) Change subject: mb/clevo/n130wu: Use device alias names in devicetree ...................................................................... mb/clevo/n130wu: Use device alias names in devicetree Switch to device alias names in devicetree. Remove unnecessary comments since the names are self-explanatory. Change-Id: Id486d9bd44bd7ba6a93a5f757af487b211e58efa Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53939 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb 1 file changed, 18 insertions(+), 18 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index 0a0cdf4..607e586 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -44,10 +44,10 @@ end device domain 0 on subsystemid 0x1558 0x1313 inherit - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA thermal subsystem - device pci 14.0 on # USB xHCI + device ref system_agent on end + device ref igpu on end + device ref sa_thermal on end + device ref south_xhci on register "SsicPortEnable" = "0" # USB2 register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A, right @@ -63,19 +63,19 @@ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C, right register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, left end - device pci 14.2 on end # Thermal Subsystem - device pci 16.0 on # Management Engine Interface 1 + device ref thermal on end + device ref heci1 on register "HeciEnabled" = "1" end - device pci 17.0 on # SATA + device ref sata on register "SataSalpSupport" = "0" # Ports register "SataPortsEnable[0]" = "1" register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[2]" = "1" end - device pci 19.0 on end # UART 2 - device pci 1c.0 on # PCI Express Port 1 + device ref uart2 on end + device ref pcie_rp1 on device pci 00.0 on end # x4 TBT register "PcieRpEnable[0]" = "1" register "PcieRpClkReqSupport[0]" = "1" @@ -85,7 +85,7 @@ register "PcieRpLtrEnable[0]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "Thunderbolt/Type-C" "SlotDataBusWidth4X" end - device pci 1c.4 on # PCI Express Port 5 + device ref pcie_rp5 on device pci 00.0 on end # x1 LAN register "PcieRpEnable[4]" = "1" register "PcieRpClkReqSupport[4]" = "1" @@ -93,7 +93,7 @@ register "PcieRpClkSrcNumber[4]" = "3" register "PcieRpLtrEnable[4]" = "1" end - device pci 1c.5 on # PCI Express Port 6 + device ref pcie_rp6 on device pci 00.0 on end # x1 WLAN register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "1" @@ -102,7 +102,7 @@ register "PcieRpLtrEnable[5]" = "1" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/A/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" end - device pci 1d.0 on # PCI Express Port 9 + device ref pcie_rp9 on device pci 00.0 on end # x4 M.2/M (J_SSD1) register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" @@ -111,7 +111,7 @@ register "PcieRpLtrEnable[8]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" end - device pci 1f.0 on # LPC Interface + device ref lpc_espi on register "gen1_dec" = "0x000c0681" register "gen2_dec" = "0x000c1641" register "gen3_dec" = "0x00040069" @@ -120,14 +120,14 @@ device pnp 0c31.0 on end end end - device pci 1f.1 hidden end # P2SB - device pci 1f.2 on # Power Management Controller + device ref p2sb hidden end + device ref pmc on register "gpe0_dw0" = "GPP_C" register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" end - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI + device ref hda on end + device ref smbus on end + device ref fast_spi on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/53939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id486d9bd44bd7ba6a93a5f757af487b211e58efa Gerrit-Change-Number: 53939 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/cherry: Add DRAM calibration support
by Rex-BC Chen (Code Review) 14 May '21

14 May '21

Attention is currently required from: Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54269 ) Change subject: mb/google/cherry: Add DRAM calibration support ...................................................................... Patch Set 9: (1 comment) File src/mainboard/google/cherry/sdram_configs.c: https://review.coreboot.org/c/coreboot/+/54269/comment/af87e132_58e832fb PS9, Line 9: die > Is this a typo? What is die size? it' not a typo. die size means dram size. -- To view, visit https://review.coreboot.org/c/coreboot/+/54269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7677baef126ee60bf35da3a4eaf720eaa118a27 Gerrit-Change-Number: 54269 Gerrit-PatchSet: 9 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 14 May 2021 08:59:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: tests: Add lib/spd_cache-test test case
by Patrick Georgi (Code Review) 14 May '21

14 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52938 ) Change subject: tests: Add lib/spd_cache-test test case ...................................................................... tests: Add lib/spd_cache-test test case Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: Ic9a1420e49e1e80d180117c931e630e54c90cd75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52938 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org> --- A tests/include/tests/lib/spd_cache_data.h M tests/lib/Makefile.inc A tests/lib/spd_cache-test.c 3 files changed, 387 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Fagerburg: Looks good to me, approved diff --git a/tests/include/tests/lib/spd_cache_data.h b/tests/include/tests/lib/spd_cache_data.h new file mode 100644 index 0000000..025a43b --- /dev/null +++ b/tests/include/tests/lib/spd_cache_data.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <inttypes.h> + +/* To generate data on Linux perform following steps: + 1) Load kernel modules: i2c-i801, eeprom, ee1004 + 2) Find i2c number with description "SMBus I801 adapter" in `i2cdetect -l` output + 3) Dump SPD (0050 and 0052 are most common addresses): + `xxd -i xxd -i /sys/bus/i2c/drivers/ee1004/0-0050/eeprom` */ + +unsigned char spd_data_ddr4_1[] = { +0x23, 0x10, 0x0c, 0x03, 0x45, 0x21, 0x00, 0x08, 0x00, 0x00, 0x00, 0x03, 0x0a, 0x03, 0x00, 0x00, +0x00, 0x00, 0x08, 0x0c, 0xc0, 0x3f, 0x00, 0x00, 0x70, 0x70, 0x70, 0x11, 0x03, 0x64, 0xf0, 0x0a, +0x20, 0x08, 0x00, 0x05, 0x00, 0xf0, 0x2b, 0x34, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0x36, 0x16, 0x36, +0x16, 0x36, 0x16, 0x36, 0x00, 0x00, 0x2b, 0x0c, 0x2b, 0x0c, 0x2b, 0x0c, 0x2b, 0x0c, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9c, 0xb4, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc1, 0xe2, 0x32, +0x11, 0x11, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xde, 0x27, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x80, 0xad, 0x00, 0x20, 0x14, 0x00, 0x00, 0x00, 0x34, 0x00, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, +0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x80, 0xad, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; +unsigned int spd_data_ddr4_1_sz = 512; + +unsigned char spd_data_ddr4_2[] = { +0x23, 0x11, 0x0c, 0x02, 0x85, 0x21, 0x00, 0x08, 0x00, 0x00, 0x00, 0x03, 0x09, 0x03, 0x00, 0x00, +0x00, 0x00, 0x07, 0x0d, 0xfc, 0x2b, 0x00, 0x00, 0x6b, 0x6b, 0x6b, 0x11, 0x00, 0x6b, 0xf0, 0x0a, +0x20, 0x08, 0x00, 0x05, 0x00, 0xa8, 0x1b, 0x28, 0x28, 0x00, 0x78, 0x00, 0x14, 0x3c, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0x36, 0x16, 0x36, +0x16, 0x36, 0x16, 0x36, 0x00, 0x20, 0x2b, 0x0c, 0x2b, 0x0c, 0x2b, 0x0c, 0x2b, 0x0c, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9c, 0xb4, 0xc9, 0xc9, 0xc9, 0xc9, 0xe7, 0xd6, 0xea, 0x05, +0x11, 0x11, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xde, 0x27, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x85, 0x9b, 0x00, 0x00, 0x00, 0x39, 0x82, 0x07, 0x7b, 0x42, 0x4c, 0x53, 0x31, 0x36, 0x47, 0x34, +0x44, 0x32, 0x34, 0x30, 0x46, 0x53, 0x45, 0x2e, 0x31, 0x36, 0x46, 0x42, 0x44, 0x00, 0x80, 0x2c, +0x00, 0x44, 0x50, 0x41, 0x47, 0x48, 0x34, 0x47, 0x30, 0x30, 0x31, 0xff, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x0c, 0x4a, 0x05, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x94, 0x00, 0x00, 0x07, 0xff, 0x3f, 0x00, +0x00, 0x6a, 0x6a, 0x6a, 0x11, 0x00, 0x6b, 0xf0, 0x0a, 0x20, 0x08, 0x00, 0x05, 0x00, 0xa8, 0x1b, +0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xcf, 0xb5, 0xca, 0xca, 0xca, 0xca, 0xd6, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; +unsigned int spd_data_ddr4_2_sz = 512; + +unsigned char spd_data_ddr3_1[] = { + 0x92, 0x13, 0x0b, 0x03, 0x04, 0x21, 0x02, 0x09, 0x03, 0x11, 0x01, 0x08, + 0x0a, 0x00, 0xfe, 0x00, 0x69, 0x78, 0x69, 0x30, 0x69, 0x11, 0x18, 0x81, + 0x20, 0x08, 0x3c, 0x3c, 0x00, 0xf0, 0x83, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0f, 0x11, 0x65, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xce, 0x03, + 0x15, 0x01, 0x19, 0x2b, 0x89, 0x05, 0xcd, 0x0f, 0x4d, 0x34, 0x37, 0x31, + 0x42, 0x31, 0x47, 0x37, 0x33, 0x51, 0x48, 0x30, 0x2d, 0x59, 0x4b, 0x30, + 0x20, 0x20, 0x00, 0x00, 0x80, 0xce, 0x00, 0x00, 0x00, 0x4b, 0x30, 0x47, + 0x4a, 0x30, 0x30, 0x30, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe8, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x37, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; +unsigned int spd_data_ddr3_1_sz = 256; diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index c76870b..0792776 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -28,6 +28,8 @@ tests-y += dimm_info_util-test tests-y += coreboot_table-test tests-y += rtc-test +tests-y += spd_cache-ddr3-test +tests-y += spd_cache-ddr4-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -144,3 +146,24 @@ rtc-test-srcs += tests/lib/rtc-test.c rtc-test-srcs += src/lib/rtc.c +spd_cache-ddr3-test-srcs += tests/lib/spd_cache-test.c +spd_cache-ddr3-test-srcs += tests/stubs/console.c +spd_cache-ddr3-test-srcs += src/lib/spd_cache.c +spd_cache-ddr3-test-srcs += src/lib/crc_byte.c +spd_cache-ddr3-test-srcs += src/commonlib/region.c +spd_cache-ddr3-test-mocks += fmap_locate_area_as_rdev +spd_cache-ddr3-test-config += CONFIG_SPD_CACHE_FMAP_NAME=\"RW_SPD_CACHE\" \ + CONFIG_DIMM_MAX=4 CONFIG_DIMM_SPD_SIZE=256 \ + CONFIG_BOOT_DEVICE_MEMORY_MAPPED=1 +spd_cache-ddr3-test-cflags += -D__TEST_SPD_CACHE_DDR=3 + +spd_cache-ddr4-test-srcs += tests/lib/spd_cache-test.c +spd_cache-ddr4-test-srcs += tests/stubs/console.c +spd_cache-ddr4-test-srcs += src/lib/spd_cache.c +spd_cache-ddr4-test-srcs += src/lib/crc_byte.c +spd_cache-ddr4-test-srcs += src/commonlib/region.c +spd_cache-ddr4-test-mocks += fmap_locate_area_as_rdev +spd_cache-ddr4-test-config += CONFIG_SPD_CACHE_FMAP_NAME=\"RW_SPD_CACHE\" \ + CONFIG_DIMM_MAX=4 CONFIG_DIMM_SPD_SIZE=512 \ + CONFIG_BOOT_DEVICE_MEMORY_MAPPED=1 +spd_cache-ddr4-test-cflags += -D__TEST_SPD_CACHE_DDR=4 diff --git a/tests/lib/spd_cache-test.c b/tests/lib/spd_cache-test.c new file mode 100644 index 0000000..4502ce6 --- /dev/null +++ b/tests/lib/spd_cache-test.c @@ -0,0 +1,257 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <crc_byte.h> +#include <spd_bin.h> +#include <spd_cache.h> +#include <stdlib.h> +#include <string.h> +#include <tests/test.h> +#include <tests/lib/spd_cache_data.h> + +struct region_device flash_rdev_rw; +static char *flash_buffer = NULL; +static size_t flash_buffer_size = 0; + +static int setup_spd_cache(void **state) +{ + flash_buffer_size = SC_SPD_TOTAL_LEN + SC_CRC_LEN; + flash_buffer = malloc(flash_buffer_size); + + if (flash_buffer == NULL) { + flash_buffer_size = 0; + return -1; + } + + rdev_chain_mem_rw(&flash_rdev_rw, flash_buffer, flash_buffer_size); + return 0; +} + +static int setup_spd_cache_test(void **state) +{ + memset(flash_buffer, 0xff, flash_buffer_size); + return 0; +} + +static int teardown_spd_cache(void **state) +{ + rdev_chain_mem_rw(&flash_rdev_rw, NULL, 0); + free(flash_buffer); + flash_buffer = NULL; + flash_buffer_size = 0; + return 0; +} + + +int __wrap_fmap_locate_area_as_rdev(const char *name, struct region_device *area) +{ + return rdev_chain(area, &flash_rdev_rw, 0, flash_buffer_size); +} + +/* This test verifies if load_spd_cache() correctly loads spd_cache pointer and size + from provided region_device. Memory region device is returned by + __wrap_fmap_locate_area_as_rdev() */ +static void test_load_spd_cache(void **state) +{ + uint8_t *spd_cache; + size_t spd_cache_sz; + + assert_int_equal(CB_SUCCESS, load_spd_cache(&spd_cache, &spd_cache_sz)); + assert_ptr_equal(flash_buffer, spd_cache); + assert_int_equal(SC_SPD_TOTAL_LEN + SC_CRC_LEN, spd_cache_sz); +} + +static void calc_spd_cache_crc(uint8_t *spd_cache) +{ + *(uint16_t *)(spd_cache + SC_CRC_OFFSET) = + CRC(spd_cache, SC_SPD_TOTAL_LEN, crc16_byte); +} + +__attribute__((unused)) +static void fill_spd_cache_ddr3(uint8_t *spd_cache, size_t spd_cache_sz) +{ + assert_true(spd_cache_sz >= (spd_data_ddr3_1_sz + sizeof(uint16_t))); + + memcpy(spd_cache, spd_data_ddr3_1, spd_data_ddr3_1_sz); + memset(spd_cache + spd_data_ddr3_1_sz, 0, spd_cache_sz - spd_data_ddr3_1_sz); + calc_spd_cache_crc(spd_cache); +} + +__attribute__((unused)) +static void fill_spd_cache_ddr4(uint8_t *spd_cache, size_t spd_cache_sz) +{ + assert_true(spd_cache_sz >= + (spd_data_ddr4_1_sz + spd_data_ddr4_2_sz + sizeof(uint16_t))); + + memcpy(spd_cache, spd_data_ddr4_1, spd_data_ddr4_1_sz); + memcpy(spd_cache + spd_data_ddr4_1_sz, spd_data_ddr4_2, spd_data_ddr4_2_sz); + memset(spd_cache + spd_data_ddr4_1_sz + spd_data_ddr4_2_sz, 0, + spd_cache_sz - (spd_data_ddr4_1_sz + spd_data_ddr4_2_sz)); + calc_spd_cache_crc(spd_cache); +} + +static void test_spd_fill_from_cache(void **state) +{ + struct spd_block blk; + uint8_t *spd_cache; + size_t spd_cache_sz; + assert_int_equal(CB_SUCCESS, load_spd_cache(&spd_cache, &spd_cache_sz)); + + /* Empty spd cache */ + assert_int_equal(CB_ERR, spd_fill_from_cache(spd_cache, &blk)); + +#if __TEST_SPD_CACHE_DDR == 3 + fill_spd_cache_ddr3(spd_cache, spd_cache_sz); +#elif __TEST_SPD_CACHE_DDR == 4 + fill_spd_cache_ddr4(spd_cache, spd_cache_sz); +#endif + assert_int_equal(CB_SUCCESS, spd_fill_from_cache(spd_cache, &blk)); +} + + +static void test_spd_cache_is_valid(void **state) +{ + uint8_t *spd_cache; + size_t spd_cache_sz; + assert_int_equal(CB_SUCCESS, load_spd_cache(&spd_cache, &spd_cache_sz)); + + /* Empty, incorrect SPD */ + assert_false(spd_cache_is_valid(spd_cache, spd_cache_sz)); + +#if __TEST_SPD_CACHE_DDR == 3 + fill_spd_cache_ddr3(spd_cache, spd_cache_sz); +#elif __TEST_SPD_CACHE_DDR == 4 + fill_spd_cache_ddr4(spd_cache, spd_cache_sz); +#endif + assert_true(spd_cache_is_valid(spd_cache, spd_cache_sz)); +} + + +/* Used for setting `sn` parameter value */ +static u32 get_spd_sn_ret_sn[SC_SPD_NUMS] = { 0 }; +static size_t get_spd_sn_ret_sn_idx = 0; +/* Implementation for testing purposes. */ +enum cb_err get_spd_sn(u8 addr, u32 *sn) +{ + *sn = get_spd_sn_ret_sn[get_spd_sn_ret_sn_idx]; + get_spd_sn_ret_sn_idx = (get_spd_sn_ret_sn_idx + 1) % ARRAY_SIZE(get_spd_sn_ret_sn); + + return mock_type(enum cb_err); +} + +static void get_sn_from_spd_cache(uint8_t *spd_cache, u32 arr[]) +{ + for (int i = 0; i < SC_SPD_NUMS; ++i) + arr[i] = *(u32 *)(spd_cache + SC_SPD_OFFSET(i) + DDR4_SPD_SN_OFF); +} + +/* check_if_dimm_changed() has is used only with DDR4, so there tests are not used for DDR3 */ +__attribute__((unused)) +static void test_check_if_dimm_changed_not_changed(void **state) +{ + uint8_t *spd_cache; + size_t spd_cache_sz; + struct spd_block blk; + + assert_int_equal(CB_SUCCESS, load_spd_cache(&spd_cache, &spd_cache_sz)); + fill_spd_cache_ddr4(spd_cache, spd_cache_sz); + assert_int_equal(CB_SUCCESS, spd_fill_from_cache(spd_cache, &blk)); + + get_sn_from_spd_cache(spd_cache, get_spd_sn_ret_sn); + get_spd_sn_ret_sn_idx = 0; + will_return_count(get_spd_sn, CB_SUCCESS, SC_SPD_NUMS); + assert_false(check_if_dimm_changed(spd_cache, &blk)); +} + +__attribute__((unused)) +static void test_check_if_dimm_changed_sn_error(void **state) +{ + uint8_t *spd_cache; + size_t spd_cache_sz; + struct spd_block blk; + + assert_int_equal(CB_SUCCESS, load_spd_cache(&spd_cache, &spd_cache_sz)); + fill_spd_cache_ddr4(spd_cache, spd_cache_sz); + assert_int_equal(CB_SUCCESS, spd_fill_from_cache(spd_cache, &blk)); + + /* Simulate error */ + will_return_count(get_spd_sn, CB_ERR, 1); + assert_true(check_if_dimm_changed(spd_cache, &blk)); +} + +__attribute__((unused)) +static void test_check_if_dimm_changed_sodimm_lost(void **state) +{ + uint8_t *spd_cache; + size_t spd_cache_sz; + struct spd_block blk; + + assert_int_equal(CB_SUCCESS, load_spd_cache(&spd_cache, &spd_cache_sz)); + fill_spd_cache_ddr4(spd_cache, spd_cache_sz); + assert_int_equal(CB_SUCCESS, spd_fill_from_cache(spd_cache, &blk)); + get_sn_from_spd_cache(spd_cache, get_spd_sn_ret_sn); + memset(spd_cache + spd_data_ddr4_1_sz, 0xff, spd_data_ddr4_2_sz); + + get_spd_sn_ret_sn_idx = 0; + will_return_always(get_spd_sn, CB_SUCCESS); + assert_true(check_if_dimm_changed(spd_cache, &blk)); +} + +__attribute__((unused)) +static void test_check_if_dimm_changed_new_sodimm(void **state) +{ + uint8_t *spd_cache; + size_t spd_cache_sz; + struct spd_block blk; + + assert_int_equal(CB_SUCCESS, load_spd_cache(&spd_cache, &spd_cache_sz)); + fill_spd_cache_ddr4(spd_cache, spd_cache_sz); + assert_int_equal(CB_SUCCESS, spd_fill_from_cache(spd_cache, &blk)); + get_sn_from_spd_cache(spd_cache, get_spd_sn_ret_sn); + memcpy(spd_cache + spd_data_ddr4_1_sz + spd_data_ddr4_2_sz, + spd_data_ddr4_2, spd_data_ddr4_2_sz); + + get_spd_sn_ret_sn_idx = 0; + will_return_always(get_spd_sn, CB_SUCCESS); + assert_true(check_if_dimm_changed(spd_cache, &blk)); +} + +__attribute__((unused)) +static void test_check_if_dimm_changed_sn_changed(void **state) +{ + uint8_t *spd_cache; + size_t spd_cache_sz; + struct spd_block blk; + + assert_int_equal(CB_SUCCESS, load_spd_cache(&spd_cache, &spd_cache_sz)); + fill_spd_cache_ddr4(spd_cache, spd_cache_sz); + assert_int_equal(CB_SUCCESS, spd_fill_from_cache(spd_cache, &blk)); + get_sn_from_spd_cache(spd_cache, get_spd_sn_ret_sn); + *(u32 *)(spd_cache + SC_SPD_OFFSET(0) + DDR4_SPD_SN_OFF) = 0x43211234; + + get_spd_sn_ret_sn_idx = 0; + will_return_always(get_spd_sn, CB_SUCCESS); + assert_true(check_if_dimm_changed(spd_cache, &blk)); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test_setup(test_load_spd_cache, setup_spd_cache_test), + cmocka_unit_test_setup(test_spd_fill_from_cache, setup_spd_cache_test), + cmocka_unit_test_setup(test_spd_cache_is_valid, setup_spd_cache_test), +#if __TEST_SPD_CACHE_DDR == 4 + cmocka_unit_test_setup(test_check_if_dimm_changed_not_changed, + setup_spd_cache_test), + cmocka_unit_test_setup(test_check_if_dimm_changed_sn_error, + setup_spd_cache_test), + cmocka_unit_test_setup(test_check_if_dimm_changed_sodimm_lost, + setup_spd_cache_test), + cmocka_unit_test_setup(test_check_if_dimm_changed_new_sodimm, + setup_spd_cache_test), + cmocka_unit_test_setup(test_check_if_dimm_changed_sn_changed, + setup_spd_cache_test), +#endif + }; + + return cmocka_run_group_tests(tests, setup_spd_cache, teardown_spd_cache); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/52938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9a1420e49e1e80d180117c931e630e54c90cd75 Gerrit-Change-Number: 52938 Gerrit-PatchSet: 6 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add known GPIO virtual wire information
by Patrick Georgi (Code Review) 14 May '21

14 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54088 ) Change subject: soc/intel/alderlake: Add known GPIO virtual wire information ...................................................................... soc/intel/alderlake: Add known GPIO virtual wire information GPIO communities 0, 1, and 4 have virtual wire indexes & bits for at least some of their groups; add the known information into the community definitions. This patch is ported form tigerlake. Change-Id: I2f1e2413d06e8afe4233d7111763cb45b78f845b Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54088 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/gpio.c 1 file changed, 27 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/gpio.c b/src/soc/intel/alderlake/gpio.c index 25f8a3c..6d9e184 100644 --- a/src/soc/intel/alderlake/gpio.c +++ b/src/soc/intel/alderlake/gpio.c @@ -5,6 +5,8 @@ #include <soc/pcr_ids.h> #include <soc/pmc.h> +#define DEFAULT_VW_BASE 0x10 + /* * This file is created based on Intel Alder Lake Processor PCH Datasheet * Document number: 630094 @@ -39,12 +41,22 @@ INTEL_GPP_BASE(GPP_B0, GPP_A0, GPP_ESPI_CLK_LOOPBK, 64), /* GPP_A */ }; +static const struct vw_entries adl_community0_vw[] = { + {GPP_A0, GPP_A23}, + {GPP_B0, GPP_B23}, +}; + static const struct pad_group adl_community1_groups[] = { INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 96), /* GPP_S */ INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 128), /* GPP_H */ INTEL_GPP_BASE(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK, 160), /* GPP_D */ }; +static const struct vw_entries adl_community1_vw[] = { + {GPP_D0, GPP_D19}, + {GPP_H0, GPP_H23}, +}; + /* This community is not visible to the OS */ static const struct pad_group adl_community2_groups[] = { INTEL_GPP(GPD0, GPD0, GPD_DRAM_RESETB), /* GPD */ @@ -61,6 +73,12 @@ INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK, 320), /* GPP_E */ }; +static const struct vw_entries adl_community4_vw[] = { + {GPP_F0, GPP_F23}, + {GPP_C0, GPP_C23}, + {GPP_E0, GPP_E23}, +}; + static const struct pad_group adl_community5_groups[] = { INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 352), /* GPP_R */ INTEL_GPP(GPP_R0, GPP_SPI0_IO_2, GPP_SPI0_CLK), /* GPP_SPI0 */ @@ -86,6 +104,9 @@ .num_reset_vals = ARRAY_SIZE(rst_map), .groups = adl_community0_groups, .num_groups = ARRAY_SIZE(adl_community0_groups), + .vw_base = DEFAULT_VW_BASE, + .vw_entries = adl_community0_vw, + .num_vw_entries = ARRAY_SIZE(adl_community0_vw), }, [COMM_1] = { /* GPP S, D, H */ .port = PID_GPIOCOM1, @@ -106,6 +127,9 @@ .num_reset_vals = ARRAY_SIZE(rst_map), .groups = adl_community1_groups, .num_groups = ARRAY_SIZE(adl_community1_groups), + .vw_base = DEFAULT_VW_BASE, + .vw_entries = adl_community1_vw, + .num_vw_entries = ARRAY_SIZE(adl_community1_vw), }, [COMM_2] = { /* GPD */ .port = PID_GPIOCOM2, @@ -165,6 +189,9 @@ .num_reset_vals = ARRAY_SIZE(rst_map), .groups = adl_community4_groups, .num_groups = ARRAY_SIZE(adl_community4_groups), + .vw_base = DEFAULT_VW_BASE, + .vw_entries = adl_community4_vw, + .num_vw_entries = ARRAY_SIZE(adl_community4_vw), }, [COMM_5] = { /* GPP R, SPI0 */ .port = PID_GPIOCOM5, -- To view, visit https://review.coreboot.org/c/coreboot/+/54088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f1e2413d06e8afe4233d7111763cb45b78f845b Gerrit-Change-Number: 54088 Gerrit-PatchSet: 2 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add known CPU Port IDs for GPIO communities
by Patrick Georgi (Code Review) 14 May '21

14 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54087 ) Change subject: soc/intel/alderlake: Add known CPU Port IDs for GPIO communities ...................................................................... soc/intel/alderlake: Add known CPU Port IDs for GPIO communities Change-Id: Id5fa5b10edeb3445a2d2453d9122376041577598 Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54087 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/gpio.c M src/soc/intel/alderlake/include/soc/pcr_ids.h 2 files changed, 11 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/gpio.c b/src/soc/intel/alderlake/gpio.c index ef6f6e4..25f8a3c 100644 --- a/src/soc/intel/alderlake/gpio.c +++ b/src/soc/intel/alderlake/gpio.c @@ -69,6 +69,7 @@ static const struct pad_community adl_communities[] = { [COMM_0] = { /* GPP B, T, A */ .port = PID_GPIOCOM0, + .cpu_port = PID_CPU_GPIOCOM0, .first_pad = GPIO_COM0_START, .last_pad = GPIO_COM0_END, .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, @@ -88,6 +89,7 @@ }, [COMM_1] = { /* GPP S, D, H */ .port = PID_GPIOCOM1, + .cpu_port = PID_CPU_GPIOCOM1, .first_pad = GPIO_COM1_START, .last_pad = GPIO_COM1_END, .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, @@ -126,6 +128,7 @@ }, [COMM_3] = { /* vGPIO */ .port = PID_GPIOCOM3, + .cpu_port = PID_CPU_GPIOCOM3, .first_pad = GPIO_COM3_START, .last_pad = GPIO_COM3_END, .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, @@ -145,6 +148,7 @@ }, [COMM_4] = { /* GPP F, C, HVMOS, E */ .port = PID_GPIOCOM4, + .cpu_port = PID_CPU_GPIOCOM4, .first_pad = GPIO_COM4_START, .last_pad = GPIO_COM4_END, .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, @@ -164,6 +168,7 @@ }, [COMM_5] = { /* GPP R, SPI0 */ .port = PID_GPIOCOM5, + .cpu_port = PID_CPU_GPIOCOM5, .first_pad = GPIO_COM5_START, .last_pad = GPIO_COM5_END, .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, diff --git a/src/soc/intel/alderlake/include/soc/pcr_ids.h b/src/soc/intel/alderlake/include/soc/pcr_ids.h index e4a29c4..9ea075a 100644 --- a/src/soc/intel/alderlake/include/soc/pcr_ids.h +++ b/src/soc/intel/alderlake/include/soc/pcr_ids.h @@ -33,6 +33,12 @@ #define PID_ITSS 0xc4 #define PID_SERIALIO 0xcb +/* CPU Port IDs */ +#define PID_CPU_GPIOCOM0 0xb7 +#define PID_CPU_GPIOCOM1 0xb8 +#define PID_CPU_GPIOCOM3 0xbb +#define PID_CPU_GPIOCOM4 0xb9 +#define PID_CPU_GPIOCOM5 0xba /* * SPI - DMI Destination ID -- To view, visit https://review.coreboot.org/c/coreboot/+/54087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5fa5b10edeb3445a2d2453d9122376041577598 Gerrit-Change-Number: 54087 Gerrit-PatchSet: 2 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add IOM PCR PID
by Patrick Georgi (Code Review) 14 May '21

14 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54086 ) Change subject: soc/intel/alderlake: Add IOM PCR PID ...................................................................... soc/intel/alderlake: Add IOM PCR PID Required for accessing IOM REGBAR space. Change-Id: I883acfa6aa41758e3c8636c94fbee920397fce8b Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54086 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/include/soc/pcr_ids.h 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/include/soc/pcr_ids.h b/src/soc/intel/alderlake/include/soc/pcr_ids.h index e05ecd8..e4a29c4 100644 --- a/src/soc/intel/alderlake/include/soc/pcr_ids.h +++ b/src/soc/intel/alderlake/include/soc/pcr_ids.h @@ -28,6 +28,7 @@ #define PID_PSF2 0xbb #define PID_PSF3 0xbc #define PID_PSF4 0xbd +#define PID_IOM 0xc1 #define PID_RTC 0xc3 #define PID_ITSS 0xc4 #define PID_SERIALIO 0xcb -- To view, visit https://review.coreboot.org/c/coreboot/+/54086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I883acfa6aa41758e3c8636c94fbee920397fce8b Gerrit-Change-Number: 54086 Gerrit-PatchSet: 2 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer/var/volteer: add specific wifi SAR for volta
by Patrick Georgi (Code Review) 14 May '21

14 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54051 ) Change subject: mb/google/volteer/var/volteer: add specific wifi SAR for volta ...................................................................... mb/google/volteer/var/volteer: add specific wifi SAR for volta volta will use different wifi SAR from voxel. Using clamshell mode of fw config to decide to load volta wifi sar. BUG=b:184820057 TEST=build and verify wifi power as expect. Cq-Depend: chrome-internal:3824093 Signed-off-by: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: I000aefca63346c70556688f232ca54360b3badef Reviewed-on: https://review.coreboot.org/c/coreboot/+/54051 Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org> Reviewed-by: YH Lin <yueherngl(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/volteer/Kconfig.name M src/mainboard/google/volteer/variants/voxel/Makefile.inc A src/mainboard/google/volteer/variants/voxel/variant.c 3 files changed, 16 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified YH Lin: Looks good to me, but someone else must approve Sheng-Liang Pan: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved Paul Fagerburg: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index f445b46..c483cc9 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -65,6 +65,7 @@ config BOARD_GOOGLE_VOXEL bool "-> Voxel" select BOARD_GOOGLE_BASEBOARD_VOLTEER + select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR config BOARD_GOOGLE_ELEMI bool "-> Elemi" diff --git a/src/mainboard/google/volteer/variants/voxel/Makefile.inc b/src/mainboard/google/volteer/variants/voxel/Makefile.inc index 3488dc6..310a99c 100644 --- a/src/mainboard/google/volteer/variants/voxel/Makefile.inc +++ b/src/mainboard/google/volteer/variants/voxel/Makefile.inc @@ -6,3 +6,4 @@ ramstage-y += gpio.c ramstage-y += ramstage.c +ramstage-y += variant.c diff --git a/src/mainboard/google/volteer/variants/voxel/variant.c b/src/mainboard/google/volteer/variants/voxel/variant.c new file mode 100644 index 0000000..70fa3a0 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voxel/variant.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <fw_config.h> +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + const char *filename = NULL; + + if (fw_config_probe(FW_CONFIG(TABLETMODE, TABLETMODE_DISABLED))) + filename = "wifi_sar-volta.hex"; + + return filename; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/54051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I000aefca63346c70556688f232ca54360b3badef Gerrit-Change-Number: 54051 Gerrit-PatchSet: 4 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: src/acpi: Add initial support for HMAT
by Patrick Georgi (Code Review) 14 May '21

14 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52047 ) Change subject: src/acpi: Add initial support for HMAT ...................................................................... src/acpi: Add initial support for HMAT Add initial HMAT (Heterogeneous Memory Attribute Table) support based on ACPI spec 6.4 section 5.2.27. Add functions to create HMAT table (revision 2) and create HMAT Memory Proximity Domain Attribute (MPDA) Structure. TESTED=Simulated HMAT table creation on OCP DeltaLake server, dumped the HMAT table and exmained the content. HMAT table and one MPDA structure are added. OCP Delatake server is based on Intel CooperLake Scalable Processor which does not support CXL (Compute Express Link). Therefore solution level testing is not done. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I5ee60ff990c3cea799c5cbdf7eead818b1bb4f9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52047 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/acpi/acpi.c M src/include/acpi/acpi.h 2 files changed, 124 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 5c3fe13..35c5ec3 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -539,6 +539,51 @@ header->checksum = acpi_checksum((void *)srat, header->length); } +int acpi_create_hmat_mpda(acpi_hmat_mpda_t *mpda, u32 initiator, u32 memory) +{ + memset((void *)mpda, 0, sizeof(acpi_hmat_mpda_t)); + + mpda->type = 0; /* Memory Proximity Domain Attributes structure */ + mpda->length = sizeof(acpi_hmat_mpda_t); + /* + * Proximity Domain for Attached Initiator field is valid. + * Bit 1 and bit 2 are reserved since HMAT revision 2. + */ + mpda->flags = (1 << 0); + mpda->proximity_domain_initiator = initiator; + mpda->proximity_domain_memory = memory; + + return mpda->length; +} + +void acpi_create_hmat(acpi_hmat_t *hmat, + unsigned long (*acpi_fill_hmat)(unsigned long current)) +{ + acpi_header_t *header = &(hmat->header); + unsigned long current = (unsigned long)hmat + sizeof(acpi_hmat_t); + + memset((void *)hmat, 0, sizeof(acpi_hmat_t)); + + if (!header) + return; + + /* Fill out header fields. */ + memcpy(header->signature, "HMAT", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->asl_compiler_revision = asl_revision; + header->length = sizeof(acpi_hmat_t); + header->revision = get_acpi_table_revision(HMAT); + + current = acpi_fill_hmat(current); + + /* (Re)calculate length and checksum. */ + header->length = current - (unsigned long)hmat; + header->checksum = acpi_checksum((void *)hmat, header->length); +} + void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags, unsigned long (*acpi_fill_dmar)(unsigned long)) { @@ -1880,6 +1925,8 @@ return 2; case SRAT: /* ACPI 2.0: 1, ACPI 3.0: 2, ACPI 4.0 upto 6.3: 3 */ return 1; /* TODO Should probably be upgraded to 2 */ + case HMAT: /* ACPI 6.4: 2 */ + return 2; case DMAR: return 1; case SLIT: /* ACPI 2.0 upto 6.3: 1 */ diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index b266acf..6aa6cb8 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -71,8 +71,8 @@ enum acpi_tables { /* Tables defined by ACPI and used by coreboot */ - BERT, DBG2, DMAR, DSDT, EINJ, FACS, FADT, HEST, HPET, IVRS, MADT, MCFG, - RSDP, RSDT, SLIT, SRAT, SSDT, TCPA, TPM2, XSDT, ECDT, LPIT, + BERT, DBG2, DMAR, DSDT, EINJ, FACS, FADT, HEST, HMAT, HPET, IVRS, MADT, + MCFG, RSDP, RSDT, SLIT, SRAT, SSDT, TCPA, TPM2, XSDT, ECDT, LPIT, /* Additional proprietary tables used by coreboot */ VFCT, NHLT, SPMI, CRAT }; @@ -208,6 +208,71 @@ u8 reserved[4]; } __packed acpi_mcfg_mmconfig_t; +/* + * HMAT (Heterogeneous Memory Attribute Table) + * ACPI spec 6.4 section 5.2.27 + */ +typedef struct acpi_hmat { + acpi_header_t header; + u32 resv; + /* Followed by HMAT table structure[n] */ +} __packed acpi_hmat_t; + +/* HMAT: Memory Proximity Domain Attributes structure */ +typedef struct acpi_hmat_mpda { + u16 type; /* Type (0) */ + u16 resv; + u32 length; /* Length in bytes (40) */ + u16 flags; + u16 resv1; + u32 proximity_domain_initiator; + u32 proximity_domain_memory; + u32 resv2; + u64 resv3; + u64 resv4; +} __packed acpi_hmat_mpda_t; + +/* HMAT: System Locality Latency and Bandwidth Information structure */ +typedef struct acpi_hmat_sllbi { + u16 type; /* Type (1) */ + u16 resv; + u32 length; /* Length in bytes */ + u8 flags; + u8 data_type; + /* + * Transfer size defined as a 5-biased power of 2 exponent, + * when the bandwidth/latency value is achieved. + */ + u8 min_transfer_size; + u8 resv1; + u32 num_initiator_domains; + u32 num_target_domains; + u32 resv2; + u64 entry_base_unit; + /* Followed by initiator proximity domain list */ + /* Followed by target proximity domain list */ + /* Followed by latency / bandwidth values */ +} __packed acpi_hmat_sllbi_t; + +/* HMAT: Memory Side Cache Information structure */ +typedef struct acpi_hmat_msci { + u16 type; /* Type (2) */ + u16 resv; + u32 length; /* Length in bytes */ + u32 domain; /* Proximity domain for the memory */ + u32 resv1; + u64 cache_size; + /* Describes level, associativity, write policy, cache line size */ + u32 cache_attributes; + u16 resv2; + /* + * Number of SMBIOS handlers that contribute to the + * memory side cache physical devices + */ + u16 num_handlers; + /* Followed by SMBIOS handlers*/ +} __packed acpi_hmat_msci_t; + /* SRAT (System Resource Affinity Table) */ typedef struct acpi_srat { acpi_header_t header; @@ -1162,6 +1227,16 @@ void acpi_create_slit(acpi_slit_t *slit, unsigned long (*acpi_fill_slit)(unsigned long current)); +/* + * Create a Memory Proximity Domain Attributes structure for HMAT, + * given proximity domain for the attached initiaor, and + * proximimity domain for the memory. + */ +int acpi_create_hmat_mpda(acpi_hmat_mpda_t *mpda, u32 initiator, u32 memory); +/* Create Heterogenous Memory Attribute Table */ +void acpi_create_hmat(acpi_hmat_t *hmat, + unsigned long (*acpi_fill_hmat)(unsigned long current)); + void acpi_create_vfct(const struct device *device, acpi_vfct_t *vfct, unsigned long (*acpi_fill_vfct)(const struct device *device, -- To view, visit https://review.coreboot.org/c/coreboot/+/52047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ee60ff990c3cea799c5cbdf7eead818b1bb4f9b Gerrit-Change-Number: 52047 Gerrit-PatchSet: 7 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit May 2021