coreboot-gerrit May 2021

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Change in coreboot[master]: Documentation/distributions: Order vendor list lexicographically
by Patrick Georgi (Code Review) 14 May '21

14 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54272 ) Change subject: Documentation/distributions: Order vendor list lexicographically ...................................................................... Documentation/distributions: Order vendor list lexicographically Change-Id: Id1f27d68124de745ff0eaad669ee86ce0b57ec09 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54272 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M Documentation/distributions.md 1 file changed, 7 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Felix Singer: Looks good to me, approved diff --git a/Documentation/distributions.md b/Documentation/distributions.md index 8401836..d4500a6 100644 --- a/Documentation/distributions.md +++ b/Documentation/distributions.md @@ -8,13 +8,6 @@ ## Hardware shipping with coreboot -### Purism - -[Purism](https://www.puri.sm) sells laptops with a focus on user privacy and -security; part of that effort is to minimize the amount of proprietary and/or -binary code. Their laptops ship with a blob-free OS and coreboot firmware -with a neutralized Intel Management Engine (ME) and SeaBIOS as the payload. - ### ChromeOS Devices All ChromeOS devices ([Chromebooks](https://chromebookdb.com/), Chromeboxes, @@ -36,6 +29,13 @@ third party, [3mdeb](https://3mdeb.com). They provide current and tested firmware binaries on [GitHub](https://pcengines.github.io). +### Purism + +[Purism](https://www.puri.sm) sells laptops with a focus on user privacy and +security; part of that effort is to minimize the amount of proprietary and/or +binary code. Their laptops ship with a blob-free OS and coreboot firmware +with a neutralized Intel Management Engine (ME) and SeaBIOS as the payload. + ## After-market firmware ### Libreboot -- To view, visit https://review.coreboot.org/c/coreboot/+/54272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1f27d68124de745ff0eaad669ee86ce0b57ec09 Gerrit-Change-Number: 54272 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Documentation/distributions: Separate all vendors by exactly one blan...
by Patrick Georgi (Code Review) 14 May '21

14 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54271 ) Change subject: Documentation/distributions: Separate all vendors by exactly one blank line ...................................................................... Documentation/distributions: Separate all vendors by exactly one blank line Change-Id: Ib1718dfa174e2a4e9c2c4b5564e196e8483a8f3c Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54271 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M Documentation/distributions.md 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/Documentation/distributions.md b/Documentation/distributions.md index 75ac698..8401836 100644 --- a/Documentation/distributions.md +++ b/Documentation/distributions.md @@ -29,7 +29,6 @@ [Libretrend](https://libretrend.com) sells the Librebox, a NUC-like PC which ships with coreboot firmware. - ### PC Engines APUs [PC Engines](https://pcengines.ch) designs and sells embedded PC hardware that -- To view, visit https://review.coreboot.org/c/coreboot/+/54271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1718dfa174e2a4e9c2c4b5564e196e8483a8f3c Gerrit-Change-Number: 54271 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Documentation/distributions: Separate parenthesis by dashes
by Patrick Georgi (Code Review) 14 May '21

14 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54270 ) Change subject: Documentation/distributions: Separate parenthesis by dashes ...................................................................... Documentation/distributions: Separate parenthesis by dashes Change-Id: I5d6095c6d8423e3a67f027f23d4c00dcb34a50cb Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54270 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M Documentation/distributions.md 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/Documentation/distributions.md b/Documentation/distributions.md index fbfeb7c..75ac698 100644 --- a/Documentation/distributions.md +++ b/Documentation/distributions.md @@ -20,8 +20,8 @@ All ChromeOS devices ([Chromebooks](https://chromebookdb.com/), Chromeboxes, Chromebit, etc) released from 2012 onward use coreboot for their main system firmware. Additionally, starting with the 2013 Chromebook Pixel, the firmware -running on the Embedded Controller (EC - a small microcontroller which provides -functions like battery management, keyboard support, and sensor interfacing) +running on the Embedded Controller (EC) – a small microcontroller which provides +functions like battery management, keyboard support, and sensor interfacing – is open source as well. ### Libretrend -- To view, visit https://review.coreboot.org/c/coreboot/+/54270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d6095c6d8423e3a67f027f23d4c00dcb34a50cb Gerrit-Change-Number: 54270 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/amd/agesa/family14: Use generic allocation functions for northbridge
by Michał Żygowski (Code Review) 14 May '21

14 May '21

Attention is currently required from: Nico Huber, Kyösti Mälkki, Piotr Król. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52934 ) Change subject: nb/amd/agesa/family14: Use generic allocation functions for northbridge ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52934/comment/0796b7e7_8418f087 PS2, Line 9: Remove obsolete resource assigning functions. > Elaborated a bit in the commit message attempting to explain it. Done File src/northbridge/amd/agesa/family14/northbridge.c: https://review.coreboot.org/c/coreboot/+/52934/comment/5fd69c73_597bdf32 PS2, Line 448: set_resource(dev, res, nodeid); > Right, the respective code in nb_read_resources does not do anything meaningful too. Removed. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74a0ed1fcbbc9e066c42c4d51d30ab1d7138134a Gerrit-Change-Number: 52934 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Fri, 14 May 2021 09:39:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/txt: Always build logginc.c
by Angel Pons (Code Review) 14 May '21

14 May '21

Attention is currently required from: Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54295 ) Change subject: security/intel/txt: Always build logginc.c ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54295/comment/2c2f84e2_12c4de2c PS1, Line 7: c typo: g -- To view, visit https://review.coreboot.org/c/coreboot/+/54295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I654adf16b47513e3279335c8a8ad48b9371d438e Gerrit-Change-Number: 54295 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 14 May 2021 09:18:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cherry: Add DRAM calibration support
by Patrick Georgi (Code Review) 14 May '21

14 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54269 ) Change subject: mb/google/cherry: Add DRAM calibration support ...................................................................... mb/google/cherry: Add DRAM calibration support Initialize and calibrate DRAM in romstage. Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.com> Change-Id: Ib7677baef126ee60bf35da3a4eaf720eaa118a27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54269 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/cherry/Makefile.inc A src/mainboard/google/cherry/boardid.c M src/mainboard/google/cherry/romstage.c A src/mainboard/google/cherry/sdram_configs.c 4 files changed, 28 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved diff --git a/src/mainboard/google/cherry/Makefile.inc b/src/mainboard/google/cherry/Makefile.inc index 4720dc5..a0862d3 100644 --- a/src/mainboard/google/cherry/Makefile.inc +++ b/src/mainboard/google/cherry/Makefile.inc @@ -7,10 +7,13 @@ verstage-y += reset.c romstage-y += memlayout.ld +romstage-y += boardid.c romstage-y += chromeos.c romstage-y += romstage.c +romstage-y += sdram_configs.c ramstage-y += memlayout.ld +ramstage-y += boardid.c ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += reset.c diff --git a/src/mainboard/google/cherry/boardid.c b/src/mainboard/google/cherry/boardid.c new file mode 100644 index 0000000..34d7692 --- /dev/null +++ b/src/mainboard/google/cherry/boardid.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boardid.h> + +uint32_t ram_code(void) +{ + return 0; +} diff --git a/src/mainboard/google/cherry/romstage.c b/src/mainboard/google/cherry/romstage.c index ec7e4f9..5505d8a 100644 --- a/src/mainboard/google/cherry/romstage.c +++ b/src/mainboard/google/cherry/romstage.c @@ -2,6 +2,7 @@ #include <arch/stages.h> #include <soc/clkbuf.h> +#include <soc/emi.h> #include <soc/mt6315.h> #include <soc/mt6359p.h> #include <soc/pmif.h> @@ -15,5 +16,6 @@ mt6315_init(); clk_buf_init(); rtc_boot(); + mtk_dram_init(); scp_rsi_enable(); } diff --git a/src/mainboard/google/cherry/sdram_configs.c b/src/mainboard/google/cherry/sdram_configs.c new file mode 100644 index 0000000..de6bdd1 --- /dev/null +++ b/src/mainboard/google/cherry/sdram_configs.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_param.h> + +const struct sdram_info *get_sdram_config(void) +{ + /* + * The MT8195 platform supports "dram adaptive" feature to + * automatically detect dram information, including channel, rank, die size..., + * and can automatically configure EMI settings. + * So we will be passing a placeholder param blob. + */ + static struct sdram_info params; + return &params; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/54269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7677baef126ee60bf35da3a4eaf720eaa118a27 Gerrit-Change-Number: 54269 Gerrit-PatchSet: 10 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/boten: Modify DPTF parameters
by Patrick Georgi (Code Review) 14 May '21

14 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52755 ) Change subject: mb/google/dedede/var/boten: Modify DPTF parameters ...................................................................... mb/google/dedede/var/boten: Modify DPTF parameters DPTF parameters from thermal team. 1. Modify TSR1 sensor as charge sensor. 2. Modify P-state parameter BUG=b:180641150 BRANCH=dedede TEST=build and verified by thermal team. Change-Id: I43002db61de650d29cd85944a4eaea1b2f99aec4 Signed-off-by: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52755 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/variants/boten/overridetree.cb 1 file changed, 36 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index cfb440e..8c68f7e 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -87,15 +87,48 @@ register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000), - [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000),}" + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 15000) + }" + ## Critical Policy register "policies.critical" = "{ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN), - [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN),}" + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 90, SHUTDOWN) + }" + + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 20000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Charger"" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 2000 }, + [2] = { 16, 1500 }, + [3] = { 8, 1000 } + }" + device generic 0 on end end - end + end # SA Thermal device device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" -- To view, visit https://review.coreboot.org/c/coreboot/+/52755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43002db61de650d29cd85944a4eaea1b2f99aec4 Gerrit-Change-Number: 52755 Gerrit-PatchSet: 4 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: tests: code coverage improvements
by Patrick Georgi (Code Review) 14 May '21

14 May '21

Attention is currently required from: Paul Fagerburg, Julius Werner. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54072 ) Change subject: tests: code coverage improvements ...................................................................... Patch Set 3: (1 comment) File tests/Makefile.inc: https://review.coreboot.org/c/coreboot/+/54072/comment/1aa262bc_9324131e PS3, Line 195: coverage-unit-tests: unit-tests coverage-report-tests make could decide to build the dependencies in parallel. From what I see, coverage-report-tests needs unit-tests to be finished, right? In that case, maybe just add "unit-tests" as dependency to coverage-report-tests? -- To view, visit https://review.coreboot.org/c/coreboot/+/54072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2bd2bfdedfab291aabeaa968c10b17e9b61c9c0a Gerrit-Change-Number: 54072 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 14 May 2021 09:08:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cherry: Add DRAM calibration support
by Hung-Te Lin (Code Review) 14 May '21

14 May '21

Attention is currently required from: Rex-BC Chen, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54269 ) Change subject: mb/google/cherry: Add DRAM calibration support ...................................................................... Patch Set 9: (1 comment) File src/mainboard/google/cherry/sdram_configs.c: https://review.coreboot.org/c/coreboot/+/54269/comment/68991a48_5711a54d PS9, Line 9: die > it' not a typo. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/54269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7677baef126ee60bf35da3a4eaf720eaa118a27 Gerrit-Change-Number: 54269 Gerrit-PatchSet: 9 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 14 May 2021 09:04:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Update CPU and IGD Device IDs
by Patrick Georgi (Code Review) 14 May '21

14 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54211 ) Change subject: soc/intel/alderlake: Update CPU and IGD Device IDs ...................................................................... soc/intel/alderlake: Update CPU and IGD Device IDs Updated CPU ID and IGD ID for Alder Lake as per EDS. TEST=Code compilation works and coreboot is able to boot and identify new device Ids. Change-Id: I2759a41a0db1eba5d159edfc89460992914fcc3c Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54211 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/include/device/pci_ids.h M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/mp_init.h 5 files changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index a3ee558..1a9aa35 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3812,6 +3812,7 @@ #define PCI_DEVICE_ID_INTEL_ADL_GT1_8 0x4618 #define PCI_DEVICE_ID_INTEL_ADL_GT1_9 0x4619 #define PCI_DEVICE_ID_INTEL_ADL_P_GT2 0x46a0 +#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_1 0x46b0 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680 #define PCI_DEVICE_ID_INTEL_ADL_M_GT1 0x46c0 diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 2666426..78f02ec 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -23,6 +23,7 @@ const char *name; } cpu_table[] = { { CPUID_ALDERLAKE_P_A0, "Alderlake-P A0" }, + { CPUID_ALDERLAKE_P_B0, "Alderlake-P B0" }, { CPUID_ALDERLAKE_M_A0, "Alderlake-M A0" }, }; @@ -98,6 +99,7 @@ { PCI_DEVICE_ID_INTEL_ADL_GT1_8, "Alderlake GT1" }, { PCI_DEVICE_ID_INTEL_ADL_GT1_9, "Alderlake GT1" }, { PCI_DEVICE_ID_INTEL_ADL_P_GT2, "Alderlake P GT2" }, + { PCI_DEVICE_ID_INTEL_ADL_P_GT2_1, "Alderlake P GT2" }, { PCI_DEVICE_ID_INTEL_ADL_M_GT1, "Alderlake M GT1" }, }; diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 9619298..7e8c199 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -68,6 +68,7 @@ { X86_VENDOR_INTEL, CPUID_JASPERLAKE_A0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_S_A0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_P_A0 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_P_B0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_M_A0 }, { 0, 0 }, }; diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 0920a05..fe89f86 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -295,6 +295,7 @@ PCI_DEVICE_ID_INTEL_ADL_GT1_8, PCI_DEVICE_ID_INTEL_ADL_GT1_9, PCI_DEVICE_ID_INTEL_ADL_P_GT2, + PCI_DEVICE_ID_INTEL_ADL_P_GT2_1, PCI_DEVICE_ID_INTEL_ADL_S_GT1, PCI_DEVICE_ID_INTEL_ADL_M_GT1, 0, diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index 9038dd5..3d8290f 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -46,6 +46,7 @@ #define CPUID_ELKHARTLAKE_B0 0x90661 #define CPUID_ALDERLAKE_S_A0 0x90670 #define CPUID_ALDERLAKE_P_A0 0x906a0 +#define CPUID_ALDERLAKE_P_B0 0x906a2 #define CPUID_ALDERLAKE_M_A0 0x906a1 /* * MP Init callback function to Find CPU Topology. This function is common -- To view, visit https://review.coreboot.org/c/coreboot/+/54211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2759a41a0db1eba5d159edfc89460992914fcc3c Gerrit-Change-Number: 54211 Gerrit-PatchSet: 3 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: merged

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coreboot-gerrit May 2021