coreboot-gerrit May 2021

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Change in coreboot[master]: vboot/secdata_mock: Make v0 kernel secdata context
by Aseda Aboagye (Code Review) 14 May '21

14 May '21

Aseda Aboagye has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54304 ) Change subject: vboot/secdata_mock: Make v0 kernel secdata context ...................................................................... vboot/secdata_mock: Make v0 kernel secdata context Vboot implicitly assumes that EFS2 (Early Firmware Selection v2) is supported on systems which do _NOT_ have a v0 secdata kernel context. For MOCK_SECDATA, we cannot retain data across a reboot (which is what EFS2 needs in order to use Hmir, the mirrored EC hash). Therefore, in order for vboot to skip the Hmir sync while using MOCK_SECDATA, we need to have MOCK_SECDATA create a v0 secdata kernel context. Otherwise, this would result in a reboot loop where vboot attempts to set Hmir and retrieve it after a reboot, but the value is not expected. This was encountered on using a firmware built with MOCK_SECDATA but had EC software sync enabled. BUG=b:187843114 BRANCH=None TEST=`USE=mocktpm cros build-ap -b keeby`; Flash keeby device, verify that DUT does not continuously reboot with EC software sync enabled. Signed-off-by: Aseda Aboagye <aaboagye(a)google.com> Change-Id: Id8e81afcddadf27d9eec274f7f85ff1520315aaa --- M src/security/vboot/secdata_mock.c 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/54304/1 diff --git a/src/security/vboot/secdata_mock.c b/src/security/vboot/secdata_mock.c index 78cb3e6..f640f92 100644 --- a/src/security/vboot/secdata_mock.c +++ b/src/security/vboot/secdata_mock.c @@ -28,7 +28,16 @@ vb2_error_t antirollback_read_space_kernel(struct vb2_context *ctx) { - vb2api_secdata_kernel_create(ctx); + /* Vboot implicitly assumes that EFS2 (Early Firmware Selection v2) is + * supported on systems which do _NOT_ have a v0 secdata kernel context. + * For MOCK_SECDATA, we cannot retain data across a reboot (which is what + * EFS2 needs in order to use Hmir, the mirrored EC hash). Therefore, in + * order for vboot to skip the Hmir sync while using MOCK_SECDATA, we need + * to have MOCK_SECDATA create a v0 secdata kernel context. Otherwise, + * this would result in a reboot loop where vboot attempts to set Hmir and + * retrieve it after a reboot, but the value is not expected. + */ + vb2api_secdata_kernel_create_v0(ctx); return VB2_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/54304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8e81afcddadf27d9eec274f7f85ff1520315aaa Gerrit-Change-Number: 54304 Gerrit-PatchSet: 1 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: Enable PCIe L1 Substates
by Matt Papageorge (Code Review) 14 May '21

14 May '21

Matt Papageorge has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54303 ) Change subject: mb/google/guybrush: Enable PCIe L1 Substates ...................................................................... mb/google/guybrush: Enable PCIe L1 Substates Currently cannot complete POST with this change. Investigating now BUG=b:188123142 TEST=Currently non-functional due to hang in POST Change-Id: I40d19be78bfcb9a30fb59f48530a4413dadbefbc Signed-off-by: Matt Papageorge <matthewpapa07(a)gmail.com> --- M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/guybrush/port_descriptors.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/54303/1 diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index 5a7cd8a..21b1f3c 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -36,6 +36,7 @@ select PCIEXP_ASPM select PCIEXP_CLK_PM select PCIEXP_COMMON_CLOCK + select PCIEXP_L1_SUB_STATE config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index 540d3d1..6de1879 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -14,6 +14,8 @@ .device_number = 2, .function_number = 1, .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ0, .gpio_group_id = GPIO_29, @@ -27,6 +29,8 @@ .device_number = 2, .function_number = 2, .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ1, .gpio_group_id = GPIO_70, @@ -40,6 +44,8 @@ .device_number = 2, .function_number = 3, .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ2, .gpio_group_id = GPIO_18, @@ -53,6 +59,8 @@ .device_number = 2, .function_number = 4, .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ3, .gpio_group_id = GPIO_40, -- To view, visit https://review.coreboot.org/c/coreboot/+/54303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40d19be78bfcb9a30fb59f48530a4413dadbefbc Gerrit-Change-Number: 54303 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: Enable PCIe Power Management and Clock Features
by Matt Papageorge (Code Review) 14 May '21

14 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Furquan Shaikh, Marshall Dawson, Eric Peers, Felix Held. Matt Papageorge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54282 ) Change subject: mb/google/guybrush: Enable PCIe Power Management and Clock Features ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/guybrush/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/54282/comment/084ab5c6_cea798e4 PS6, Line 16: .link_aspm = ASPM_L1, Descriptor switches are needed so AGESA can adjust some needed straps -- To view, visit https://review.coreboot.org/c/coreboot/+/54282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefc4b5b489cb8caf59f21dd4333d7af66ba47c32 Gerrit-Change-Number: 54282 Gerrit-PatchSet: 6 Gerrit-Owner: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 14 May 2021 19:05:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Enable PCIe Power Management and Clock Features
by Matt Papageorge (Code Review) 14 May '21

14 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Furquan Shaikh, Marshall Dawson, Eric Peers, Felix Held. Matt Papageorge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54282 ) Change subject: mb/google/guybrush: Enable PCIe Power Management and Clock Features ...................................................................... Patch Set 6: (1 comment) This change is ready for review. Patchset: PS6: I am currently omitting L1ss, which currently cause a hang when enabled. Separate bug for investigating that in the bug referenced in b/188123142 -- To view, visit https://review.coreboot.org/c/coreboot/+/54282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefc4b5b489cb8caf59f21dd4333d7af66ba47c32 Gerrit-Change-Number: 54282 Gerrit-PatchSet: 6 Gerrit-Owner: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 14 May 2021 19:05:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: intel/commonblocks/tcss: Add API for Type-C port orientation
by Tim Wawrzynczak (Code Review) 14 May '21

14 May '21

Attention is currently required from: Caveh Jalali, Nick Vaccaro, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54294 ) Change subject: intel/commonblocks/tcss: Add API for Type-C port orientation ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/include/intelblocks/tcss.h: https://review.coreboot.org/c/coreboot/+/54294/comment/fda8ed3f_db098299 PS1, Line 102: ori, ena) suggestion: an enum or #define for these values would be very helpful -- To view, visit https://review.coreboot.org/c/coreboot/+/54294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5510d1c9e97bd104c89cde7dd38ad791f859d7c Gerrit-Change-Number: 54294 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 14 May 2021 17:14:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00
by Tim Wawrzynczak (Code Review) 14 May '21

14 May '21

Attention is currently required from: Bora Guvendik, V Sowmya, Furquan Shaikh, Maulik V Vaghela, Rizwan Qureshi, Subrata Banik, Meera Ravindranath, Bernardo Perez Priego, Tim Wawrzynczak, Ronak Kanabar, Srinidhi N Kaushik, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54083 ) Change subject: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00 ...................................................................... Patch Set 4: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54083/comment/bf24bd91_6f3b1174 PS4, Line 26: Cq-Depend: TBD Please update to: ``` Cq-Depend: chrome-internal:3831865, chrome-internal:3831864, chrome-internal:3831913 Cq-Depend: chromium:TODO ``` and then when these 2 changes get merged here, I'll take care of the downstreaming and update the Cq-Depend in our tree. -- To view, visit https://review.coreboot.org/c/coreboot/+/54083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8d7980146f1bfc96472ef504cf9f16eee63a13e Gerrit-Change-Number: 54083 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 14 May 2021 17:03:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Update meminit code due to upd changes FSP 2147 ...
by Tim Wawrzynczak (Code Review) 14 May '21

14 May '21

Attention is currently required from: Bora Guvendik, Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Ronak Kanabar, Tim Wawrzynczak, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54036 ) Change subject: soc/intel/alderlake: Update meminit code due to upd changes FSP 2147 onwards ...................................................................... Patch Set 4: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54036/comment/02217fef_72ad8e3b PS4, Line 19: > Will also need the same Cq-Depend as its parent Please update to: ``` Cq-Depend: chrome-internal:3831865, chrome-internal:3831864, chrome-internal:3831913 Cq-Depend: chromium:TODO ``` and then when these 2 changes get merged here, I'll take care of the downstreaming and update the Cq-Depend in our tree. -- To view, visit https://review.coreboot.org/c/coreboot/+/54036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5af11ae99db3bbe3373a9bd4ce36453b58d62fec Gerrit-Change-Number: 54036 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 14 May 2021 17:03:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: Provide EC access for Retimer firmware upgrade
by John Zhao (Code Review) 14 May '21

14 May '21

Attention is currently required from: Duncan Laurie. Hello build bot (Jenkins), Duncan Laurie, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52713 to look at the new patch set (#6). Change subject: ec/google/chromeec: Provide EC access for Retimer firmware upgrade ...................................................................... ec/google/chromeec: Provide EC access for Retimer firmware upgrade coreboot needs to access EC RFWU entry in order to suspend and resume PD and modes setting. This change adds ec_retimer_fw_update implementation for Retimer firmware upgrade. BUG=b:186521258 TEST=Build image successfully. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: Ib937d8bd72fc39487854773573b435bf2add672a --- M src/ec/google/chromeec/ec_acpi.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/52713/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/52713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib937d8bd72fc39487854773573b435bf2add672a Gerrit-Change-Number: 52713 Gerrit-PatchSet: 6 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Duncan Laurie Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Duncan Laurie Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/shadowmountain: Update mainboard properties
by John Zhao (Code Review) 14 May '21

14 May '21

Attention is currently required from: Tim Wawrzynczak. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54292 to look at the new patch set (#3). Change subject: mb/intel/shadowmountain: Update mainboard properties ...................................................................... mb/intel/shadowmountain: Update mainboard properties This changes updates mainboard properties by adding DFP number and power_gpio for each DFP. BUG=b:186521258 TEST=None Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I29480bf77f7df9890bef64a5f9f02074a34dc131 --- M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/54292/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/54292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29480bf77f7df9890bef64a5f9f02074a34dc131 Gerrit-Change-Number: 54292 Gerrit-PatchSet: 3 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/shadowmountain: Remove power_gpio from baseboard
by John Zhao (Code Review) 14 May '21

14 May '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54290 to look at the new patch set (#2). Change subject: mb/intel/shadowmountain: Remove power_gpio from baseboard ...................................................................... mb/intel/shadowmountain: Remove power_gpio from baseboard Along with upstream kernel for Retimer firmware update, coreboot defines power control for each DFP respectively under host router. This change removes the power_gpio from the baseboard. Individual DFPx power_gpio will be added once the dependent definition is complete. BUG=b:186521258 TEST=Build image successfully. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I819d2900afabbfdb2713fa8eee35d3c90cb904fd --- M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/54290/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I819d2900afabbfdb2713fa8eee35d3c90cb904fd Gerrit-Change-Number: 54290 Gerrit-PatchSet: 2 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021