coreboot-gerrit May 2021

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Change in coreboot[master]: payload/tianocore: Drop IA32 option when UEFIPAYLOAD select
by Lance Zhao (Code Review) 13 May '21

13 May '21

Attention is currently required from: Bora Guvendik, Lijian Zhao, Martin Roth, Matt DeVillier, John Zhao, Stefan Reinauer. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54189 ) Change subject: payload/tianocore: Drop IA32 option when UEFIPAYLOAD select ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/54189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadd9a3c455fad4eede8a0a017415acd2c57fba04 Gerrit-Change-Number: 54189 Gerrit-PatchSet: 2 Gerrit-Owner: Lance Zhao Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Fri, 14 May 2021 01:30:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Enable GFX HDA FSP UPD
by Marshall Dawson (Code Review) 13 May '21

13 May '21

Marshall Dawson has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54100 ) Change subject: soc/amd/cezanne: Enable GFX HDA FSP UPD ...................................................................... soc/amd/cezanne: Enable GFX HDA FSP UPD By default, FSP disables the GFX HDA. Enable it to support HDMI Audio functionality. BUG=b:186479763 TEST=Build and boot to OS in guybrush. Ensure that the GFX HDA is enumerated in lspci output. 04:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] Device 1637 Change-Id: I42cb26c44bbca3d937c5d52736c42468139f7b07 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54100 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/fsp_m_params.c 1 file changed, 26 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 4aff7e0..5dd3056 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -8,10 +8,34 @@ #include <device/device.h> #include <fsp/api.h> #include <soc/platform_descriptors.h> +#include <soc/pci_devs.h> #include <string.h> #include <types.h> #include "chip.h" +static const struct device_path gfx_hda_path[] = { + { + .type = DEVICE_PATH_PCI, + .pci.devfn = PCIE_ABC_A_DEVFN + }, + { + .type = DEVICE_PATH_PCI, + .pci.devfn = GFX_HDA_DEVFN + }, +}; + +static bool devtree_gfx_hda_dev_enabled(void) +{ + const struct device *gfx_hda_dev; + + gfx_hda_dev = find_dev_nested_path(pci_root_bus(), gfx_hda_path, + ARRAY_SIZE(gfx_hda_path)); + if (!gfx_hda_dev) + return false; + + return gfx_hda_dev->enabled; +} + static void fill_dxio_descriptors(FSP_M_CONFIG *mcfg, const fsp_dxio_descriptor *descs, size_t num) { @@ -136,6 +160,8 @@ mcfg->telemetry_vddcrsocOffset = config->telemetry_vddcrsocoffset; + mcfg->enable_nb_azalia = devtree_gfx_hda_dev_enabled(); + fsp_fill_pcie_ddi_descriptors(mcfg); fsp_assign_ioapic_upds(mcfg); } -- To view, visit https://review.coreboot.org/c/coreboot/+/54100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42cb26c44bbca3d937c5d52736c42468139f7b07 Gerrit-Change-Number: 54100 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: Enable GFX HDA FSP UPD
by Marshall Dawson (Code Review) 13 May '21

13 May '21

Attention is currently required from: Jason Glenesk, Martin Roth, Karthik Ramasubramanian, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54100 ) Change subject: soc/amd/cezanne: Enable GFX HDA FSP UPD ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42cb26c44bbca3d937c5d52736c42468139f7b07 Gerrit-Change-Number: 54100 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 14 May 2021 01:02:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: amd/cezanne: adding support for the changed AMD FSP API for USB PHY
by Marshall Dawson (Code Review) 13 May '21

13 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt Papageorge, Julian Schroeder, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54065 ) Change subject: amd/cezanne: adding support for the changed AMD FSP API for USB PHY ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54065/comment/3a63ac7c_01d8b2cb PS6, Line 7: amd/cezanne: adding Oh, one more. Use soc soc/amd/cezanne And soc/amd/cezanne: add support... -- To view, visit https://review.coreboot.org/c/coreboot/+/54065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b Gerrit-Change-Number: 54065 Gerrit-PatchSet: 6 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshall.dawson(a)amd.corp-partner.google.com> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 14 May 2021 00:55:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amd/cezanne: adding support for the changed AMD FSP API for USB PHY
by Marshall Dawson (Code Review) 13 May '21

13 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Matt Papageorge, Julian Schroeder, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54065 ) Change subject: amd/cezanne: adding support for the changed AMD FSP API for USB PHY ...................................................................... Patch Set 6: (4 comments) File src/soc/amd/cezanne/fsp_m_params.c: https://review.coreboot.org/c/coreboot/+/54065/comment/c820ba7d_eead333a PS6, Line 132: coreboot uses tabs for indenting. Here and line 135. File src/vendorcode/amd/fsp/cezanne/FspUsb.h: https://review.coreboot.org/c/coreboot/+/54065/comment/b4be2cfb_db7753b3 PS6, Line 11: uint8_t compdstune; ///< COMPDSTUNE Use tabs to indent all these https://review.coreboot.org/c/coreboot/+/54065/comment/8e1d9ec3_da23004e PS6, Line 12: uint8_t sqrxtune; ///< SQRXTUNE : uint8_t txfslstune; ///< TXFSLSTUNE : uint8_t txpreempamptune; ///< TXPREEMPAMPTUNE : uint8_t txpreemppulsetune; ///< TXPREEMPPULSETUNE : uint8_t txrisetune; ///< TXRISETUNE : uint8_t txvreftune; ///< TXVREFTUNE : uint8_t txhsxvtune; ///< TXHSXVTUNE : uint8_t txrestune; ///< TXRESTUNE Remove Windows line endings from these. Run "make gitconfig" to catch these ahead of time with a commit hook. https://review.coreboot.org/c/coreboot/+/54065/comment/051e3e33_aa9d7ac0 PS6, Line 23: uint8_t tx_term_ctrl; ///< tx_term_ctrl : uint8_t rx_term_ctrl; ///< rx_term_ctrl : uint8_t tx_vboost_lvl_en; ///< TX_VBOOST_LVL_EN : uint8_t tx_vboost_lvl; ///< TX_VBOOST_LVL Remove Windows line endings from these. -- To view, visit https://review.coreboot.org/c/coreboot/+/54065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b Gerrit-Change-Number: 54065 Gerrit-PatchSet: 6 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshall.dawson(a)amd.corp-partner.google.com> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 14 May 2021 00:51:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cbfs: Increase mcache size defaults
by Julius Werner (Code Review) 13 May '21

13 May '21

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54146 ) Change subject: cbfs: Increase mcache size defaults ...................................................................... cbfs: Increase mcache size defaults The CBFS mcache size default was eyeballed to what should be "hopefully enough" for most users, but some recent Chrome OS devices have already hit the limit. Since most current (and probably all future) x86 chipsets likely have the CAR space to spare, let's just double the size default for all supporting chipsets right now so that we hopefully won't run into these issues again any time soon. The CBFS_MCACHE_RW_PERCENTAGE default for CHROMEOS was set to 25 under the assumption that Chrome OS images have historically always had a lot more files in their RO CBFS than the RW (because l10n assets were only in RO). Unfortunately, this has recently changed with the introduction of updateable assets. While hopefully not that many boards will need these, the whole idea is that you won't know whether you need them yet at the time the RO image is frozen, and mcache layout parameters cannot be changed in an RW update. So better to use the normal 50/50 split on Chrome OS devices going forward so we are prepared for the eventuality of needing RW assets again. The RW percentage should really also be menuconfig-controllable, because this is something the user may want to change on the fly depending on their payload requirements. Move the option to the vboot Kconfigs because it also kinda belongs there anyway and this makes it fit in better in menuconfig. (I haven't made the mcache size menuconfig-controllable because if anyone needs to increase this, they can just override the default in the chipset Kconfig for everyone using that chipset, under the assumption that all boards of that chipset have the same amount of available CAR space and there's no reason not to use up the available space. This seems more in line with how this would work on non-x86 platforms that define this directly in their memlayout.ld.) Also add explicit warnings to both options that they mustn't be changed in an RW update to an older RO image. BUG=b:187561710 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I046ae18c9db9a5d682384edde303c07e0be9d790 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54146 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/arch/x86/Kconfig M src/lib/Kconfig M src/mainboard/google/volteer/Kconfig M src/security/vboot/Kconfig 4 files changed, 14 insertions(+), 21 deletions(-) Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index bb03db2..a488b55 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -147,9 +147,10 @@ config CBFS_MCACHE_SIZE hex depends on !NO_CBFS_MCACHE - default 0x2000 + default 0x4000 help - Increase this value if you see CBFS mcache overflow warnings. + Increase this value if you see CBFS mcache overflow warnings. Do NOT + change this value for vboot RW updates! config PC80_SYSTEM bool diff --git a/src/lib/Kconfig b/src/lib/Kconfig index e1d56fe..239f613 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -98,14 +98,3 @@ the associated CAR/SRAM size. In that case every single CBFS file lookup must re-read the same CBFS directory entries from flash to find the respective file. - -config CBFS_MCACHE_RW_PERCENTAGE - int - depends on VBOOT && !NO_CBFS_MCACHE - default 25 if CHROMEOS # Chrome OS stores many L10n files in RO only - default 50 - help - The amount of the CBFS_MCACHE area that's used for the RW CBFS, in - percent from 0 to 100. The remaining area will be used for the RO - CBFS. Default is an even 50/50 split. When VBOOT is disabled, this - will automatically be 0 (meaning the whole MCACHE is used for RO). diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 2fec5be..3112672 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -161,12 +161,4 @@ bool default n -config CBFS_MCACHE_RW_PERCENTAGE - int - default 50 - -config CBFS_MCACHE_SIZE - hex - default 0x4000 - endif # BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index a39680d..515efc7 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -235,6 +235,17 @@ Add a space-delimited list of filenames that should only be in the RW-B section. +config CBFS_MCACHE_RW_PERCENTAGE + int "Percentage of CBFS metadata cache used for RW CBFS" + depends on !NO_CBFS_MCACHE + default 50 + help + The amount of the CBFS_MCACHE area that's used for the RW CBFS, in + percent from 0 to 100. The remaining area will be used for the RO + CBFS. Default is an even 50/50 split. When VBOOT is disabled, this + will automatically be 0 (meaning the whole MCACHE is used for RO). + Do NOT change this value for vboot RW updates! + config VBOOT_ENABLE_CBFS_FALLBACK bool default n -- To view, visit https://review.coreboot.org/c/coreboot/+/54146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I046ae18c9db9a5d682384edde303c07e0be9d790 Gerrit-Change-Number: 54146 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cbfs: Increase mcache size defaults
by Julius Werner (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54146 ) Change subject: cbfs: Increase mcache size defaults ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Jenkins is still happy, I'm a little surprised 😊 I mean, the CAR sizes probably change in larger chunks between CPU generations. The jump from the CPUs that already couldn't fit the smaller cache to the newer ones was probably more than 8K. -- To view, visit https://review.coreboot.org/c/coreboot/+/54146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I046ae18c9db9a5d682384edde303c07e0be9d790 Gerrit-Change-Number: 54146 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Fri, 14 May 2021 00:35:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: vboot: Add VB2_CONTEXT_EC_IN_RO
by Julius Werner (Code Review) 13 May '21

13 May '21

Attention is currently required from: Daisuke Nojiri, Aaron Durbin. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54099 ) Change subject: vboot: Add VB2_CONTEXT_EC_IN_RO ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: LGTM but remember you need to add an uprev patch after the other CL lands first. -- To view, visit https://review.coreboot.org/c/coreboot/+/54099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fa09dd7ae5baa1efb4e1ed4f0fe9a6803167c93 Gerrit-Change-Number: 54099 Gerrit-PatchSet: 2 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Thu, 13 May 2021 23:24:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/majolica: Disable IO ports 0x60/0x64
by Marshall Dawson (Code Review) 13 May '21

13 May '21

Attention is currently required from: Raul Rangel, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54071 ) Change subject: mb/amd/majolica: Disable IO ports 0x60/0x64 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56a7eb4200e4615e1b4d9f14594d64f93e031a54 Gerrit-Change-Number: 54071 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 13 May 2021 23:02:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: Implement support for DRIVERS_ACPI_THERMAL_ZONE
by Tim Wawrzynczak (Code Review) 13 May '21

13 May '21

Attention is currently required from: Raul Rangel, Furquan Shaikh. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54133 ) Change subject: ec/google/chromeec: Implement support for DRIVERS_ACPI_THERMAL_ZONE ...................................................................... Patch Set 2: (1 comment) File src/ec/google/chromeec/ec_acpi.c: https://review.coreboot.org/c/coreboot/+/54133/comment/4c7398fa_c5e91ccb PS2, Line 267: : void google_chromeec_acpigen_write_TMP(const struct device *dev) : { : struct drivers_acpi_thermal_zone_config *config = config_of(dev); : static char buf[DEVICE_PATH_MAX] = {}; : const char *ec_path = acpi_device_path(config->temperature_controller); : : /* : * The cros EC device returns EC0.CREC as the acpi_name. The method : * we want is on the EC0 device. : */ : snprintf(buf, sizeof(buf), "%.*s.TSRD", strlen(ec_path) - 5, : acpi_device_path(config->temperature_controller)); : : acpigen_write_method_serialized("_TMP", 0); : : acpigen_emit_byte(RETURN_OP); : acpigen_emit_namestring(buf); : acpigen_write_integer(config->sensor_id); : : acpigen_write_method_end(); : } consider a refactor? https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… also regarding EC0 vs. EC0.CREC, I have considered at least for now, until we can straighten out the ASL vs. the acpigen'd AML... we could have a function in `ec_acpi.c` that does this: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… like: ``` const struct device *google_chromeec_get_EC0(void) { static struct device *ec0; if (!ec0) { create_it; } return ec0; } ``` that was my thought, since I have a few other places I wanted to acpigen some more EC-related things... WDYT? -- To view, visit https://review.coreboot.org/c/coreboot/+/54133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I418b6691a7d00a4c2d89c9c1fe8f9416602be0f1 Gerrit-Change-Number: 54133 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Thu, 13 May 2021 22:53:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2021