coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: cbfs: Increase mcache size defaults
by Tim Wawrzynczak (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh, Julius Werner, Aaron Durbin. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54146 ) Change subject: cbfs: Increase mcache size defaults ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: Jenkins is still happy, I'm a little surprised 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/54146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I046ae18c9db9a5d682384edde303c07e0be9d790 Gerrit-Change-Number: 54146 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Thu, 13 May 2021 17:12:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: enable DPTF functionality for brya
by Sumeet R Pawnikar (Code Review) 13 May '21

13 May '21

Attention is currently required from: V Sowmya, John Su, Furquan Shaikh. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52859 ) Change subject: mb/google/brya: enable DPTF functionality for brya ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52859/comment/eb84ee41_62a8d3de PS5, Line 12: BUG=None > Would you mind filing a bug for DPTF enablement? Would be good to see some before-and-after data if […] Done. -- To view, visit https://review.coreboot.org/c/coreboot/+/52859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33266c85aa30869466034ccbab04a3c7820ae2b0 Gerrit-Change-Number: 52859 Gerrit-PatchSet: 6 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Thu, 13 May 2021 17:12:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/gm45: Guard even more macro parameters
by Angel Pons (Code Review) 13 May '21

13 May '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54280 ) Change subject: nb/intel/gm45: Guard even more macro parameters ...................................................................... nb/intel/gm45: Guard even more macro parameters Add brackets around the parameters to avoid operation order problems. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: Icb9d6e8bdafdac7ad820b1629d04e7bdfbcd4b3f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/gm45/raminit_read_write_training.c M src/northbridge/intel/gm45/raminit_receive_enable_calibration.c 2 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/54280/1 diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c index 544c523..be614ae 100644 --- a/src/northbridge/intel/gm45/raminit_read_write_training.c +++ b/src/northbridge/intel/gm45/raminit_read_write_training.c @@ -12,13 +12,13 @@ } address_bunch_t; /* Read Training. */ -#define CxRDTy_MCHBAR(ch, bl) (0x14b0 + (ch * 0x0100) + ((7 - bl) * 4)) +#define CxRDTy_MCHBAR(ch, bl) (0x14b0 + ((ch) * 0x0100) + ((7 - (bl)) * 4)) #define CxRDTy_T_SHIFT 20 #define CxRDTy_T_MASK (0xf << CxRDTy_T_SHIFT) -#define CxRDTy_T(t) ((t << CxRDTy_T_SHIFT) & CxRDTy_T_MASK) +#define CxRDTy_T(t) (((t) << CxRDTy_T_SHIFT) & CxRDTy_T_MASK) #define CxRDTy_P_SHIFT 16 #define CxRDTy_P_MASK (0x7 << CxRDTy_P_SHIFT) -#define CxRDTy_P(p) ((p << CxRDTy_P_SHIFT) & CxRDTy_P_MASK) +#define CxRDTy_P(p) (((p) << CxRDTy_P_SHIFT) & CxRDTy_P_MASK) static const u32 read_training_schedule[] = { 0xfefefefe, 0x7f7f7f7f, 0xbebebebe, 0xdfdfdfdf, 0xeeeeeeee, 0xf7f7f7f7, 0xfafafafa, 0xfdfdfdfd, @@ -276,13 +276,13 @@ /* Write Training. */ #define CxWRTy_T_SHIFT 28 #define CxWRTy_T_MASK (0xf << CxWRTy_T_SHIFT) -#define CxWRTy_T(t) ((t << CxWRTy_T_SHIFT) & CxWRTy_T_MASK) +#define CxWRTy_T(t) (((t) << CxWRTy_T_SHIFT) & CxWRTy_T_MASK) #define CxWRTy_P_SHIFT 24 #define CxWRTy_P_MASK (0x7 << CxWRTy_P_SHIFT) -#define CxWRTy_P(p) ((p << CxWRTy_P_SHIFT) & CxWRTy_P_MASK) +#define CxWRTy_P(p) (((p) << CxWRTy_P_SHIFT) & CxWRTy_P_MASK) #define CxWRTy_F_SHIFT 18 #define CxWRTy_F_MASK (0x3 << CxWRTy_F_SHIFT) -#define CxWRTy_F(f) ((f << CxWRTy_F_SHIFT) & CxWRTy_F_MASK) +#define CxWRTy_F(f) (((f) << CxWRTy_F_SHIFT) & CxWRTy_F_MASK) #define CxWRTy_D_SHIFT 16 #define CxWRTy_D_MASK (0x3 << CxWRTy_D_SHIFT) #define CxWRTy_BELOW_D (0x3 << CxWRTy_D_SHIFT) diff --git a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c index 0b1c789..1d20746 100644 --- a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c +++ b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c @@ -5,29 +5,29 @@ #include <console/console.h> #include "gm45.h" -#define CxRECy_MCHBAR(x, y) (0x14a0 + (x * 0x0100) + ((3 - y) * 4)) +#define CxRECy_MCHBAR(x, y) (0x14a0 + ((x) * 0x0100) + ((3 - (y)) * 4)) #define CxRECy_SHIFT_L 0 #define CxRECy_MASK_L (3 << CxRECy_SHIFT_L) #define CxRECy_SHIFT_H 16 #define CxRECy_MASK_H (3 << CxRECy_SHIFT_H) #define CxRECy_T_SHIFT 28 #define CxRECy_T_MASK (0xf << CxRECy_T_SHIFT) -#define CxRECy_T(t) ((t << CxRECy_T_SHIFT) & CxRECy_T_MASK) +#define CxRECy_T(t) (((t) << CxRECy_T_SHIFT) & CxRECy_T_MASK) #define CxRECy_P_SHIFT 24 #define CxRECy_P_MASK (0x7 << CxRECy_P_SHIFT) -#define CxRECy_P(p) ((p << CxRECy_P_SHIFT) & CxRECy_P_MASK) +#define CxRECy_P(p) (((p) << CxRECy_P_SHIFT) & CxRECy_P_MASK) #define CxRECy_PH_SHIFT 22 #define CxRECy_PH_MASK (0x3 << CxRECy_PH_SHIFT) -#define CxRECy_PH(p) ((p << CxRECy_PH_SHIFT) & CxRECy_PH_MASK) +#define CxRECy_PH(p) (((p) << CxRECy_PH_SHIFT) & CxRECy_PH_MASK) #define CxRECy_PM_SHIFT 20 #define CxRECy_PM_MASK (0x3 << CxRECy_PM_SHIFT) -#define CxRECy_PM(p) ((p << CxRECy_PM_SHIFT) & CxRECy_PM_MASK) +#define CxRECy_PM(p) (((p) << CxRECy_PM_SHIFT) & CxRECy_PM_MASK) #define CxRECy_TIMING_MASK (CxRECy_T_MASK | CxRECy_P_MASK | \ CxRECy_PH_MASK | CxRECy_PM_MASK) #define CxDRT3_C_SHIFT 7 #define CxDRT3_C_MASK (0xf << CxDRT3_C_SHIFT) -#define CxDRT3_C(c) ((c << CxDRT3_C_SHIFT) & CxDRT3_C_MASK) +#define CxDRT3_C(c) (((c) << CxDRT3_C_SHIFT) & CxDRT3_C_MASK) /* group to byte-lane mapping: (cardF X group X 2 per group) */ static const char bytelane_map[2][4][2] = { /* A,B,C */{ { 0, 1 }, { 2, 3 }, { 4, 5 }, { 6, 7 } }, -- To view, visit https://review.coreboot.org/c/coreboot/+/54280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb9d6e8bdafdac7ad820b1629d04e7bdfbcd4b3f Gerrit-Change-Number: 54280 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: enable DPTF functionality for brya
by Tim Wawrzynczak (Code Review) 13 May '21

13 May '21

Attention is currently required from: V Sowmya, John Su, Furquan Shaikh, Sumeet R Pawnikar. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52859 ) Change subject: mb/google/brya: enable DPTF functionality for brya ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52859/comment/1be050ec_bdba6e96 PS5, Line 12: BUG=None Would you mind filing a bug for DPTF enablement? Would be good to see some before-and-after data if available. -- To view, visit https://review.coreboot.org/c/coreboot/+/52859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33266c85aa30869466034ccbab04a3c7820ae2b0 Gerrit-Change-Number: 52859 Gerrit-PatchSet: 5 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Thu, 13 May 2021 17:03:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Add SoC thermal zone
by Raul Rangel (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Tim Wawrzynczak, Rob Barnes. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54134 ) Change subject: mb/google/guybrush: Add SoC thermal zone ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/guybrush/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/54134/comment/648d688c_fb7f7db3 PS1, Line 55: chip drivers/acpi/thermal_zone : register "name" = ""SOC"" : : register "temperature_sensor_id" = "0" : : register "polling_period" = "10000" : : # EC is configured to power off the system at 92C, so add one degree of buffer : # so the OS can gracefully shutdown : register "critical_temperature" = "91" : : # EC is configured to assert PROCHOT at 90C. That drastically lowers : # performance. Instead we will tell the OS to start throttling the CPUs at : # 85C in hopes that we don't hit the PROCHOT limit. : register "passive_config" = "{ : .temperature = 85, : .time_constant_1 = 2, : .time_constant_2 = 5, : .time_sampling_period = 2000, : }" : : device generic 0 on end : end > Another suggestion: The new alias syntax allows you to add a pointer to another `struct device` like […] I think that's a good idea. If we go that route, I think I want to move the acpigen_write_TMP method into `struct device_operations`. This way we can cleanly support multiple temperature controllers. The ec_lpc.c code would set .acpi_write_TMP in its ops. This would all be guarded with DRIVERS_ACPI_THERMAL_ZONE so we don't increase the device tree size for everyone. What do you think? -- To view, visit https://review.coreboot.org/c/coreboot/+/54134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaeed75bdaa16b117d0fa7144ede98db1388f74f3 Gerrit-Change-Number: 54134 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Thu, 13 May 2021 17:02:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: OEM variables support for DPTF
by Karthik Ramasubramanian (Code Review) 13 May '21

13 May '21

Attention is currently required from: Sumeet R Pawnikar. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54098 ) Change subject: ec/google/chromeec: OEM variables support for DPTF ...................................................................... Patch Set 1: (3 comments) File src/ec/google/chromeec/ec_dptf_helpers.c: https://review.coreboot.org/c/coreboot/+/54098/comment/bfd003f0_c16af6b9 PS1, Line 135: ODVP Same comment as below. https://review.coreboot.org/c/coreboot/+/54098/comment/31384b78_1ce31356 PS1, Line 136: acpigen_pop_len(); Can you please add a comment regarding which scope you are trying to pop? Also shouldn't this be done before generating the notification or does it not matter? https://review.coreboot.org/c/coreboot/+/54098/comment/037e1045_8bee3463 PS1, Line 300: ODVE Besides Tim's comment below, the method name is mentioned as ODVP in BWG. -- To view, visit https://review.coreboot.org/c/coreboot/+/54098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79fbf00521d54e66b6cd7d95b026a76fd3a4394b Gerrit-Change-Number: 54098 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Thu, 13 May 2021 16:52:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: enable DPTF functionality for brya
by Sumeet R Pawnikar (Code Review) 13 May '21

13 May '21

Attention is currently required from: V Sowmya, John Su, Furquan Shaikh, Tim Wawrzynczak. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52859 ) Change subject: mb/google/brya: enable DPTF functionality for brya ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/brya/variants/brya0/overridetree.cb: https://review.coreboot.org/c/coreboot/+/52859/comment/60a7a37f_5d5f855c PS4, Line 11: ## below sensor information based on P2 schm and boards available : ## we will update for any change in the next new patch version > remove these lines Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33266c85aa30869466034ccbab04a3c7820ae2b0 Gerrit-Change-Number: 52859 Gerrit-PatchSet: 5 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 13 May 2021 16:45:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/dptf: Add OEM variables support
by Karthik Ramasubramanian (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh, Justin TerAvest, Tim Wawrzynczak, Sumeet R Pawnikar, Todd Broch, Aaron Durbin, Patrick Rudolph. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50127 ) Change subject: drivers/intel/dptf: Add OEM variables support ...................................................................... Patch Set 8: (1 comment) File src/include/acpi/acpigen_dptf.h: https://review.coreboot.org/c/coreboot/+/50127/comment/9a3deb61_51d2efc2 PS8, Line 117: uint8_t oem0; : uint8_t oem1; : uint8_t oem2; : uint8_t oem3; : uint8_t oem4; : uint8_t oem5; : }; > suggestion: representing this as an array will simplify the code, e.g. […] Also why is it part of IETM? As per the BWG doc, I don't see any scope being mentioned for ODVP package. Looking here, it is added under the scope of DPTF_PATH and not IETM. So why is it mentioned as part of ietm? +1 to Tim's comment regarding DWORDS. -- To view, visit https://review.coreboot.org/c/coreboot/+/50127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf3cf7b40e9a441b41d0c659d76895a58669c2fb Gerrit-Change-Number: 50127 Gerrit-PatchSet: 8 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Todd Broch <tbroch(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Justin TerAvest <teravest(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Todd Broch <tbroch(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 13 May 2021 16:32:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Enable HECI1 communication
by Tim Wawrzynczak (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh, Sridhar Siricilla. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54210 ) Change subject: mb/google/brya: Enable HECI1 communication ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73acdd99788f9b60b7bcea372145e9694a124174 Gerrit-Change-Number: 54210 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Thu, 13 May 2021 16:29:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/variants/copano: Redefine GPIO_EC_IN_RW to GPP_F17
by Tim Wawrzynczak (Code Review) 13 May '21

13 May '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54085 ) Change subject: mb/google/volteer/variants/copano: Redefine GPIO_EC_IN_RW to GPP_F17 ...................................................................... mb/google/volteer/variants/copano: Redefine GPIO_EC_IN_RW to GPP_F17 Redefine GPIO_EC_IN_RW to GPP_F17 Signed-off-by: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Change-Id: I428eb8db34c80d38899a2b823ec7193de4a8f5e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54085 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/volteer/variants/copano/include/variant/gpio.h 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Zhuohao Lee: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Hao Chou: Looks good to me, but someone else must approve Wayne3 Wang: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/volteer/variants/copano/include/variant/gpio.h b/src/mainboard/google/volteer/variants/copano/include/variant/gpio.h index b5fa8c5..ed1eea3 100644 --- a/src/mainboard/google/volteer/variants/copano/include/variant/gpio.h +++ b/src/mainboard/google/volteer/variants/copano/include/variant/gpio.h @@ -12,4 +12,8 @@ #define GPIO_MEM_CONFIG_2 GPP_C14 #define GPIO_MEM_CONFIG_3 GPP_D15 +#undef GPIO_EC_IN_RW +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_F17 + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/54085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I428eb8db34c80d38899a2b823ec7193de4a8f5e4 Gerrit-Change-Number: 54085 Gerrit-PatchSet: 2 Gerrit-Owner: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-CC: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-CC: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-MessageType: merged

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coreboot-gerrit May 2021