coreboot-gerrit May 2021

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Change in coreboot[master]: drivers/intel/fsp1_1/romstage.c: Remove MCU update
by Arthur Heymans (Code Review) 29 May '21

29 May '21

Attention is currently required from: Lee Leahy, Huang Jin, Patrick Rudolph. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55064 ) Change subject: drivers/intel/fsp1_1/romstage.c: Remove MCU update ...................................................................... drivers/intel/fsp1_1/romstage.c: Remove MCU update On Braswell this is done in the bootblock before C code is executed. Change-Id: I72c7b821e04169ae237d8adb6a8348f06e87b047 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_1/romstage.c 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/55064/1 diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index ff03805..62b112a 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -103,10 +103,6 @@ timestamp_add_now(TS_START_ROMSTAGE); - /* Load microcode before RAM init */ - if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS)) - intel_update_microcode_from_cbfs(); - /* Display parameters */ if (!CONFIG(NO_MMCONF_SUPPORT)) printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/55064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72c7b821e04169ae237d8adb6a8348f06e87b047 Gerrit-Change-Number: 55064 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Huang Jin <huang.jin(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: use initial_lapicid() instead of opencoding it
by Arthur Heymans (Code Review) 29 May '21

29 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Anjaneya "Reddy" Chagam, Marshall Dawson, Jonathan Zhang, Johnny Lin, Morgan Jang, Patrick Rudolph, Felix Held. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55063 ) Change subject: use initial_lapicid() instead of opencoding it ...................................................................... use initial_lapicid() instead of opencoding it Change-Id: I289015b81b2a9d915c4cab9b0544fc19b85df7a3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/amd/agesa/eventlog.c M src/drivers/amd/agesa/romstage.c M src/soc/amd/picasso/mca.c M src/soc/amd/stoneyridge/mca.c M src/soc/intel/xeon_sp/smmrelocate.c 5 files changed, 10 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/55063/1 diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index 49ab4ce..126a2ee 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cpu/x86/lapic.h> #include <console/console.h> #include <stdint.h> #include <string.h> @@ -97,7 +98,7 @@ { int i; - task->apic_id = (u8) (cpuid_ebx(1) >> 24); + task->apic_id = (u8)initial_lapicid(); task->func = func; task->function_name = undefined; diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 29423ef..cb57e0b 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -6,6 +6,7 @@ #include <arch/romstage.h> #include <cbmem.h> #include <console/console.h> +#include <cpu/x86/lapic.h> #include <halt.h> #include <program_loading.h> #include <romstage_handoff.h> @@ -35,7 +36,7 @@ struct postcar_frame pcf; struct sysinfo romstage_state; struct sysinfo *cb = &romstage_state; - u8 initial_apic_id = (u8) (cpuid_ebx(1) >> 24); + u32 initial_apic_id = initial_lapicid(); int cbmem_initted = 0; fill_sysinfo(cb); diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index aab95ca..3e45154 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -2,6 +2,7 @@ #include <amdblocks/msr_zen.h> #include <amdblocks/reset.h> +#include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> #include <acpi/acpi.h> #include <soc/cpu.h> @@ -163,7 +164,7 @@ for (i = 0 ; i < num_banks ; i++) { mci.sts = rdmsr(MCAX_STATUS_MSR(i)); if (mci.sts.hi || mci.sts.lo) { - int core = cpuid_ebx(1) >> 24; + int core = initial_lapicid(); printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n", core, i, diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index b1f955f..8002e1e 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/reset.h> +#include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> #include <acpi/acpi.h> #include <soc/cpu.h> @@ -165,7 +166,7 @@ mci.sts = rdmsr(IA32_MC0_STATUS + (i * 4)); if (mci.sts.hi || mci.sts.lo) { - int core = cpuid_ebx(1) >> 24; + uint32_t core = initial_lapicid(); printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n", core, i, mca_bank_name[i]); diff --git a/src/soc/intel/xeon_sp/smmrelocate.c b/src/soc/intel/xeon_sp/smmrelocate.c index dc4b511..45e41f6 100644 --- a/src/soc/intel/xeon_sp/smmrelocate.c +++ b/src/soc/intel/xeon_sp/smmrelocate.c @@ -2,6 +2,7 @@ #include <assert.h> #include <string.h> +#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/intel/em64t101_save_state.h> #include <cpu/intel/smm_reloc.h> @@ -96,9 +97,8 @@ smbase = staggered_smbase; iedbase = relo_params->ied_base; - apic_id = cpuid_ebx(1) >> 24; printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n apic_id=0x%x\n", - smbase, iedbase, apic_id); + smbase, iedbase, initial_lapicid()); save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state)); -- To view, visit https://review.coreboot.org/c/coreboot/+/55063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I289015b81b2a9d915c4cab9b0544fc19b85df7a3 Gerrit-Change-Number: 55063 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/car/romstage.c: Drop unused function argument
by Arthur Heymans (Code Review) 29 May '21

29 May '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55062 ) Change subject: cpu/intel/car/romstage.c: Drop unused function argument ...................................................................... cpu/intel/car/romstage.c: Drop unused function argument This is a leftover when migrating to C_ENV_BOOTBLOCK Change-Id: Ibc610cd15448632dc13d87094853d9b981e2679b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/romstage.c 1 file changed, 2 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/55062/1 diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 4b4a4ab..63ddd74 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -16,7 +16,7 @@ static struct postcar_frame early_mtrrs; -static void romstage_main(unsigned long bist) +static void romstage_main(void) { int i; const int num_guards = 64; @@ -58,11 +58,6 @@ /* We do not return here. */ } -/* We don't carry BIST from bootblock in a good location to read from. - * Any error should have been reported in bootblock already. - */ -#define NO_BIST 0 - asmlinkage void car_stage_entry(void) { timestamp_add_now(TS_START_ROMSTAGE); @@ -70,5 +65,5 @@ /* Assumes the hardware was set up during the bootblock */ console_init(); - romstage_main(NO_BIST); + romstage_main(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/55062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc610cd15448632dc13d87094853d9b981e2679b Gerrit-Change-Number: 55062 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: Make fsp_temp_ram_exit() function static
by Subrata Banik (Code Review) 29 May '21

29 May '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55025 ) Change subject: drivers/intel/fsp2_0: Make fsp_temp_ram_exit() function static ...................................................................... drivers/intel/fsp2_0: Make fsp_temp_ram_exit() function static fsp_temp_ram_exit() function is only getting called by late_car_teardown() function inside temp_ram_exit.c file. Hence, make function as static and removed from include/fsp/api.h. Change-Id: I2239400e475482bc21f771d41a5ac524222d40fc Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55025 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/temp_ram_exit.c 2 files changed, 1 insertion(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 8561600..a095b78 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -34,7 +34,6 @@ /* Main FSP stages */ void fsp_memory_init(bool s3wake); void fsp_silicon_init(void); -void fsp_temp_ram_exit(void); /* * Load FSP-S from stage cache or CBFS. This allows SoCs to load FSPS-S diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c index 0ef6c5c..5d7cbd4 100644 --- a/src/drivers/intel/fsp2_0/temp_ram_exit.c +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -7,7 +7,7 @@ #include <cbfs.h> #include <types.h> -void fsp_temp_ram_exit(void) +static void fsp_temp_ram_exit(void) { struct fsp_header hdr; uint32_t status; -- To view, visit https://review.coreboot.org/c/coreboot/+/55025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2239400e475482bc21f771d41a5ac524222d40fc Gerrit-Change-Number: 55025 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/sasukette: Modify the touch pad slave address
by Tao Xia (Code Review) 29 May '21

29 May '21

Attention is currently required from: Henry Sun, Karthik Ramasubramanian. Tao Xia has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55035 ) Change subject: mb/google/dedede/var/sasukette: Modify the touch pad slave address ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: @Karthik Please help do Code-Review. Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/55035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0bd80baa27dfeb7bcb43f0ca4b02e1228e372a6 Gerrit-Change-Number: 55035 Gerrit-PatchSet: 1 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jessie Xu <xuyanan(a)huaqin.corp-partner.google.com> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-CC: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Sat, 29 May 2021 05:49:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/blipper: Configure I2C times for touchpad/touchp...
by Tao Xia (Code Review) 29 May '21

29 May '21

Attention is currently required from: Furquan Shaikh, zanxi chen, Henry Sun, Paul Menzel, Karthik Ramasubramanian, Karthikeyan Ramasubramanian. Tao Xia has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54249 ) Change subject: mb/google/dedede/var/blipper: Configure I2C times for touchpad/touchpanel/codec ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: @Karthik Please help do Code-Review. Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/54249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8438e37be49f8a74f53fd8460110dac1a3f06993 Gerrit-Change-Number: 54249 Gerrit-PatchSet: 3 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ginger Zhang <zhangqingchun(a)huaqin.corp-partner.google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-CC: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Sat, 29 May 2021 05:48:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/... - Add Boot Guard support
by Patrick Rudolph (Code Review) 29 May '21

29 May '21

Attention is currently required from: Christopher Meis, Patrick Rudolph. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55048 ) Change subject: src/... - Add Boot Guard support ...................................................................... Patch Set 3: (1 comment) File src/mainboard/prodrive/hermes/Kconfig: https://review.coreboot.org/c/coreboot/+/55048/comment/e19e31c3_cb0bcf45 PS3, Line 73: C_ENV_BOOTBLOCK_SIZE doesn't the latest css automatically detect the bootblock size? with that feature there's no need for fixed size. -- To view, visit https://review.coreboot.org/c/coreboot/+/55048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b73a79f51692178e8565803efb2c9caf3096ff9 Gerrit-Change-Number: 55048 Gerrit-PatchSet: 3 Gerrit-Owner: Christopher Meis Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christopher Meis Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 29 May 2021 05:12:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: configs: Update configs for OCP Delta Lake for coreboot/LinuxBoot
by Johnny Lin (Code Review) 29 May '21

29 May '21

Attention is currently required from: Anjaneya "Reddy" Chagam, insomniac. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55058 ) Change subject: configs: Update configs for OCP Delta Lake for coreboot/LinuxBoot ...................................................................... Patch Set 1: (1 comment) This change is ready for review. Patchset: PS1: This is for OCP OSF submission image build. -- To view, visit https://review.coreboot.org/c/coreboot/+/55058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib494e4170a7ebb445d9e11df83c370b40a9e5194 Gerrit-Change-Number: 55058 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: insomniac <insomniac(a)slackware.it> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: insomniac <insomniac(a)slackware.it> Gerrit-Comment-Date: Sat, 29 May 2021 00:35:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/intel/xeon_sp: add hardware error support (HEST)
by Rocky Phagura (Code Review) 28 May '21

28 May '21

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Rocky Phagura, Tim Wawrzynczak, David Hendricks, Angel Pons, Arthur Heymans, Morgan Jang, Patrick Rudolph, Tim Chu. Rocky Phagura has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52090 ) Change subject: src/intel/xeon_sp: add hardware error support (HEST) ...................................................................... Patch Set 19: (3 comments) File src/soc/intel/common/block/acpi/acpi/globalnvs.asl: https://review.coreboot.org/c/coreboot/+/52090/comment/52420baa_1a93d891 PS18, Line 27: , 8, // 0x40 - 0x48 Hest log buffer > Where in SMM is this being used? I can't see it. It's in the SOC portion which I cannot upstream until we get approval from HW vendor. File src/soc/intel/xeon_sp/Makefile.inc: https://review.coreboot.org/c/coreboot/+/52090/comment/fbbc8b72_325c73dd PS18, Line 19: ifeq ($(CONFIG_SOC_INTEL_XEON_RAS),y) : subdirs-y += ras : endif > Much simpler: […] Done... File src/soc/intel/xeon_sp/uncore.c: https://review.coreboot.org/c/coreboot/+/52090/comment/18a3b736_edcefba4 PS18, Line 149: * +--------------------------+ cbmem_top : * | HEST ELOG | (CONFIG_ERROR_LOG_BUFFER_SIZE) : * +--------------------------+ > Here the HEST ELOG is below cbmem_top, but in the code it looks like it is above cbmem_top. […] 1. Done...corrected the map so that HEST ELOG is above cbmem_top. 2. Yes, it cannot be part of CBMEM because in the E820 table, CBMEM is labeled as type16 memory (Unknown to the OS) and therefore ACPI drivers fail to acknowledge this memory and generate ACPI errors, unable to load HEST. -- To view, visit https://review.coreboot.org/c/coreboot/+/52090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If76b2af153616182cc053ca878f30fe056e9c8bd Gerrit-Change-Number: 52090 Gerrit-PatchSet: 19 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 28 May 2021 23:28:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Rocky Phagura Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: src/intel/xeon_sp: add hardware error support (HEST)
by Rocky Phagura (Code Review) 28 May '21

28 May '21

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Rocky Phagura, Tim Wawrzynczak, David Hendricks, Morgan Jang, Patrick Rudolph, Tim Chu. Hello build bot (Jenkins), Patrick Georgi, Jonathan Zhang, Rocky Phagura, Angel Pons, Arthur Heymans, Patrick Rudolph, Lance Zhao, Marc Jones, Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Tim Wawrzynczak, David Hendricks, Morgan Jang, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52090 to look at the new patch set (#19). Change subject: src/intel/xeon_sp: add hardware error support (HEST) ...................................................................... src/intel/xeon_sp: add hardware error support (HEST) This patch adds the ACPI hardware error source table (HEST) support. This involves a few different parts: (1) The ACPI HEST table which is filled with the appropriate fields (2) Reserved memory which is used by runtime SW to provide error information. OS will not accept a HEST table with this memory set to 0. The ASL code to enable APEI bit will be submitted in a separate patch. Tested on DeltaLake mainboard with following options enabled SOC_INTEL_XEON_RAS After boot to Linux, the following will show in dmesg: HEST: Table parsing has been initialized Change-Id: If76b2af153616182cc053ca878f30fe056e9c8bd Signed-off-by: Rocky Phagura <rphagura(a)fb.com> --- M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/include/intelblocks/nvs.h M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/include/soc/hest.h M src/soc/intel/xeon_sp/nb_acpi.c A src/soc/intel/xeon_sp/ras/Kconfig A src/soc/intel/xeon_sp/ras/Makefile.inc A src/soc/intel/xeon_sp/ras/hest.c M src/soc/intel/xeon_sp/uncore.c 10 files changed, 175 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/52090/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/52090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If76b2af153616182cc053ca878f30fe056e9c8bd Gerrit-Change-Number: 52090 Gerrit-PatchSet: 19 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Rocky Phagura Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021