coreboot-gerrit May 2021

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Change in coreboot[master]: configs: Update configs for OCP Delta Lake for coreboot/LinuxBoot
by Johnny Lin (Code Review) 28 May '21

28 May '21

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55058 ) Change subject: configs: Update configs for OCP Delta Lake for coreboot/LinuxBoot ...................................................................... configs: Update configs for OCP Delta Lake for coreboot/LinuxBoot Need to put the respective binary blobs in site-local/deltalake to build the final coreboot image. Tested=On OCP Delta Lake it can boot up target Linux OS. Change-Id: Ib494e4170a7ebb445d9e11df83c370b40a9e5194 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M configs/builder/config.ocp.deltalake 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/55058/1 diff --git a/configs/builder/config.ocp.deltalake b/configs/builder/config.ocp.deltalake index 4a8cda1..9766b89 100644 --- a/configs/builder/config.ocp.deltalake +++ b/configs/builder/config.ocp.deltalake @@ -3,15 +3,24 @@ CONFIG_VENDOR_OCP=y CONFIG_BOARD_OCP_DELTALAKE=y +CONFIG_UART_FOR_CONSOLE=1 CONFIG_HAVE_IFD_BIN=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_LINUX_COMMAND_LINE="earlyprintk=uart8250,io,0x2f8,57600n1 console=uart8250,io,0x2f8,57600n1 intel_pstate=disable" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y CONFIG_HAVE_ME_BIN=y CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +# CONFIG_ON_DEVICE_ROM_LOAD is not set CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y -CONFIG_CPU_UCODE_BINARIES="site-local/deltalake/mbf5065a.mcb" +CONFIG_CPU_UCODE_BINARIES="site-local/deltalake/mbf5065b.mcb" CONFIG_ADD_FSP_BINARIES=y CONFIG_FSP_T_FILE="site-local/deltalake/Server_T.fd" CONFIG_FSP_M_FILE="site-local/deltalake/Server_M.fd" CONFIG_FSP_S_FILE="site-local/deltalake/Server_S.fd" CONFIG_ME_BIN_PATH="site-local/deltalake/flashregion_2_intel_me.bin" CONFIG_IFD_BIN_PATH="site-local/deltalake/flashregion_0_flashdescriptor.bin" +CONFIG_CONSOLE_SERIAL_57600=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4=y +CONFIG_PAYLOAD_LINUX=y +CONFIG_PAYLOAD_FILE="site-local/deltalake/linuxboot_uroot_ttys0" -- To view, visit https://review.coreboot.org/c/coreboot/+/55058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib494e4170a7ebb445d9e11df83c370b40a9e5194 Gerrit-Change-Number: 55058 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [NOTFORMERGE] soc/amd/picasso/mca: force machine check error path
by Felix Held (Code Review) 28 May '21

28 May '21

Felix Held has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52617 ) Change subject: [NOTFORMERGE] soc/amd/picasso/mca: force machine check error path ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/52617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e2680477b906ca9a94a7e5d6f5d214124d26fe4 Gerrit-Change-Number: 52617 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: arch/x86/acpi_bert_storage: change return type of bert_errors_present
by Felix Held (Code Review) 28 May '21

28 May '21

Attention is currently required from: Angel Pons. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55023 ) Change subject: arch/x86/acpi_bert_storage: change return type of bert_errors_present ...................................................................... Patch Set 2: (2 comments) File src/arch/x86/acpi_bert_storage.c: https://review.coreboot.org/c/coreboot/+/55023/comment/fde85183_7b165682 PS2, Line 23: int > retype this too? Done https://review.coreboot.org/c/coreboot/+/55023/comment/b9b13856_a31293b5 PS2, Line 38: return bert_region_broken ? 0 : !!bert_region_used; > How about: […] good point; done -- To view, visit https://review.coreboot.org/c/coreboot/+/55023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13d6472deeb26ba92d257761df069e32d9b2e5d4 Gerrit-Change-Number: 55023 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 28 May 2021 16:38:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/acpi_bert_storage: change return type of bert_errors_present
by Felix Held (Code Review) 28 May '21

28 May '21

Attention is currently required from: Felix Held. Hello build bot (Jenkins), Paul Menzel, Angel Pons, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55023 to look at the new patch set (#3). Change subject: arch/x86/acpi_bert_storage: change return type of bert_errors_present ...................................................................... arch/x86/acpi_bert_storage: change return type of bert_errors_present The return value is a boolean, so use the bool type. Also add the types.h header to have the bool type defined. Also change type of bert_region_broken static variable to bool. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I13d6472deeb26ba92d257761df069e32d9b2e5d4 --- M src/arch/x86/acpi_bert_storage.c M src/arch/x86/include/arch/bert_storage.h 2 files changed, 8 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/55023/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/55023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13d6472deeb26ba92d257761df069e32d9b2e5d4 Gerrit-Change-Number: 55023 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/picasso: fix MCACHE on psp_verstage RO boot
by Felix Held (Code Review) 28 May '21

28 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54711 ) Change subject: soc/amd/picasso: fix MCACHE on psp_verstage RO boot ...................................................................... soc/amd/picasso: fix MCACHE on psp_verstage RO boot On RW boot path psp_verstage call cbfs_map which calls chain of _cbfs_alloc, cbfs_boot_lookup and cbfs_get_boot_device. Then cbfs_get_boot_device initializes MCACHE which is used later. However on RO boot path psp_verstage doesn't try to find anything in the CBFS which results RO MCACHE not to be initialized. Add cbfs_get_boot_device(true) to explicitly initialize MCACHE on recovery boot. BUG=b:177091575 BRANCH=none TEST=build and boot jelboz Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: I6c4b522fef5a4affd215faa122bdf6b53190cf3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54711 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/psp_verstage/psp_verstage.c M src/soc/amd/picasso/Kconfig 2 files changed, 10 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 2265e17..5c59c4f 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -238,6 +238,16 @@ reboot_into_recovery(ctx, retval); post_code(POSTCODE_UPDATE_BOOT_REGION); + + /* + * Since psp_verstage doesn't load next stage we never call + * any cbfs API on RO path. However we still need to initialize + * RO CBFS MCACHE manually to pass it in transfer_buffer. + * In RW path, MCACHE build will be skipped for RO region since + * we already built here. + */ + cbfs_get_boot_device(true); + retval = update_boot_region(ctx); if (retval) reboot_into_recovery(ctx, retval); diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index b930277..4bfd093 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -67,7 +67,6 @@ select FSP_COMPRESS_FSP_S_LZMA select UDK_2017_BINDING select HAVE_CF9_RESET - select NO_CBFS_MCACHE if VBOOT_STARTS_BEFORE_BOOTBLOCK config SOC_AMD_COMMON_BLOCK_UCODE_SIZE default 3200 -- To view, visit https://review.coreboot.org/c/coreboot/+/54711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c4b522fef5a4affd215faa122bdf6b53190cf3d Gerrit-Change-Number: 54711 Gerrit-PatchSet: 6 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: acpi: drop unused parameter from acpi_soc_fill_bert
by Felix Held (Code Review) 28 May '21

28 May '21

Attention is currently required from: Lance Zhao, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55052 ) Change subject: acpi: drop unused parameter from acpi_soc_fill_bert ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I wonder why the parameter is unused. To me, it doesn't make much sense... the next call (acpi_write_bert) fills the ssdt, so the parameter isn't needed for this function -- To view, visit https://review.coreboot.org/c/coreboot/+/55052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic354824468f016a7857c6990024ae87db6fd00bf Gerrit-Change-Number: 55052 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 28 May 2021 16:12:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/include/bert_storage: introduce and use bert_generate_ssdt
by Felix Held (Code Review) 28 May '21

28 May '21

Attention is currently required from: Angel Pons, Arthur Heymans. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55024 ) Change subject: arch/x86/include/bert_storage: introduce and use bert_generate_ssdt ...................................................................... Patch Set 2: (1 comment) File src/arch/x86/include/arch/bert_storage.h: https://review.coreboot.org/c/coreboot/+/55024/comment/ea77ecd0_b5ac7e6e PS2, Line 60: bert_generate_ssdt > To me, the `bert_generate_ssdt` function name sounds like it's a procedure that generates the BERT S […] good point. i'll do that as a follow-up to avoid rebases, since the code that uses this gets moved around a bit. see CB:55057 -- To view, visit https://review.coreboot.org/c/coreboot/+/55024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia955f627c190ea38e05b5aaedc7cb2d030274e83 Gerrit-Change-Number: 55024 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 28 May 2021 16:11:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/include/bert_storage: rename bert_generate_ssdt
by Felix Held (Code Review) 28 May '21

28 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55057 ) Change subject: arch/x86/include/bert_storage: rename bert_generate_ssdt ...................................................................... arch/x86/include/bert_storage: rename bert_generate_ssdt Since it doesn't generate the SSDT, but only indicates if a SSDT should be generated, rename this to bert_should_generate_ssdt. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Suggested-by: Angel Pons <th3fanbus(a)gmail.com> Change-Id: If55cb54ee5f788e5a8d1fc4ececa9d8d4c2c51cf --- M src/arch/x86/include/arch/bert_storage.h M src/soc/amd/common/block/acpi/bert.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/55057/1 diff --git a/src/arch/x86/include/arch/bert_storage.h b/src/arch/x86/include/arch/bert_storage.h index 794fb83..527afcb 100644 --- a/src/arch/x86/include/arch/bert_storage.h +++ b/src/arch/x86/include/arch/bert_storage.h @@ -57,7 +57,7 @@ /* Find if errors were added, a BERT region is present, and ACPI table needed */ bool bert_errors_present(void); /* The BERT SSDT should only be generated when BERT support is enabled and there's an error */ -static inline bool bert_generate_ssdt(void) +static inline bool bert_should_generate_ssdt(void) { return CONFIG(ACPI_BERT) && bert_errors_present(); } diff --git a/src/soc/amd/common/block/acpi/bert.c b/src/soc/amd/common/block/acpi/bert.c index 9102715..81294c9 100644 --- a/src/soc/amd/common/block/acpi/bert.c +++ b/src/soc/amd/common/block/acpi/bert.c @@ -12,7 +12,7 @@ * a table with a 0-length region: * BERT: [Firmware Bug]: table invalid. */ - if (!bert_generate_ssdt()) + if (!bert_should_generate_ssdt()) return CB_ERR; bert_errors_region(region, length); -- To view, visit https://review.coreboot.org/c/coreboot/+/55057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If55cb54ee5f788e5a8d1fc4ececa9d8d4c2c51cf Gerrit-Change-Number: 55057 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd: factor out acpi_soc_get_bert_region to amd/common
by Felix Held (Code Review) 28 May '21

28 May '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55056 ) Change subject: soc/amd: factor out acpi_soc_get_bert_region to amd/common ...................................................................... soc/amd: factor out acpi_soc_get_bert_region to amd/common This also adds BERT SSDT gerenation support for Cezanne, but since the functionality to populate the BERT memory region isn't implemented yet, this won't result in a BERT SSDT being generated on Cezanne, since bert_generate_ssdt will always return false there. TEST=BERT SSDT generation still works on AMD/Mandolin Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I69b4a9a7432041e1f4902436fa4e6dee5332dbd2 --- M src/soc/amd/common/block/acpi/Makefile.inc A src/soc/amd/common/block/acpi/bert.c M src/soc/amd/picasso/agesa_acpi.c M src/soc/amd/stoneyridge/northbridge.c 4 files changed, 26 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/55056/1 diff --git a/src/soc/amd/common/block/acpi/Makefile.inc b/src/soc/amd/common/block/acpi/Makefile.inc index 9f774d4..30e01dd 100644 --- a/src/soc/amd/common/block/acpi/Makefile.inc +++ b/src/soc/amd/common/block/acpi/Makefile.inc @@ -9,6 +9,7 @@ ramstage-y += pm_state.c ramstage-y += tables.c +ramstage-$(CONFIG_ACPI_BERT) += bert.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_ALIB) += alib.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_GPIO) += gpio.c diff --git a/src/soc/amd/common/block/acpi/bert.c b/src/soc/amd/common/block/acpi/bert.c new file mode 100644 index 0000000..9102715 --- /dev/null +++ b/src/soc/amd/common/block/acpi/bert.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <arch/bert_storage.h> +#include <console/console.h> +#include <types.h> + +enum cb_err acpi_soc_get_bert_region(void **region, size_t *length) +{ + /* + * Skip the table if no errors are present. ACPI driver reports + * a table with a 0-length region: + * BERT: [Firmware Bug]: table invalid. + */ + if (!bert_generate_ssdt()) + return CB_ERR; + + bert_errors_region(region, length); + if (!region) { + printk(BIOS_ERR, "Error: Can't find BERT storage area\n"); + return CB_ERR; + } + + return CB_SUCCESS; +} diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index 3fd2550..abac9c1 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -3,7 +3,6 @@ #include <acpi/acpi.h> #include <acpi/acpi_crat.h> #include <acpi/acpi_ivrs.h> -#include <arch/bert_storage.h> #include <console/console.h> #include <cpu/amd/cpuid.h> #include <cpu/amd/msr.h> @@ -1017,22 +1016,3 @@ return current; } - -enum cb_err acpi_soc_get_bert_region(void **region, size_t *length) -{ - /* - * Skip the table if no errors are present. ACPI driver reports - * a table with a 0-length region: - * BERT: [Firmware Bug]: table invalid. - */ - if (!bert_generate_ssdt()) - return CB_ERR; - - bert_errors_region(region, length); - if (!region) { - printk(BIOS_ERR, "Error: Can't find BERT storage area\n"); - return CB_ERR; - } - - return CB_SUCCESS; -} diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index fc6d39e..a2e719b 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -26,7 +26,6 @@ #include <soc/iomap.h> #include <stdint.h> #include <string.h> -#include <arch/bert_storage.h> #include "chip.h" @@ -326,25 +325,6 @@ .devices = pci_device_ids, }; -enum cb_err acpi_soc_get_bert_region(void **region, size_t *length) -{ - /* - * Skip the table if no errors are present. ACPI driver reports - * a table with a 0-length region: - * BERT: [Firmware Bug]: table invalid. - */ - if (!bert_generate_ssdt()) - return CB_ERR; - - bert_errors_region(region, length); - if (!region) { - printk(BIOS_ERR, "Error: Can't find BERT storage area\n"); - return CB_ERR; - } - - return CB_SUCCESS; -} - /* * Enable VGA cycles. Set memory ranges of the FCH legacy devices (TPM, HPET, * BIOS RAM, Watchdog Timer, IOAPIC and ACPI) as non-posted. Set remaining -- To view, visit https://review.coreboot.org/c/coreboot/+/55056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69b4a9a7432041e1f4902436fa4e6dee5332dbd2 Gerrit-Change-Number: 55056 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpi: drop unused parameter from acpi_soc_fill_bert
by Angel Pons (Code Review) 28 May '21

28 May '21

Attention is currently required from: Lance Zhao, Tim Wawrzynczak, Patrick Rudolph, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55052 ) Change subject: acpi: drop unused parameter from acpi_soc_fill_bert ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I wonder why the parameter is unused. To me, it doesn't make much sense... -- To view, visit https://review.coreboot.org/c/coreboot/+/55052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic354824468f016a7857c6990024ae87db6fd00bf Gerrit-Change-Number: 55052 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 May 2021 15:51:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2021