coreboot-gerrit May 2021

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Change in coreboot[master]: soc/amd/picasso/agesa_acpi: add BERT support
by Felix Held (Code Review) 28 May '21

28 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54149 to look at the new patch set (#4). Change subject: soc/amd/picasso/agesa_acpi: add BERT support ...................................................................... soc/amd/picasso/agesa_acpi: add BERT support Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I14577e80e722cb5ccf344a4520cf3adde669fc5e --- M src/soc/amd/picasso/agesa_acpi.c 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/54149/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/54149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14577e80e722cb5ccf344a4520cf3adde669fc5e Gerrit-Change-Number: 54149 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86/acpi_bert_storage: unbreak BERT support
by Felix Held (Code Review) 28 May '21

28 May '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54738 to look at the new patch set (#3). Change subject: arch/x86/acpi_bert_storage: unbreak BERT support ...................................................................... arch/x86/acpi_bert_storage: unbreak BERT support commit 522e0dbdaa46dde5363ad4c50a11938ae2f17a0d (acpi: Add support for reporting CrashLog in BERT table) broke the BERT support for AMD platforms. [1] is the check in the Linux kernel that failed after that patch. CB:55006 moves the calculations that are needed by the Intel SoC BERT support to the SoC code, so this change shouldn't break it. TEST=When injecting a BERT error Linux on AMD/Mandolin is able to decode and display the error. [1] https://elixir.bootlin.com/linux/v5.12.6/source/drivers/firmware/efi/cper.c… Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic2d2a115f3f2879c3d3a02f3ee8aee82f00f2ac7 --- M src/arch/x86/acpi_bert_storage.c 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/54738/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/54738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2d2a115f3f2879c3d3a02f3ee8aee82f00f2ac7 Gerrit-Change-Number: 54738 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Update CrashLog data length tracking
by Felix Held (Code Review) 28 May '21

28 May '21

Attention is currently required from: Martin Roth, Patrick Rudolph, Felix Held. Felix Held has uploaded a new patch set (#3) to the change originally created by Francois Toguo Fotso. ( https://review.coreboot.org/c/coreboot/+/55006 ) Change subject: soc/intel/common: Update CrashLog data length tracking ...................................................................... soc/intel/common: Update CrashLog data length tracking The CrashLog raw_data_length, previously used to track the length for the Intel CrashLog decoder, is causing noises in the Linux kernel for AMD. Hence this update made at the soc level which will enable the pulling put of the tracking from x86/acpi_bert_storage.c. BUG=None TEST=Built, and BERT successfully generated in the crashLog flow. Signed-off-by: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Change-Id: I97ff14d62bda69389c7647fcbbf23d5cab2b36e6 --- M src/soc/intel/common/block/acpi/acpi_bert.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/55006/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/55006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97ff14d62bda69389c7647fcbbf23d5cab2b36e6 Gerrit-Change-Number: 55006 Gerrit-PatchSet: 3 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Nikunj Dadhania <nikunj.dadhania(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86/include/bert_storage: introduce and use bert_generate_ssdt
by Felix Held (Code Review) 28 May '21

28 May '21

Attention is currently required from: Felix Held. Hello build bot (Jenkins), Paul Menzel, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55024 to look at the new patch set (#2). Change subject: arch/x86/include/bert_storage: introduce and use bert_generate_ssdt ...................................................................... arch/x86/include/bert_storage: introduce and use bert_generate_ssdt Since bert_errors_present() is only available when ACPI_BERT is selected the ACPI table generation code needs to check that before calling the function, so add bert_generate_ssdt that returns false when ACPI_BERT isn't selected or the return value of bert_errors_present() when ACPI_BERT is selected. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia955f627c190ea38e05b5aaedc7cb2d030274e83 --- M src/arch/x86/include/arch/bert_storage.h M src/soc/amd/stoneyridge/northbridge.c 2 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/55024/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia955f627c190ea38e05b5aaedc7cb2d030274e83 Gerrit-Change-Number: 55024 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: Initialize SSPM
by Rex-BC Chen (Code Review) 28 May '21

28 May '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55051 to look at the new patch set (#2). Change subject: soc/mediatek: Initialize SSPM ...................................................................... soc/mediatek: Initialize SSPM Load SSPM firmware and boot up SSPM in ramstage. TEST=none Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ia227ea9f7d58129068cb36ec2de7d9feb677006b --- M src/soc/mediatek/mt8195/Kconfig M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/soc.c 3 files changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/55051/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia227ea9f7d58129068cb36ec2de7d9feb677006b Gerrit-Change-Number: 55051 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: Initialize SSPM
by Rex-BC Chen (Code Review) 28 May '21

28 May '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55051 ) Change subject: soc/mediatek: Initialize SSPM ...................................................................... soc/mediatek: Initialize SSPM Load SSPM firmware and boot up SSPM in ramstage. TEST=none Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ia227ea9f7d58129068cb36ec2de7d9feb677006b --- M src/soc/mediatek/mt8195/Kconfig M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/soc.c 3 files changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/55051/1 diff --git a/src/soc/mediatek/mt8195/Kconfig b/src/soc/mediatek/mt8195/Kconfig index f9bf846..6412d04 100644 --- a/src/soc/mediatek/mt8195/Kconfig +++ b/src/soc/mediatek/mt8195/Kconfig @@ -25,6 +25,12 @@ help The file name of the MediaTek MCUPM firmware. +config SSPM_FIRMWARE + string + default "sspm.bin" + help + The file name of the MediaTek SSPM firmware. + config FLASH_DUAL_READ bool default y diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 1f89a58..ae325d5 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -54,6 +54,7 @@ ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += soc.c +ramstage-y += ../common/sspm.c ramstage-y += ../common/timer.c timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/ufs.c @@ -66,7 +67,8 @@ MT8195_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8195 mcu-firmware-files := \ - $(CONFIG_MCUPM_FIRMWARE) + $(CONFIG_MCUPM_FIRMWARE) \ + $(CONFIG_SSPM_FIRMWARE) $(foreach fw, $(call strip_quotes,$(mcu-firmware-files)), \ $(eval $(fw)-file := $(MT8195_BLOB_DIR)/$(fw)) \ diff --git a/src/soc/mediatek/mt8195/soc.c b/src/soc/mediatek/mt8195/soc.c index 3ebf23d..f9f4f99 100644 --- a/src/soc/mediatek/mt8195/soc.c +++ b/src/soc/mediatek/mt8195/soc.c @@ -4,6 +4,7 @@ #include <soc/emi.h> #include <soc/mcupm.h> #include <soc/mmu_operations.h> +#include <soc/sspm.h> #include <soc/ufs.h> #include <symbols.h> @@ -16,6 +17,7 @@ { mtk_mmu_disable_l2c_sram(); mcupm_init(); + sspm_init(); ufs_disable_refclk(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/55051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia227ea9f7d58129068cb36ec2de7d9feb677006b Gerrit-Change-Number: 55051 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek: Move the SSPM driver to common
by Rex-BC Chen (Code Review) 28 May '21

28 May '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55050 ) Change subject: soc/mediatek: Move the SSPM driver to common ...................................................................... soc/mediatek: Move the SSPM driver to common The SSPM drivers can be shared by MT8183, MT8192 and MT8195. TEST=emerge-{asurada, kukui} coreboot; Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: If9779853becb298eeeabb3dc6096bc474baae202 --- A src/soc/mediatek/common/include/soc/sspm.h R src/soc/mediatek/common/sspm.c M src/soc/mediatek/mt8183/Makefile.inc D src/soc/mediatek/mt8183/include/soc/sspm.h M src/soc/mediatek/mt8192/Makefile.inc D src/soc/mediatek/mt8192/include/soc/sspm.h D src/soc/mediatek/mt8192/sspm.c 7 files changed, 17 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/55050/1 diff --git a/src/soc/mediatek/common/include/soc/sspm.h b/src/soc/mediatek/common/include/soc/sspm.h new file mode 100644 index 0000000..ff405ce --- /dev/null +++ b/src/soc/mediatek/common/include/soc/sspm.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_COMMON_SSPM_H +#define SOC_MEDIATEK_COMMON_SSPM_H + +#include <soc/addressmap.h> +#include <types.h> + +struct sspm_regs { + u32 sw_rstn; +}; +static struct sspm_regs *const sspm_reg = (void *)SSPM_CFG_BASE; +void sspm_init(void); +#endif /* SOC_MEDIATEK_COMMON_SSPM_H */ diff --git a/src/soc/mediatek/mt8183/sspm.c b/src/soc/mediatek/common/sspm.c similarity index 92% rename from src/soc/mediatek/mt8183/sspm.c rename to src/soc/mediatek/common/sspm.c index e0ac84a..0a4d5b0 100644 --- a/src/soc/mediatek/mt8183/sspm.c +++ b/src/soc/mediatek/common/sspm.c @@ -7,7 +7,7 @@ static void reset_sspm(struct mtk_mcu *mcu) { - write32(&mt8183_sspm->sw_rstn, 0x1); + write32(&sspm_reg->sw_rstn, 0x1); } static struct mtk_mcu sspm = { diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index e0ec810..2cf8133 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -58,7 +58,7 @@ ramstage-y += soc.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += spm.c -ramstage-y += sspm.c +ramstage-y += ../common/sspm.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c diff --git a/src/soc/mediatek/mt8183/include/soc/sspm.h b/src/soc/mediatek/mt8183/include/soc/sspm.h deleted file mode 100644 index 23160a8..0000000 --- a/src/soc/mediatek/mt8183/include/soc/sspm.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef SOC_MEDIATEK_MT8183_SSPM_H -#define SOC_MEDIATEK_MT8183_SSPM_H - -#include <soc/addressmap.h> -#include <types.h> - -struct mt8183_sspm_regs { - u32 sw_rstn; -}; -static struct mt8183_sspm_regs *const mt8183_sspm = (void *)SSPM_CFG_BASE; -void sspm_init(void); -#endif /* SOC_MEDIATEK_MT8183_SSPM_H */ diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index bdff835..0943e7c 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -61,7 +61,7 @@ ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c ramstage-y += soc.c ramstage-y += spm.c -ramstage-y += sspm.c +ramstage-y += ../common/sspm.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/ufs.c diff --git a/src/soc/mediatek/mt8192/include/soc/sspm.h b/src/soc/mediatek/mt8192/include/soc/sspm.h deleted file mode 100644 index 5749fa4..0000000 --- a/src/soc/mediatek/mt8192/include/soc/sspm.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef SOC_MEDIATEK_MT8192_SSPM_H -#define SOC_MEDIATEK_MT8192_SSPM_H - -#include <soc/addressmap.h> -#include <types.h> - -struct mt8192_sspm_regs { - u32 sw_rstn; -}; -static struct mt8192_sspm_regs *const mt8192_sspm = (void *)SSPM_CFG_BASE; -void sspm_init(void); -#endif /* SOC_MEDIATEK_MT8192_SSPM_H */ diff --git a/src/soc/mediatek/mt8192/sspm.c b/src/soc/mediatek/mt8192/sspm.c deleted file mode 100644 index cce08c2..0000000 --- a/src/soc/mediatek/mt8192/sspm.c +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/mmio.h> -#include <soc/mcu_common.h> -#include <soc/sspm.h> -#include <soc/symbols.h> - -static void reset_sspm(struct mtk_mcu *mcu) -{ - write32(&mt8192_sspm->sw_rstn, 0x1); -} - -static struct mtk_mcu sspm = { - .firmware_name = CONFIG_SSPM_FIRMWARE, - .run_address = (void *)SSPM_SRAM_BASE, - .reset = reset_sspm, -}; - -void sspm_init(void) -{ - sspm.load_buffer = _dram_dma; - sspm.buffer_size = REGION_SIZE(dram_dma); - - mtk_init_mcu(&sspm); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/55050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9779853becb298eeeabb3dc6096bc474baae202 Gerrit-Change-Number: 55050 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpi: Add support for reporting CrashLog in BERT table
by Francois Toguo Fotso (Code Review) 28 May '21

28 May '21

Francois Toguo Fotso has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49799 ) Change subject: acpi: Add support for reporting CrashLog in BERT table ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: Starting next week I will be out of office for about 2 months and won't be available to review patches, until I return. If the CLs you want me to review can wait until then, fine. Otherwise I would suggest not making any changes to the Intel flow at all. Our flow has been validated multiple times by us and Google (as attested by Tim in this CL) and it is in use in a program execution. CB:55006 has removed any dependency you had on the Intel flow, you can now safely remove the raw_data_length change which was interfering with yours. While I am away if changes are made to the common code, then before they are merged, Tim can verify that they are not breaking the Intel CrashLog both on TGL and ADL. He has now become an expert on that flow. -- To view, visit https://review.coreboot.org/c/coreboot/+/49799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00e390d735d61beac2e89a726e39119d9b06b3df Gerrit-Change-Number: 49799 Gerrit-PatchSet: 10 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nikunj Dadhania <nikunj.dadhania(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Comment-Date: Fri, 28 May 2021 14:24:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: [WIP]Set BASE Addresses for TBT DMA remapping en...
by Sridhar Siricilla (Code Review) 28 May '21

28 May '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph. Sridhar Siricilla has removed Meera Ravindranath from this change. ( https://review.coreboot.org/c/coreboot/+/55015 ) Change subject: soc/intel/alderlake: [WIP]Set BASE Addresses for TBT DMA remapping engine ...................................................................... Removed reviewer Meera Ravindranath. -- To view, visit https://review.coreboot.org/c/coreboot/+/55015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I669255065d60d73c4bea0eeb732c4114bcc447c0 Gerrit-Change-Number: 55015 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: soc/intel/alderlake: [WIP]Set BASE Addresses for TBT DMA remapping en...
by Sridhar Siricilla (Code Review) 28 May '21

28 May '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Meera Ravindranath, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Meera Ravindranath, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55015 to look at the new patch set (#3). Change subject: soc/intel/alderlake: [WIP]Set BASE Addresses for TBT DMA remapping engine ...................................................................... soc/intel/alderlake: [WIP]Set BASE Addresses for TBT DMA remapping engine The patch configures 4KB memory region window for each of the TBT DMA remapping engine. So, the remap engines map their register set to the respective 4KB window. TEST=TBD Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I669255065d60d73c4bea0eeb732c4114bcc447c0 --- M src/soc/intel/alderlake/romstage/fsp_params.c 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/55015/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/55015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I669255065d60d73c4bea0eeb732c4114bcc447c0 Gerrit-Change-Number: 55015 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021