coreboot-gerrit May 2021

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Change in coreboot[master]: soc/amd/picasso: remove warm reset flag code
by Felix Held (Code Review) 28 May '21

28 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55059 to look at the new patch set (#2). Change subject: soc/amd/picasso: remove warm reset flag code ...................................................................... soc/amd/picasso: remove warm reset flag code Since the MCA(X) registers have defined values on the cold boot path, the is_warm_reset check can be dropped. Also the warm reset bit in the NCP_ERR register doesn't behave as the PPR suggested; no matter if something was written to the register or the machine went through a warm reset cycle, the NCP_WARM_BOOT bit never got set. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I4e6df98ffd5d15ca204c9847a76c19c753726737 --- M src/soc/amd/picasso/cpu.c M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/mca.c M src/soc/amd/picasso/reset.c 5 files changed, 25 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/55059/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e6df98ffd5d15ca204c9847a76c19c753726737 Gerrit-Change-Number: 55059 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: ec: To test OEM variables functionality
by Sumeet R Pawnikar (Code Review) 28 May '21

28 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Aaron Durbin, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Aaron Durbin, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51937 to look at the new patch set (#5). Change subject: ec: To test OEM variables functionality ...................................................................... ec: To test OEM variables functionality Test OEM variables functionality with different conditions BRANCH=None BUG=b:187253038 TEST=Built and tested on dedede board Change-Id: I65e7245d8e4dadaa3ad9ea14d606940ca364e5a1 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/ec/google/chromeec/acpi/ec.asl 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/51937/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/51937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65e7245d8e4dadaa3ad9ea14d606940ca364e5a1 Gerrit-Change-Number: 51937 Gerrit-PatchSet: 5 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: ec/google/chromeec: OEM variables support for DPTF
by Sumeet R Pawnikar (Code Review) 28 May '21

28 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Sumeet R Pawnikar, Aaron Durbin, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54098 to look at the new patch set (#4). Change subject: ec/google/chromeec: OEM variables support for DPTF ...................................................................... ec/google/chromeec: OEM variables support for DPTF This adds OEM variables support for DPTF to notify the change. BRANCH=None BUG=b:187253038 TEST=Built and tested on dedede board Change-Id: I79fbf00521d54e66b6cd7d95b026a76fd3a4394b Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/ec/google/chromeec/ec_dptf_helpers.c M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/include/intelblocks/nvs.h 3 files changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/54098/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/54098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79fbf00521d54e66b6cd7d95b026a76fd3a4394b Gerrit-Change-Number: 54098 Gerrit-PatchSet: 4 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Documentation/community: Add link to the OSF Slack
by Patrick Georgi (Code Review) 28 May '21

28 May '21

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55036 ) Change subject: Documentation/community: Add link to the OSF Slack ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d9887e524e47e6f42a5013e9f696881ef54a631 Gerrit-Change-Number: 55036 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 28 May 2021 17:58:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Fix up toctree
by Patrick Georgi (Code Review) 28 May '21

28 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55020 ) Change subject: Documentation: Fix up toctree ...................................................................... Documentation: Fix up toctree Some files weren't properly hooked up, making Sphinx complain. Change-Id: If959fa63d4ddbc3916c49c5ad6602e76b12a7e60 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55020 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/infrastructure/index.md M Documentation/mainboard/index.md M Documentation/technotes/index.md 3 files changed, 3 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Felix Singer: Looks good to me, approved Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/Documentation/infrastructure/index.md b/Documentation/infrastructure/index.md index 42bcbf6..a452013 100644 --- a/Documentation/infrastructure/index.md +++ b/Documentation/infrastructure/index.md @@ -3,4 +3,4 @@ This section contains documentation about coreboot infrastructure ## Jenkins builders and builds -[Setting up Jenkins build machines](builders.md) +* [Setting up Jenkins build machines](builders.md) diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 3307271..a08cc43 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -153,6 +153,7 @@ ## Purism +- [Librem 14](purism/librem_14.md) - [Librem Mini](purism/librem_mini.md) ## Protectli diff --git a/Documentation/technotes/index.md b/Documentation/technotes/index.md index a9320fb..fda8bd6 100644 --- a/Documentation/technotes/index.md +++ b/Documentation/technotes/index.md @@ -3,4 +3,5 @@ * [Dealing with Untrusted Input in SMM](2017-02-dealing-with-untrusted-input-in-smm.md) * [Rebuilding coreboot image generation](2015-11-rebuilding-coreboot-image-generation.md) * [Unit testing coreboot](2020-03-unit-testing-coreboot.md) +* [Unit Test Code Coverage](2021-05-code-coverage.md) * [Address Sanitizer](asan.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/55020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If959fa63d4ddbc3916c49c5ad6602e76b12a7e60 Gerrit-Change-Number: 55020 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Documentation: Fix named link
by Patrick Georgi (Code Review) 28 May '21

28 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55019 ) Change subject: Documentation: Fix named link ...................................................................... Documentation: Fix named link The syntax requires two bracketed fields. Change-Id: I98ebe714e57f50017755eed7888f0dd2637a3066 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55019 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M Documentation/mainboard/supermicro/flashing_on_vendorbmc.md 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Felix Singer: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/Documentation/mainboard/supermicro/flashing_on_vendorbmc.md b/Documentation/mainboard/supermicro/flashing_on_vendorbmc.md index c831302..377d900 100644 --- a/Documentation/mainboard/supermicro/flashing_on_vendorbmc.md +++ b/Documentation/mainboard/supermicro/flashing_on_vendorbmc.md @@ -34,7 +34,7 @@ ## Flashing with disabled ME If ME is disabled via `me_cleaner` or the ME recovery jumper, it is still -possible to flash remotely with the [`Supermicro Update Manager`](SUM) (`SUM`). +possible to flash remotely with the [`Supermicro Update Manager`][SUM] (`SUM`). ```sh ./sum -i <remote BMC IP> -u <user> -p <password> -c UpdateBios --reboot \ -- To view, visit https://review.coreboot.org/c/coreboot/+/55019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98ebe714e57f50017755eed7888f0dd2637a3066 Gerrit-Change-Number: 55019 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso: remove warm reset flag code
by Felix Held (Code Review) 28 May '21

28 May '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55059 ) Change subject: soc/amd/picasso: remove warm reset flag code ...................................................................... soc/amd/picasso: remove warm reset flag code Since the MCA(X) registers have defined values on the cold boot path, the is_warm_reset check can be dropped. Also the warm reset bit in the NCP_ERR register doesn't behave as the PPR suggested; no matter if something was written to the register or the machine went through a warm reset cycle, the NCP_WARM_BOOT bit never got set. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I4e6df98ffd5d15ca204c9847a76c19c753726737 --- M src/soc/amd/picasso/cpu.c M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/mca.c M src/soc/amd/picasso/reset.c 5 files changed, 25 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/55059/1 diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 5acaa69..4e9c9a9 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -59,8 +59,6 @@ /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); - - set_warm_reset_flag(); } static void model_17_init(struct device *dev) diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 5b75ecb..b6f5dbb 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -83,7 +83,6 @@ #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) /* 8 bytes */ #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */ -#define NCP_ERR 0xf0 #define SMB_BASE_ADDR 0xb00 #define PM2_INDEX 0xcd0 #define PM2_DATA 0xcd1 diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 11660aa..b623ed3 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -140,9 +140,6 @@ #define SATA_CAPABILITIES_REG 0xfc #define SATA_CAPABILITY_SPM BIT(12) -/* IO 0xf0 NCP Error */ -#define NCP_WARM_BOOT BIT(7) /* Write-once */ - typedef struct aoac_devs { unsigned int :7; unsigned int ic2e:1; /* 7: I2C2 */ diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index aab95ca..2576f6e 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -159,36 +159,34 @@ cap = rdmsr(IA32_MCG_CAP); num_banks = cap.lo & MCA_BANKS_MASK; - if (is_warm_reset()) { - for (i = 0 ; i < num_banks ; i++) { - mci.sts = rdmsr(MCAX_STATUS_MSR(i)); - if (mci.sts.hi || mci.sts.lo) { - int core = cpuid_ebx(1) >> 24; + for (i = 0 ; i < num_banks ; i++) { + mci.sts = rdmsr(MCAX_STATUS_MSR(i)); + if (mci.sts.hi || mci.sts.lo) { + int core = cpuid_ebx(1) >> 24; - printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n", - core, i, - i < ARRAY_SIZE(mca_bank_name) ? mca_bank_name[i] : ""); + printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n", + core, i, + i < ARRAY_SIZE(mca_bank_name) ? mca_bank_name[i] : ""); - printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n", - i, mci.sts.hi, mci.sts.lo); - mci.addr = rdmsr(MCAX_ADDR_MSR(i)); - printk(BIOS_WARNING, " MC%d_ADDR = %08x_%08x\n", - i, mci.addr.hi, mci.addr.lo); - mci.misc = rdmsr(MCAX_MISC0_MSR(i)); - printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n", - i, mci.misc.hi, mci.misc.lo); - mci.ctl = rdmsr(MCAX_CTL_MSR(i)); - printk(BIOS_WARNING, " MC%d_CTL = %08x_%08x\n", - i, mci.ctl.hi, mci.ctl.lo); - mci.cmask = rdmsr(MCA_CTL_MASK_MSR(i)); - printk(BIOS_WARNING, " MC%d_CTL_MASK = %08x_%08x\n", - i, mci.cmask.hi, mci.cmask.lo); + printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n", + i, mci.sts.hi, mci.sts.lo); + mci.addr = rdmsr(MCAX_ADDR_MSR(i)); + printk(BIOS_WARNING, " MC%d_ADDR = %08x_%08x\n", + i, mci.addr.hi, mci.addr.lo); + mci.misc = rdmsr(MCAX_MISC0_MSR(i)); + printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n", + i, mci.misc.hi, mci.misc.lo); + mci.ctl = rdmsr(MCAX_CTL_MSR(i)); + printk(BIOS_WARNING, " MC%d_CTL = %08x_%08x\n", + i, mci.ctl.hi, mci.ctl.lo); + mci.cmask = rdmsr(MCA_CTL_MASK_MSR(i)); + printk(BIOS_WARNING, " MC%d_CTL_MASK = %08x_%08x\n", + i, mci.cmask.hi, mci.cmask.lo); - mci.bank = i; - if (CONFIG(ACPI_BERT) - && mca_valid(mci.sts)) - build_bert_mca_error(&mci); - } + mci.bank = i; + if (CONFIG(ACPI_BERT) + && mca_valid(mci.sts)) + build_bert_mca_error(&mci); } } diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c index 84226ea..6c9662a 100644 --- a/src/soc/amd/picasso/reset.c +++ b/src/soc/amd/picasso/reset.c @@ -7,18 +7,6 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/reset.h> -void set_warm_reset_flag(void) -{ - uint8_t ncp = inb(NCP_ERR); - - outb(NCP_ERR, ncp | NCP_WARM_BOOT); -} - -int is_warm_reset(void) -{ - return !!(inb(NCP_ERR) & NCP_WARM_BOOT); -} - void do_cold_reset(void) { /* De-assert and then assert all PwrGood signals on CF9 reset. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/55059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e6df98ffd5d15ca204c9847a76c19c753726737 Gerrit-Change-Number: 55059 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/... - Add Boot Guard support
by Christian Walter (Code Review) 28 May '21

28 May '21

Attention is currently required from: Christopher Meis, Patrick Rudolph. Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55048 ) Change subject: src/... - Add Boot Guard support ...................................................................... Patch Set 3: (2 comments) File src/mainboard/prodrive/hermes/Kconfig: https://review.coreboot.org/c/coreboot/+/55048/comment/582fb786_dd652194 PS3, Line 77: CBnT CBnT? Not BtG? File src/security/intel/bg/Makefile.inc: https://review.coreboot.org/c/coreboot/+/55048/comment/bb5420d6_acb593d9 PS3, Line 7: PK_HASH_ALG_SHA1:=4 That is not used anywhere? -- To view, visit https://review.coreboot.org/c/coreboot/+/55048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b73a79f51692178e8565803efb2c9caf3096ff9 Gerrit-Change-Number: 55048 Gerrit-PatchSet: 3 Gerrit-Owner: Christopher Meis Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christopher Meis Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 28 May 2021 17:35:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/acpi_bert_storage: change return type of bert_errors_present
by Angel Pons (Code Review) 28 May '21

28 May '21

Attention is currently required from: Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55023 ) Change subject: arch/x86/acpi_bert_storage: change return type of bert_errors_present ...................................................................... Patch Set 3: (1 comment) File src/arch/x86/acpi_bert_storage.c: https://review.coreboot.org/c/coreboot/+/55023/comment/33ece7fb_a401c0fd PS3, Line 38: !! the double negation is not needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/55023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13d6472deeb26ba92d257761df069e32d9b2e5d4 Gerrit-Change-Number: 55023 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 May 2021 17:13:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: acpi: drop unused parameter from acpi_soc_fill_bert
by Angel Pons (Code Review) 28 May '21

28 May '21

Attention is currently required from: Lance Zhao, Tim Wawrzynczak, Patrick Rudolph, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55052 ) Change subject: acpi: drop unused parameter from acpi_soc_fill_bert ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: > the next call (acpi_write_bert) fills the ssdt, so the parameter isn't needed for this function Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/55052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic354824468f016a7857c6990024ae87db6fd00bf Gerrit-Change-Number: 55052 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 May 2021 17:12:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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coreboot-gerrit May 2021