coreboot-gerrit May 2021

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Change in coreboot[master]: arch/x86/acpi_bert_storage: change return type of bert_errors_present
by Angel Pons (Code Review) 28 May '21

28 May '21

Attention is currently required from: Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55023 ) Change subject: arch/x86/acpi_bert_storage: change return type of bert_errors_present ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13d6472deeb26ba92d257761df069e32d9b2e5d4 Gerrit-Change-Number: 55023 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 May 2021 18:32:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/kontron/mal10: Use mainboard_ops driver for GPIO configuration
by Felix Singer (Code Review) 28 May '21

28 May '21

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48143 ) Change subject: mb/kontron/mal10: Use mainboard_ops driver for GPIO configuration ...................................................................... mb/kontron/mal10: Use mainboard_ops driver for GPIO configuration `mainboard_silicon_init_params()` should *only* be used for configuring FSP options which can not be configured anywhere else. Therefore, use the init phase from the mainboard_ops driver for configuring the GPIOs. Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: Ia01091938ac113cb5cf95f046609a1ebf3620806 --- M src/mainboard/kontron/mal10/ramstage.c 1 file changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/48143/1 diff --git a/src/mainboard/kontron/mal10/ramstage.c b/src/mainboard/kontron/mal10/ramstage.c index 48194e6..87ead15 100644 --- a/src/mainboard/kontron/mal10/ramstage.c +++ b/src/mainboard/kontron/mal10/ramstage.c @@ -1,13 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <device/device.h> #include <soc/ramstage.h> #include <carrier/gpio.h> #include <stddef.h> -void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) +static void init_mainboard(void *chip_info) { carrier_gpio_configure(); +} +void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) +{ /* * CPU Power Management Configuration correspond to the BIOS Setup menu settings * in the AMI UEFI v112. @@ -45,3 +49,7 @@ silconfig->IoApicDeviceNumber = 0x1F; silconfig->IoApicFunctionNumber = 0; } + +struct chip_operations mainboard_ops = { + .init = init_mainboard, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/48143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia01091938ac113cb5cf95f046609a1ebf3620806 Gerrit-Change-Number: 48143 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/siemens/{mc_apl2,...,mc_apl6}: Do early UART pad configuration
by Felix Held (Code Review) 28 May '21

28 May '21

Attention is currently required from: Paul Menzel, Mario Scheithauer, Werner Zeh. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54911 ) Change subject: mb/siemens/{mc_apl2,...,mc_apl6}: Do early UART pad configuration ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54911/comment/ac155033_127890bc PS3, Line 9: With commit 405f2296892c10a48db50cd66c2eb364cde0806e the UART pad > Done i consider using short git hashes bad practice, since that massively increases the chance of collisions -- To view, visit https://review.coreboot.org/c/coreboot/+/54911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If78726d9b141e4e7580cca3267f49c1a5b95d7fa Gerrit-Change-Number: 54911 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 28 May 2021 18:28:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: vendorcode/intel/fsp: Update to include post PRQ UPDs for Tiger Lake
by Felix Held (Code Review) 28 May '21

28 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54811 ) Change subject: vendorcode/intel/fsp: Update to include post PRQ UPDs for Tiger Lake ...................................................................... vendorcode/intel/fsp: Update to include post PRQ UPDs for Tiger Lake Update FSP headers for Tiger Lake platform generated based on FSP version 4133 to include post PRQ UPDs. BUG=b:188452018 BRANCH=none TEST=build voxel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I493391294391c1222a1aa5fdb86baad968abf7a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54811 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 2 files changed, 2,138 insertions(+), 201 deletions(-) Approvals: build bot (Jenkins): Verified Srinidhi N Kaushik: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index e84b34f..6210f3c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -248,9 +248,9 @@ **/ UINT8 TrainTrace; -/** Offset 0x012D - Reserved +/** Offset 0x012D **/ - UINT8 Reserved0[3]; + UINT8 UnusedUpdSpace0[3]; /** Offset 0x0130 - Intel Enhanced Debug @deprecated - Not used and has no effect @@ -346,9 +346,17 @@ **/ UINT8 PchTraceHubMemReg1Size; -/** Offset 0x0154 - Reserved +/** Offset 0x0154 - HD Audio DMIC Link Clock Select + Determines DMIC<N> Clock Source. 0: Both, 1: ClkA, 2: ClkB + 0: Both, 1: ClkA, 2: ClkB **/ - UINT8 Reserved1[7]; + UINT8 PchHdaAudioLinkDmicClockSelect[2]; + +/** Offset 0x0156 - PchPreMemRsvd + Reserved for PCH Pre-Mem Reserved + $EN_DIS +**/ + UINT8 PchPreMemRsvd[5]; /** Offset 0x015B - State of X2APIC_OPT_OUT bit in the DMAR table 0=Disable/Clear, 1=Enable/Set @@ -362,9 +370,9 @@ **/ UINT8 DmaControlGuarantee; -/** Offset 0x015D - Reserved +/** Offset 0x015D **/ - UINT8 Reserved2[3]; + UINT8 UnusedUpdSpace1[3]; /** Offset 0x0160 - Base addresses for VT-d function MMIO access Base addresses for VT-d MMIO access per VT-d engine @@ -432,9 +440,9 @@ **/ UINT8 UserBd; -/** Offset 0x018D - Reserved +/** Offset 0x018D **/ - UINT8 Reserved3; + UINT8 UnusedUpdSpace2; /** Offset 0x018E - DDR Frequency Limit Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, @@ -519,9 +527,9 @@ **/ UINT8 RefClk; -/** Offset 0x019F - Reserved +/** Offset 0x019F **/ - UINT8 Reserved4; + UINT8 UnusedUpdSpace3; /** Offset 0x01A0 - Memory Voltage DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM @@ -550,9 +558,9 @@ **/ UINT8 tCWL; -/** Offset 0x01A5 - Reserved +/** Offset 0x01A5 **/ - UINT8 Reserved5; + UINT8 UnusedUpdSpace4; /** Offset 0x01A6 - tFAW Min Four Activate Window Delay Time, 0: AUTO, max: 63. Only used if FspmUpd->FspmConfig.SpdProfileSelected @@ -572,9 +580,9 @@ **/ UINT8 tRCDtRP; -/** Offset 0x01AB - Reserved +/** Offset 0x01AB **/ - UINT8 Reserved6; + UINT8 UnusedUpdSpace5; /** Offset 0x01AC - tREFI Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected @@ -653,9 +661,20 @@ **/ UINT8 CpuTraceHubMemReg1Size; -/** Offset 0x01BA - Reserved +/** Offset 0x01BA - SAGV Gear Ratio + Gear Selection for SAGV points. 0 - Auto, 1-1 Gear 1, 2-Gear 2 **/ - UINT8 Reserved7[13]; + UINT8 SaGvGear[4]; + +/** Offset 0x01BE - SAGV Frequency + SAGV Frequency per point in Mhz. 0 for Auto and a ratio of 133/100MHz: 1333/1300. +**/ + UINT16 SaGvFreq[4]; + +/** Offset 0x01C6 - SAGV Disabled Gear Ratio + Gear Selection for SAGV Disabled. 0 - Auto, 1-1 Gear 1, 2-Gear 2 +**/ + UINT8 GearRatio; /** Offset 0x01C7 - HECI Timeouts 0: Disable, 1: Enable (Default) timeout check for HECI @@ -716,9 +735,9 @@ **/ UINT8 PsmiRegionSize; -/** Offset 0x01DD - Reserved +/** Offset 0x01DD **/ - UINT8 Reserved8[3]; + UINT8 UnusedUpdSpace6[3]; /** Offset 0x01E0 - Temporary MMIO address for GMADR Obsolete field now and it has been extended to 64 bit address, used GmAdr64 @@ -739,9 +758,14 @@ **/ UINT16 GttSize; -/** Offset 0x01EA - Reserved +/** Offset 0x01EA **/ - UINT8 Reserved9[98]; + UINT8 UnusedUpdSpace7[2]; + +/** Offset 0x01EC - Hybrid Graphics GPIO information for PEG 0 + Hybrid Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs +**/ + UINT32 CpuPcie0Rtd3Gpio[24]; /** Offset 0x024C - Enable/Disable MRC TXT dependency When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): @@ -824,9 +848,9 @@ **/ UINT8 ImguClkOutEn[6]; -/** Offset 0x0263 - Reserved +/** Offset 0x0263 **/ - UINT8 Reserved10; + UINT8 UnusedUpdSpace8; /** Offset 0x0264 - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 @@ -834,9 +858,12 @@ **/ UINT32 CpuPcieRpEnableMask; -/** Offset 0x0268 - Reserved +/** Offset 0x0268 - Assertion on Link Down GPIOs + GPIO Assertion on Link Down. Disabled(0x0)(Default): Disable assertion on Link Down + GPIOs, Enabled(0x1): Enable assertion on Link Down GPIOs + 0:Disable, 1:Enable **/ - UINT8 Reserved11; + UINT8 CpuPcieRpLinkDownGpios; /** Offset 0x0269 - RpClockReqMsgEnable **/ @@ -852,9 +879,17 @@ **/ UINT8 GtPsmiSupport; -/** Offset 0x026F - Reserved +/** Offset 0x026F - Selection of DiSM Region Size + DiSM Size to be allocated for 2LM Sku Default is 0 + 0:0GB, 1:1GB, 2:2GB, 3:3GB, 4:4GB, 5:5GB, 6:6GB, 7:7GB **/ - UINT8 Reserved12[2]; + UINT8 DismSize; + +/** Offset 0x0270 - Enable Display memory map programming for DFD Restore + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DfdRestoreEnable; /** Offset 0x0271 - Program GPIOs for LFP on DDI port-A device 0=Disabled,1(Default)=eDP, 2=MIPI DSI @@ -952,9 +987,80 @@ **/ UINT8 DdiPort4Ddc; -/** Offset 0x0281 - Reserved +/** Offset 0x0281 - Enable Gt CLOS + 0(Default)=Disable, 1=Enable + $EN_DIS **/ - UINT8 Reserved13[121]; + UINT8 GtClosEnable; + +/** Offset 0x0282 +**/ + UINT8 UnusedUpdSpace9[6]; + +/** Offset 0x0288 - Temporary MMIO address for GMADR + The reference code will use this as Temporary MMIO address space to access GMADR + Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to + (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress + - 0x1) (Where ApertureSize = 256MB, 512MB, 1024MB and 2048MB) +**/ + UINT64 GmAdr64; + +/** Offset 0x0290 - Hybrid Graphics Slot Selection + PEG or PCH Slot Selection for Hybrid Graphics +**/ + UINT8 HgSlot; + +/** Offset 0x0291 - DMI ASPM Configuration:{Combo + Set ASPM Configuration + 0:Disabled, 1:L0s, 2:L1, 3:L1L0s +**/ + UINT8 DmiAspm; + +/** Offset 0x0292 - DMI ASPM Control Configuration:{Combo + Set ASPM Control configuration + 0:Disabled, 1:L0s, 2:L1, 3:L1L0s +**/ + UINT8 DmiAspmCtrl; + +/** Offset 0x0293 - DMI ASPM L1 exit Latency + Range: 0-7, 4 is default L1 exit Latency +**/ + UINT8 DmiAspmL1ExitLatency; + +/** Offset 0x0294 - Per-core HT Disable + Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, + 0 - is ignored. Input is in HEX and each bit maps to a logical core. Ex. A value + of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have + HT enabled. Range is 0 - 0x7F for max 8 cores. You can only disable up to MAX_CORE_COUNT - 1. +**/ + UINT16 PerCoreHtDisable; + +/** Offset 0x0296 - DEKEL CDR Relock + Enable/Disable CDR Relock. 0: Disable(Default); 1: Enable +**/ + UINT8 CpuPcieRpCdrRelock[4]; + +/** Offset 0x029A - Realtime Memory OverClock + Disable/Enables Realtime Memory OverClock + $EN_DIS +**/ + UINT8 RealtimeMemoryOC; + +/** Offset 0x029B - Xl1el + Enable/Disable NewFom for DEKEL Programming. 0: Disable(Default); 1: Enable +**/ + UINT8 CpuPcieNewFom[4]; + +/** Offset 0x029F - Xl1el + Enable/Disable NewFomDisable. 0: Disable(Default); 1: Enable +**/ + UINT8 CpuPcieIotgMode[4]; + +/** Offset 0x02A3 - SaPreMemProductionRsvd + Reserved for SA Pre-Mem Production + $EN_DIS +**/ + UINT8 SaPreMemProductionRsvd[87]; /** Offset 0x02FA - DMI Max Link Speed Auto (0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): @@ -1203,9 +1309,15 @@ **/ UINT8 CpuCrashLogEnable; -/** Offset 0x0340 - Reserved +/** Offset 0x0340 - ElixirSpringsPatchAddr + DEPRECATED **/ - UINT8 Reserved14[8]; + UINT32 ElixirSpringsPatchAddr; + +/** Offset 0x0344 - ElixirSpringsPatchSize + DEPRECATED +**/ + UINT32 ElixirSpringsPatchSize; /** Offset 0x0348 - CPU Run Control Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; 2: @@ -1242,9 +1354,9 @@ **/ UINT8 Txt; -/** Offset 0x034E - Reserved +/** Offset 0x034E **/ - UINT8 Reserved15[2]; + UINT8 UnusedUpdSpace10[2]; /** Offset 0x0350 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable @@ -1312,9 +1424,11 @@ **/ UINT8 ConfigTdpLevel; -/** Offset 0x038A - Reserved +/** Offset 0x038A - ReservedSecurityPreMem + Reserved for Security Pre-Mem + $EN_DIS **/ - UINT8 Reserved16[5]; + UINT8 ReservedSecurityPreMem[5]; /** Offset 0x038F - Enable PCH HSIO PCIE Rx Set Ctle Enable PCH PCIe Gen 3 Set CTLE Value. @@ -1499,9 +1613,9 @@ **/ UINT8 PchNumRsvdSmbusAddresses; -/** Offset 0x0573 - Reserved +/** Offset 0x0573 **/ - UINT8 Reserved17; + UINT8 UnusedUpdSpace11; /** Offset 0x0574 - SMBUS Base Address SMBUS Base Address (IO space). @@ -1525,9 +1639,14 @@ **/ UINT8 PcieClkSrcClkReq[16]; -/** Offset 0x0597 - Reserved +/** Offset 0x0597 **/ - UINT8 Reserved18[5]; + UINT8 UnusedUpdSpace12; + +/** Offset 0x0598 - Point of RsvdSmbusAddressTable + Array of addresses reserved for non-ARP-capable SMBus devices. +**/ + UINT32 RsvdSmbusAddressTablePtr; /** Offset 0x059C - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 @@ -1554,9 +1673,9 @@ **/ UINT8 SerialIoUartDebugAutoFlow; -/** Offset 0x05A3 - Reserved +/** Offset 0x05A3 **/ - UINT8 Reserved19; + UINT8 UnusedUpdSpace13; /** Offset 0x05A4 - Serial Io Uart Debug BaudRate Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, @@ -1582,9 +1701,15 @@ **/ UINT8 SerialIoUartDebugDataBits; -/** Offset 0x05AB - Reserved +/** Offset 0x05AB **/ - UINT8 Reserved20[5]; + UINT8 UnusedUpdSpace14; + +/** Offset 0x05AC - Serial Io Uart Debug Mmio Base + Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode + = SerialIoUartPci. +**/ + UINT32 SerialIoUartDebugMmioBase; /** Offset 0x05B0 - ISA Serial Base selection Select ISA Serial Base address. Default is 0x3F8. @@ -1871,9 +1996,43 @@ **/ UINT8 EccSupport; -/** Offset 0x05E0 - Reserved +/** Offset 0x05E0 - Ibecc + In-Band ECC Support + $EN_DIS **/ - UINT8 Reserved21[44]; + UINT8 Ibecc; + +/** Offset 0x05E1 - IbeccParity + In-Band ECC Parity Control + $EN_DIS +**/ + UINT8 IbeccParity; + +/** Offset 0x05E2 - IbeccOperationMode + In-Band ECC Operation Mode + 0:Protect base on address range, 1: Non-protected, 2: All protected +**/ + UINT8 IbeccOperationMode; + +/** Offset 0x05E3 - IbeccProtectedRegionEnable + In-Band ECC Protected Region Enable + $EN_DIS +**/ + UINT8 IbeccProtectedRegionEnable[8]; + +/** Offset 0x05EB +**/ + UINT8 UnusedUpdSpace15[1]; + +/** Offset 0x05EC - IbeccProtectedRegionBases + IBECC Protected Region Bases +**/ + UINT16 IbeccProtectedRegionBase[8]; + +/** Offset 0x05FC - IbeccProtectedRegionMasks + IBECC Protected Region Masks +**/ + UINT16 IbeccProtectedRegionMask[8]; /** Offset 0x060C - Memory Remap Enables/Disable Memory Remap @@ -1948,9 +2107,17 @@ **/ UINT8 ExitOnFailure; -/** Offset 0x0618 - Reserved +/** Offset 0x0618 - New Features 1 - MRC + New Feature Enabling 1, 0:Disable, 1:Enable + 0:Disable, 1:Enable **/ - UINT8 Reserved22[2]; + UINT8 NewFeatureEnable1; + +/** Offset 0x0619 - New Features 2 - MRC + New Feature Enabling 2, 0:Disable, 1:Enable + 0:Disable, 1:Enable +**/ + UINT8 NewFeatureEnable2; /** Offset 0x061A - Duty Cycle Correction Training Enable/Disable Duty Cycle Correction Training @@ -2000,9 +2167,35 @@ **/ UINT8 TXTCODQS; -/** Offset 0x0622 - Reserved +/** Offset 0x0622 - CMD/CTL Drive Strength Up/Dn 2D + Enable/Disable CMD/CTL Drive Strength Up/Dn 2D + $EN_DIS **/ - UINT8 Reserved23[5]; + UINT8 CMDDRUD; + +/** Offset 0x0623 - VccDLL Bypass Training + Enable/Disable VccDLL Bypass Training + $EN_DIS +**/ + UINT8 VCCDLLBP; + +/** Offset 0x0624 - PanicVttDnLp Training + Enable/Disable PanicVttDnLp Training + $EN_DIS +**/ + UINT8 PVTTDNLP; + +/** Offset 0x0625 - Read Vref Decap Training* + Enable/Disable Read Vref Decap Training* + $EN_DIS +**/ + UINT8 RDVREFDC; + +/** Offset 0x0626 - Vddq Training + Enable/Disable Vddq Training + $EN_DIS +**/ + UINT8 VDDQT; /** Offset 0x0627 - Rank Margin Tool Per Bit Enable/Disable Rank Margin Tool Per Bit @@ -2010,9 +2203,15 @@ **/ UINT8 RMTBIT; -/** Offset 0x0628 - Reserved +/** Offset 0x0628 - Override Performance Downgrade for Mixed Memory + Disable/Enables Override Performance Downgrade for Mixed Memory + $EN_DIS **/ - UINT8 Reserved24[2]; + UINT8 OverrideDowngradeForMixedMemory; + +/** Offset 0x0629 +**/ + UINT8 Reserved2[1]; /** Offset 0x062A - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP @@ -2033,9 +2232,9 @@ **/ UINT8 ChHashInterleaveBit; -/** Offset 0x062D - Reserved +/** Offset 0x062D **/ - UINT8 Reserved25; + UINT8 UnusedUpdSpace16; /** Offset 0x062E - Ch Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to @@ -2066,9 +2265,205 @@ **/ UINT8 RhActProbability; -/** Offset 0x0639 - Reserved +/** Offset 0x0639 - Idle Energy Mc0Ch0Dimm0 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) **/ - UINT8 Reserved26[40]; + UINT8 IdleEnergyMc0Ch0Dimm0; + +/** Offset 0x063A - Idle Energy Mc0Ch0Dimm1 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc0Ch0Dimm1; + +/** Offset 0x063B - Idle Energy Mc0Ch1Dimm0 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc0Ch1Dimm0; + +/** Offset 0x063C - Idle Energy Mc0Ch1Dimm1 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc0Ch1Dimm1; + +/** Offset 0x063D - Idle Energy Mc1Ch0Dimm0 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc1Ch0Dimm0; + +/** Offset 0x063E - Idle Energy Mc1Ch0Dimm1 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc1Ch0Dimm1; + +/** Offset 0x063F - Idle Energy Mc1Ch1Dimm0 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc1Ch1Dimm0; + +/** Offset 0x0640 - Idle Energy Mc1Ch1Dimm1 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyMc1Ch1Dimm1; + +/** Offset 0x0641 - PowerDown Energy Mc0Ch0Dimm0 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc0Ch0Dimm0; + +/** Offset 0x0642 - PowerDown Energy Mc0Ch0Dimm1 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc0Ch0Dimm1; + +/** Offset 0x0643 - PowerDown Energy Mc0Ch1Dimm0 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc0Ch1Dimm0; + +/** Offset 0x0644 - PowerDown Energy Mc0Ch1Dimm1 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc0Ch1Dimm1; + +/** Offset 0x0645 - PowerDown Energy Mc1Ch0Dimm0 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc1Ch0Dimm0; + +/** Offset 0x0646 - PowerDown Energy Mc1Ch0Dimm1 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc1Ch0Dimm1; + +/** Offset 0x0647 - PowerDown Energy Mc1Ch1Dimm0 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc1Ch1Dimm0; + +/** Offset 0x0648 - PowerDown Energy Mc1Ch1Dimm1 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) +**/ + UINT8 PdEnergyMc1Ch1Dimm1; + +/** Offset 0x0649 - Activate Energy Mc0Ch0Dimm0 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc0Ch0Dimm0; + +/** Offset 0x064A - Activate Energy Mc0Ch0Dimm1 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc0Ch0Dimm1; + +/** Offset 0x064B - Activate Energy Mc0Ch1Dimm0 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc0Ch1Dimm0; + +/** Offset 0x064C - Activate Energy Mc0Ch1Dimm1 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc0Ch1Dimm1; + +/** Offset 0x064D - Activate Energy Mc1Ch0Dimm0 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc1Ch0Dimm0; + +/** Offset 0x064E - Activate Energy Mc1Ch0Dimm1 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc1Ch0Dimm1; + +/** Offset 0x064F - Activate Energy Mc1Ch1Dimm0 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc1Ch1Dimm0; + +/** Offset 0x0650 - Activate Energy Mc1Ch1Dimm1 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyMc1Ch1Dimm1; + +/** Offset 0x0651 - Read Energy Mc0Ch0Dimm0 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc0Ch0Dimm0; + +/** Offset 0x0652 - Read Energy Mc0Ch0Dimm1 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc0Ch0Dimm1; + +/** Offset 0x0653 - Read Energy Mc0Ch1Dimm0 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc0Ch1Dimm0; + +/** Offset 0x0654 - Read Energy Mc0Ch1Dimm1 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc0Ch1Dimm1; + +/** Offset 0x0655 - Read Energy Mc1Ch0Dimm0 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc1Ch0Dimm0; + +/** Offset 0x0656 - Read Energy Mc1Ch0Dimm1 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc1Ch0Dimm1; + +/** Offset 0x0657 - Read Energy Mc1Ch1Dimm0 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc1Ch1Dimm0; + +/** Offset 0x0658 - Read Energy Mc1Ch1Dimm1 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyMc1Ch1Dimm1; + +/** Offset 0x0659 - Write Energy Mc0Ch0Dimm0 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc0Ch0Dimm0; + +/** Offset 0x065A - Write Energy Mc0Ch0Dimm1 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc0Ch0Dimm1; + +/** Offset 0x065B - Write Energy Mc0Ch1Dimm0 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc0Ch1Dimm0; + +/** Offset 0x065C - Write Energy Mc0Ch1Dimm1 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc0Ch1Dimm1; + +/** Offset 0x065D - Write Energy Mc1Ch0Dimm0 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc1Ch0Dimm0; + +/** Offset 0x065E - Write Energy Mc1Ch0Dimm1 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc1Ch0Dimm1; + +/** Offset 0x065F - Write Energy Mc1Ch1Dimm0 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc1Ch1Dimm0; + +/** Offset 0x0660 - Write Energy Mc1Ch1Dimm1 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyMc1Ch1Dimm1; /** Offset 0x0661 - Throttler CKEMin Timer Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). @@ -2124,9 +2519,11 @@ **/ UINT8 UserBudgetEnable; -/** Offset 0x066A - Reserved +/** Offset 0x066A - Power Down Mode + This option controls command bus tristating during idle periods + 0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto **/ - UINT8 Reserved27; + UINT8 PowerDownMode; /** Offset 0x066B - Pwr Down Idle Timer The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means @@ -2134,9 +2531,11 @@ **/ UINT8 PwdwnIdleCounter; -/** Offset 0x066C - Reserved +/** Offset 0x066C - Page Close Idle Timeout + This option controls Page Close Idle Timeout + 0:Enabled, 1:Disabled **/ - UINT8 Reserved28; + UINT8 DisPgCloseIdleTimeout; /** Offset 0x066D - Bitmask of ranks that have CA bus terminated Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, @@ -2188,9 +2587,9 @@ **/ UINT8 UsbTcPortEnPreMem; -/** Offset 0x0675 - Reserved +/** Offset 0x0675 **/ - UINT8 Reserved29; + UINT8 UnusedUpdSpace17; /** Offset 0x0676 - Post Code Output Port This option configures Post Code Output Port @@ -2208,9 +2607,22 @@ **/ UINT8 CridEnable; -/** Offset 0x067A - Reserved +/** Offset 0x067A - WRC Feature + Enable/Disable WRC (Write Cache) feature of IOP. When feature is enabled, supports + IO devices allocating onto the ring and into LLC. WRC is fused on by default. + $EN_DIS **/ - UINT8 Reserved30[18]; + UINT8 WrcFeatureEnable; + +/** Offset 0x067B +**/ + UINT8 UnusedUpdSpace18[1]; + +/** Offset 0x067C - BCLK RFI Frequency + Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz 0 - No + RFI Tuning. Range is 98Mhz-100Mhz. +**/ + UINT32 BclkRfiFreq[4]; /** Offset 0x068C - Size of PCIe IMR. Size of PCIe IMR in megabytes @@ -2223,9 +2635,18 @@ **/ UINT8 PcieImrEnabled; -/** Offset 0x068F - Reserved +/** Offset 0x068F - Enable PCIe IMR + 1: PCH PCIE, 2: SA PCIE. If PCIeImrEnabled is TRUE then this will use to select + the Root port location from PCH PCIe or SA PCIe + $EN_DIS **/ - UINT8 Reserved31[2]; + UINT8 PcieImrRpLocation; + +/** Offset 0x0690 - Root port number for IMR. + Root port number for IMR.If PCieImrRpLocation is PCH PCIe then select root port + from 0 to 23 and if it is SA PCIe then select root port from 0 to 3 +**/ + UINT8 PcieImrRpSelection; /** Offset 0x0691 - SerialDebugMrcLevel MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, @@ -2236,9 +2657,95 @@ **/ UINT8 SerialDebugMrcLevel; -/** Offset 0x0692 - Reserved +/** Offset 0x0692 - Mem Boot Mode + 0: BOOT_MODE_1LM(Default), 1: BOOT_MODE_2LM, 2: BOOT_MODE_PROVISION + 0: BOOT_MODE_1LM, 1: BOOT_MODE_2LM, 2: BOOT_MODE_PROVISION **/ - UINT8 Reserved32[32]; + UINT8 MemBootMode; + +/** Offset 0x0693 - PCIe ASPM programming will happen in relation to the Oprom + This option is specifically needed for ASPM configuration in 2LM feature + 0:Disabled, 1:L0, 2:L1, 3:L0L1, 4:Auto +**/ + UINT8 Peg3Aspm; + +/** Offset 0x0694 - MFVC WRR VC Arbitration + 0: DEFAULT_PHASES(Default), 1: PROGRAM_128PHASES + 0: DEFAULT_PHASES, 1: PROGRAM_128PHASES +**/ + UINT8 MfvcWrrArb; + +/** Offset 0x0695 - BZM Support + 1: enable, 0: disable(Default), Enable/disable setting for Boot-time Zero Memory support + $EN_DIS +**/ + UINT8 BzmSupport; + +/** Offset 0x0696 - VcId_7_0 values + Select VC ID for arbitration +**/ + UINT8 VcId_7_0[16]; + +/** Offset 0x06A6 - Set Hw Parameters enable/disable + 1: enable, 0: disable, Enable/disable setting of HW parameters + $EN_DIS +**/ + UINT8 SetHwParameters; + +/** Offset 0x06A7 +**/ + UINT8 UnusedUpdSpace19; + +/** Offset 0x06A8 - LTR L1.2 Threshold Value + LTR L1.2 Threshold Value +**/ + UINT16 Ltr_L1D2_ThVal; + +/** Offset 0x06AA - LTR L1.2 Threshold Scale + LTR L1.2 Threshold Scale +**/ + UINT8 Ltr_L1D2_ThScale; + +/** Offset 0x06AB - system power state + system power state indicates the platform power state +**/ + UINT8 SysPwrState; + +/** Offset 0x06AC - Media Death Notification Enable/Disable + 1: enable, 0: disable, Enable/disable for Media Death Notification + $EN_DIS +**/ + UINT8 MediaDeathNotification; + +/** Offset 0x06AD - Health Log Notification Enable/Disable + 1: enable, 0: disable, Enable/disable for Health Log Notification + $EN_DIS +**/ + UINT8 HealthLogNotification; + +/** Offset 0x06AE - Temp crosses below TempThrottle Notification Enable/Disable + 1: enable, 0: disable, Enable/disable for Temp crosses below TempThrottle Notification + $EN_DIS +**/ + UINT8 TempBelowThrottleNotification; + +/** Offset 0x06AF - Temp crosses above TempThrottle Notification Enable/Disable + 1: enable, 0: disable, Enable/disable for Temp crosses above TempThrottle Notification + $EN_DIS +**/ + UINT8 TempAboveThrottleNotification; + +/** Offset 0x06B0 - Missing Commit Bit Notification Enable/Disable + 1: enable, 0: disable, Enable/disable for Missing Commit Bit Notification + $EN_DIS +**/ + UINT8 MissingCommitBitNotification; + +/** Offset 0x06B1 - NVMeHoldDisableBit + 1: enable, 0: disable, Enable/disable for NVMeHoldDisableBit + $EN_DIS +**/ + UINT8 NVMeHoldDisableBit; /** Offset 0x06B2 - Ddr4OneDpc DDR4 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only, @@ -2247,9 +2754,42 @@ **/ UINT8 Ddr4OneDpc; -/** Offset 0x06B3 - Reserved +/** Offset 0x06B3 - Ch Hash Override POR settings + Enable/Disable Override Channel Hash Support POR values + $EN_DIS **/ - UINT8 Reserved33[9]; + UINT8 ChHashOverride; + +/** Offset 0x06B4 - PDA Enumeration + Enables/Disable PDA Enumeration + $EN_DIS +**/ + UINT8 PDA; + +/** Offset 0x06B5 - DPin Policy + Set DPin Policy. Internal Only:All display ports are for internal only. External + First:All display ports are for external only, if there is no External DP-In presence + presents then IOM will use all ports internal only + 0: Internal Only, 1: External First +**/ + UINT8 DpInExternalEn; + +/** Offset 0x06B6 - DPin External Ports Number + Total number of External Gfx DpIn Port present on Board. Currently hardware wise + max 0x04 DpIn port supported, however DpIn module can handle upto 0x08 DpIn ports +**/ + UINT8 NumberOfDpInPort; + +/** Offset 0x06B7 - DPin External Port Connect Map + Indicate which Dp-In port connection detected. Each BIT stand for one Dp-In port. +**/ + UINT8 DpInPortConnectMap; + +/** Offset 0x06B8 - Command Pins Mapping + BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller + 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending. +**/ + UINT8 Lp5CccConfig[4]; /** Offset 0x06BC - Command Pins Mirrored BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller @@ -2257,9 +2797,28 @@ **/ UINT32 CmdMirror[1]; -/** Offset 0x06C0 - Reserved +/** Offset 0x06C0 - CPU BCLK SSC Enable + Enable/Disable CPU BCLK Spread Spectrum. Default is Enabled. + $EN_DIS **/ - UINT8 Reserved34[5]; + UINT8 CpuBclkSpread; + +/** Offset 0x06C1 - McParity + CMI/MC Parity Control + $EN_DIS +**/ + UINT8 McParity; + +/** Offset 0x06C2 - Vddq Voltage Override + # is multiple of 1mV where 0 means Auto. +**/ + UINT16 VddqVoltageOverride; + +/** Offset 0x06C4 - Extended Bank Hashing + Eanble/Disable ExtendedBankHashing + $EN_DIS +**/ + UINT8 ExtendedBankHashing; /** Offset 0x06C5 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -2287,9 +2846,13 @@ **/ UINT8 LockPTMregs; -/** Offset 0x06C9 - Reserved +/** Offset 0x06C9 - Rsvd + Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): + Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE + peak values unmodified + $EN_DIS **/ - UINT8 Reserved35; + UINT8 PegGen3Rsvd; /** Offset 0x06CA - Panel Power Enable Control for enabling/disabling VDD force bit (Required only for early enabling of @@ -2304,9 +2867,153 @@ **/ UINT8 BdatTestType; -/** Offset 0x06CC - Reserved +/** Offset 0x06CC - PMR Size + Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot **/ - UINT8 Reserved36[98]; + UINT32 DmaBufferSize; + +/** Offset 0x06D0 - VT-d/IOMMU Boot Policy + BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS +**/ + UINT8 PreBootDmaMask; + +/** Offset 0x06D1 - Enable/Disable DMI GEN3 Hardware Eq + Enable/Disable DMI GEN3 Hardware Eq. Disabled(0x0): Disable Hardware Eq, Enabled(0x1)(Default): + Enable EQ Phase1 Static Presets Programming + $EN_DIS +**/ + UINT8 DmiHweq; + +/** Offset 0x06D2 - Enable/Disable CPU DMI GEN3 Phase 23 Bypass + CPU DMI GEN3 Phase 23 Bypass. Disabled(0x0)(Default): Disable Phase 23 Bypass, Enabled(0x1): + Enable Phase 23 Bypass + $EN_DIS +**/ + UINT8 Gen3EqPhase23Bypass; + +/** Offset 0x06D3 - Enable/Disable CPU DMI GEN3 Phase 3 Bypass + CPU DMI GEN3 Phase 3 Bypass. Disabled(0x0)(Default): Disable Phase 3 Bypass, Enabled(0x1): + Enable Phase 3 Bypass + $EN_DIS +**/ + UINT8 Gen3EqPhase3Bypass; + +/** Offset 0x06D4 - Enable/Disable CPU DMI Gen3 EQ Local Transmitter Coefficient Override Enable + Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0)(Default): + Disable Local Transmitter Coefficient Override, Enabled(0x1): Enable Local Transmitter + Coefficient Override + $EN_DIS +**/ + UINT8 Gen3LtcoEnable; + +/** Offset 0x06D5 - Enable/Disable CPU DMI Gen3 EQ Remote Transmitter Coefficient/Preset Override Enable + Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0): Disable Remote + Transmitter Coefficient/Preset Override, Enabled(0x1)(Default): Enable Remote + Transmitter Coefficient/Preset Override + $EN_DIS +**/ + UINT8 Gen3RtcoRtpoEnable; + +/** Offset 0x06D6 - DMI Gen3 Transmitter Pre-Cursor Coefficient + Used for programming DMI Gen3 Transmitter Pre-Cursor Coefficient . Range: 0-10, + 2 is default for each lane +**/ + UINT8 DmiGen3Ltcpre[8]; + +/** Offset 0x06DE - DMI Gen3 Transmitter Post-Cursor Coefficient + Used for programming Transmitter Post-Cursor Coefficient. Range: 0-9, 2 is default + for each lane +**/ + UINT8 DmiGen3Ltcpo[8]; + +/** Offset 0x06E6 - PCIE Hw Eq Gen3 CoeffList Cm + CPU_PCIE_EQ_PARAM. Coefficient C-1. +**/ + UINT8 CpuDmiHwEqGen3CoeffListCm[8]; + +/** Offset 0x06EE - PCIE Hw Eq Gen3 CoeffList Cp + CPU_PCIE_EQ_PARAM. Coefficient C+1. +**/ + UINT8 CpuDmiHwEqGen3CoeffListCp[8]; + +/** Offset 0x06F6 - Enable/Disable DMI GEN3 DmiGen3DsPresetEnable + Enable/Disable DMI GEN3 DmiGen3DsPreset. Auto(0x0)(Default): DmiGen3DsPresetEnable, + Manual(0x1): Enable DmiGen3DsPresetEnable + $EN_DIS +**/ + UINT8 DmiGen3DsPresetEnable; + +/** Offset 0x06F7 - DMI Gen3 Root port preset Rx values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-10, 1 is default + for each lane +**/ + UINT8 DmiGen3DsPortRxPreset[8]; + +/** Offset 0x06FF - DMI Gen3 Root port preset Tx values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default + for each lane +**/ + UINT8 DmiGen3DsPortTxPreset[8]; + +/** Offset 0x0707 - Program DMI GEN3 Extended number of VC + (DEPRECATED) +**/ + UINT8 DmiGen3MultiVC; + +/** Offset 0x0708 - Enable/Disable DMI GEN3 DmiGen3Vc1Control + (DEPRECATED) + $EN_DIS +**/ + UINT8 DmiGen3Vc1Control; + +/** Offset 0x0709 - Enable/Disable DMI GEN3 DmiGen3VcMControl + (DEPRECATED) + $EN_DIS +**/ + UINT8 DmiGen3VcMControl; + +/** Offset 0x070A - DMI Secure Register Lock:{Combo + (DEPRECATED) + 0:Disable, 1:Enable +**/ + UINT8 DmiSrl; + +/** Offset 0x070B - DMI Scramble Enable:{Combo + (DEPRECATED) + 0:Disable, 1:Enable +**/ + UINT8 DmiScramble; + +/** Offset 0x070C - DMI Max Payload Size:{Combo + (DEPRECATED) + 0:Auto, 1:128 TLP, 2:256 TLP +**/ + UINT8 DmiMaxPayload; + +/** Offset 0x070D - DPin Dynamic Switch Policy + Dynamic one-time switch from iGFx to dGFx after boot to OS + 0: Disble, 1: Enable +**/ + UINT8 DPinDynamicSwitch; + +/** Offset 0x070E - Delay before sending commn + Delay before sending dynamic one-time switch cmd to IOM, ACPI BIOS consumes this + value and proceed delay when _DSM is invoked: 0=Minimal, 5000=Maximum, default + is 0 second +**/ + UINT16 DPinDynamicSwitchDelay0; + +/** Offset 0x0710 - Delay before IOM de-assert HPD + Delay before IOM de-assert HPD, ACPI BIOS passes this value to IOM when sending + dynamic one-time switch command: 1000=Minimal, 5000=Maximum, default is 1000 = 1 second +**/ + UINT16 DPinDynamicSwitchDelay1; + +/** Offset 0x0712 - SaPreMemTestRsvd + Reserved for SA Pre-Mem Test + $EN_DIS +**/ + UINT8 SaPreMemTestRsvd[28]; /** Offset 0x072E - TotalFlashSize Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable @@ -2320,9 +3027,11 @@ **/ UINT16 BiosSize; -/** Offset 0x0732 - Reserved +/** Offset 0x0732 - SecurityTestRsvd + Reserved for SA Pre-Mem Test + $EN_DIS **/ - UINT8 Reserved37[12]; + UINT8 SecurityTestRsvd[12]; /** Offset 0x073E - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. @@ -2362,18 +3071,26 @@ **/ UINT8 PchHdaAudioLinkHdaEnable; -/** Offset 0x0744 - Reserved +/** Offset 0x0744 - Enable HDA SDI lanes + Enable/disable HDA SDI lanes. **/ - UINT8 Reserved38[3]; + UINT8 PchHdaSdiEnable[2]; + +/** Offset 0x0746 - HDA Power/Clock Gating (PGD/CGD) + Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1: + FORCE_ENABLE, 2: FORCE_DISABLE. + 0: POR, 1: Force Enable, 2: Force Disable +**/ + UINT8 PchHdaTestPowerClockGating; /** Offset 0x0747 - Enable HD Audio DMIC_N Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. **/ UINT8 PchHdaAudioLinkDmicEnable[2]; -/** Offset 0x0749 - Reserved +/** Offset 0x0749 **/ - UINT8 Reserved39[3]; + UINT8 UnusedUpdSpace20[3]; /** Offset 0x074C - DMIC<N> ClkA Pin Muxing (N - DMIC number) Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_* @@ -2391,9 +3108,9 @@ **/ UINT8 PchHdaDspEnable; -/** Offset 0x075D - Reserved +/** Offset 0x075D **/ - UINT8 Reserved40[3]; + UINT8 UnusedUpdSpace21[3]; /** Offset 0x0760 - DMIC<N> Data Pin Muxing Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* @@ -2472,9 +3189,20 @@ **/ UINT8 KtDeviceEnable; -/** Offset 0x077C - Reserved +/** Offset 0x077C - Hybrid Graphics GPIO information for PEG 1 + Hybrid Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs **/ - UINT8 Reserved41[288]; + UINT32 CpuPcie1Rtd3Gpio[24]; + +/** Offset 0x07DC - Hybrid Graphics GPIO information for PEG 2 + Hybrid Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs +**/ + UINT32 CpuPcie2Rtd3Gpio[24]; + +/** Offset 0x083C - Hybrid Graphics GPIO information for PEG 3 + Hybrid Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs +**/ + UINT32 CpuPcie3Rtd3Gpio[24]; /** Offset 0x089C - Skip CPU replacement check Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check @@ -2482,9 +3210,11 @@ **/ UINT8 SkipCpuReplacementCheck; -/** Offset 0x089D - Reserved +/** Offset 0x089D - PCI Express Dekel Workaround + Select the 1 to 9 for Dekel registers endpoint programming: 1=Minimal, 9=Maximum, + default is 2 **/ - UINT8 Reserved42; + UINT8 CpuPcieRpDekelSquelchWa; /** Offset 0x089E - Serial Io Uart Debug Mode Select SerialIo Uart Controller mode @@ -2493,9 +3223,157 @@ **/ UINT8 SerialIoUartDebugMode; -/** Offset 0x089F - Reserved +/** Offset 0x089F **/ - UINT8 Reserved43[124]; + UINT8 UnusedUpdSpace22; + +/** Offset 0x08A0 - SerialIoUartDebugRxPinMux - FSPT + Select RX pin muxing for SerialIo UART used for debug +**/ + UINT32 SerialIoUartDebugRxPinMux; + +/** Offset 0x08A4 - SerialIoUartDebugTxPinMux - FSPM + Select TX pin muxing for SerialIo UART used for debug +**/ + UINT32 SerialIoUartDebugTxPinMux; + +/** Offset 0x08A8 - SerialIoUartDebugRtsPinMux - FSPM + Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* + for possible values. +**/ + UINT32 SerialIoUartDebugRtsPinMux; + +/** Offset 0x08AC - SerialIoUartDebugCtsPinMux - FSPM + Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* + for possible values. +**/ + UINT32 SerialIoUartDebugCtsPinMux; + +/** Offset 0x08B0 - Avx2 Voltage Guardband Scaling Factor + AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in + 1/100 units, where a value of 125 would apply a 1.25 scale factor. +**/ + UINT8 Avx2VoltageScaleFactor; + +/** Offset 0x08B1 - Avx512 Voltage Guardband Scaling Factor + AVX512 Voltage Guardband Scale factor applied to AVX512 workloads. Range is 0-200 + in 1/100 units, where a value of 125 would apply a 1.25 scale factor. +**/ + UINT8 Avx512VoltageScaleFactor; + +/** Offset 0x08B2 - Lane Used of CSI port + Lane Used of each CSI port + 1:x1, 2:x2, 3:x3, 4:x4, 8:x8 +**/ + UINT8 IpuLaneUsed[8]; + +/** Offset 0x08BA - Lane Used of CSI port + Speed of each CSI port + 0:Sensor default, 1:<416Mbps, 2:<1.5Gbps, 3:<2Gbps, 4:<2.5Gbps, 5:<4Gbps, 6:>4Gbps +**/ + UINT8 CsiSpeed[8]; + +/** Offset 0x08C2 - DPmem Support + 1: enable, 0: disable(Default), Enable/disable setting for Dynamic Persistent Memory support + $EN_DIS +**/ + UINT8 DpmemSupport; + +/** Offset 0x08C3 - Core VF Point Offset Mode + Selects Core Voltage & Frequency Point Offset between Legacy and Selection modes; + 0: Legacy; 1: Selection. + 0:Legacy, 1:Selection +**/ + UINT8 CoreVfPointOffsetMode; + +/** Offset 0x08C4 - Core VF Point Offset + Array used to specifies the Offset Voltage applied to the each selected Core VF + Point. This voltage is specified in millivolts. +**/ + UINT16 CoreVfPointOffset[15]; + +/** Offset 0x08E2 - Core VF Point Offset Prefix + Sets the CoreVfPointOffset value as positive or negative for corresponding core + VF Point; 0: Positive ; 1: Negative. + 0:Positive, 1:Negative +**/ + UINT8 CoreVfPointOffsetPrefix[15]; + +/** Offset 0x08F1 - Core VF Point Ratio + Array for the each selected Core VF Point to display the ration. +**/ + UINT8 CoreVfPointRatio[15]; + +/** Offset 0x0900 - Core VF Point Count + Number of supported Core Voltage & Frequency Point Offset +**/ + UINT8 CoreVfPointCount; + +/** Offset 0x0901 - Enable CPU CrashLog GPRs dump + Enable or Disable CPU CrashLog GPRs dump; 0: Disable; 1: Enable; 2: Only + disable Smm GPRs dump + 0:Disabled, 1:Enabled, 2:Only Smm GPRs Disabled +**/ + UINT8 CrashLogGprs; + +/** Offset 0x0902 +**/ + UINT8 UnusedUpdSpace23[2]; + +/** Offset 0x0904 - Bitmask of disable cores + Core mask is a bitwise indication of which core should be disabled. 0x00=Default; + Bit 0 - core 0, bit 7 - core 7. +**/ + UINT32 DisableCoreMask; + +/** Offset 0x0908 - REFRESH_PANIC_WM + @deprecated - Not used and has no effect, Please use RefreshWm +**/ + UINT8 RefreshPanicWm; + +/** Offset 0x0909 - REFRESH_HP_WM + @deprecated - Not used and has no effect, Please use RefreshWm +**/ + UINT8 RefreshHpWm; + +/** Offset 0x090A - Support Unlimited ICCMAX + Support Unlimited ICCMAX more than maximum value 255.75A; 0: Disabled; 1: Enabled. + $EN_DIS +**/ + UINT8 UnlimitedIccMax; + +/** Offset 0x090B - Per Core Max Ratio override + Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new + favored core ratio to each Core. 0: Disable, 1: enable + $EN_DIS +**/ + UINT8 PerCoreRatioOverride; + +/** Offset 0x090C - Per Core Current Max Ratio + Array for the Per Core Max Ratio +**/ + UINT8 PerCoreRatio[10]; + +/** Offset 0x0916 - Margin Limit Check + Margin Limit Check. Choose level of margin check + 0:Disable, 1:L1, 2:L2, 3:Both +**/ + UINT8 MarginLimitCheck; + +/** Offset 0x0917 +**/ + UINT8 UnusedUpdSpace24; + +/** Offset 0x0918 - Margin Limit L2 + % of L1 check for margin limit check +**/ + UINT16 MarginLimitL2; + +/** Offset 0x091A - Iotg Pll SscEn + Enable or disable CPU SSC. 0: Disable, 1: Enable + $EN_DIS +**/ + UINT8 IotgPllSscEn; /** Offset 0x091B - GPIO Override Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings @@ -2504,9 +3382,135 @@ **/ UINT8 GpioOverride; -/** Offset 0x091C - Reserved +/** Offset 0x091C - Write0 enabling + Enable/Disable Write0 + $EN_DIS **/ - UINT8 Reserved44[52]; + UINT8 WRITE0; + +/** Offset 0x091D +**/ + UINT8 UnusedUpdSpace25[3]; + +/** Offset 0x0920 +**/ + UINT32 VccInVoltageOverride; + +/** Offset 0x0924 - Dynamic Memory Timings Changes + Dynamic Memory Timings Changes; 0: Disabled; 1: Enabled. + $EN_DIS +**/ + UINT8 DynamicMemoryChange; + +/** Offset 0x0925 - IbeccErrorInj + In-Band ECC Error Injection NOTE: For Debug or Development purposes only! Disable + this option for production systems. + $EN_DIS +**/ + UINT8 IbeccErrorInj; + +/** Offset 0x0926 - Enable/Disable DMI GEN3 DmiGen3UsPresetEnable + Enable/Disable DMI GEN3 DmiGen3UsPreset. Auto(0x0)(Default): DmiGen3UsPresetEnable, + Manual(0x1): Enable DmiGen3UsPresetEnable + $EN_DIS +**/ + UINT8 DmiGen3UsPresetEnable; + +/** Offset 0x0927 - DMI Gen3 Root port preset Rx values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default + for each lane +**/ + UINT8 DmiGen3UsPortRxPreset[8]; + +/** Offset 0x092F - DMI Gen3 Root port preset Tx values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-10, 1 is default + for each lane +**/ + UINT8 DmiGen3UsPortTxPreset[8]; + +/** Offset 0x0937 - BCLK Frequency Source + Clock source of BCLK OC frequency, 0:CPU BCLK, 1:PCH BCLK, 2:External CLK + 0:CPU BCLK, 1:PCH BCLK, 2:External CLK +**/ + UINT8 BclkSource; + +/** Offset 0x0938 - CPU BCLK OC Frequency + CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz 0 + - Auto. Range is 8000-50000 (10KHz). +**/ + UINT32 CpuBclkOcFrequency; + +/** Offset 0x093C - Ring CCF Auto Gv Disable Down + Ring CCF Auto Gv Disable Down, 0: Disabled, 1:Fused default + 0:Disabled, 1:Fused default +**/ + UINT8 RingCcfAutoGvDisable; + +/** Offset 0x093D - SA/Uncore voltage mode + SA/Uncore voltage mode; 0: Adaptive; 1: Override. + $EN_DIS +**/ + UINT8 SaVoltageMode; + +/** Offset 0x093E - SA/Uncore Voltage Override + The SA/Uncore voltage override applicable when SA/Uncore voltage mode is in Override + mode. Valid Range 0 to 2000 +**/ + UINT16 SaVoltageOverride; + +/** Offset 0x0940 - SA/Uncore Extra Turbo voltage + Extra Turbo voltage applicable when SA/Uncore voltage mode is in Adaptive mode. + Valid Range 0 to 2000 +**/ + UINT16 SaExtraTurboVoltage; + +/** Offset 0x0942 - DdrMemoryDown + DDR Memory Down Support. + $EN_DIS +**/ + UINT8 DdrMemoryDown; + +/** Offset 0x0943 +**/ + UINT8 UnusedUpdSpace26; + +/** Offset 0x0944 - The VccIn Max Voltage Limit + This will override maximum VCCIN voltage limit to the voltage value specified. 0 + - no override Valid Range 0 to 3000mV +**/ + UINT16 VccInMaxLimit; + +/** Offset 0x0946 - VccIO Voltage Override + This will override VccIO output voltage level to the voltage value specified. Valid + Range 0 to 2000 +**/ + UINT16 VccIoVoltageOverride; + +/** Offset 0x0948 - Boost VRef Voltage + Default: 0: 0.7V 1: 1.0V to support the high frequencies needed for BCLK OC. + 0: 0.7V , 1:1.0V +**/ + UINT8 BoostRefVoltage; + +/** Offset 0x0949 - Pcie Ref Pll SSC + Pcie Ref Pll SSC Percentatge. 0x0: 0.0%, 0x1: 0.1%, 0x2:0.2%, 0x3: 0.3%, 0x4: 0.4%, + 0x5: 0.5%, 0xFE: Disable, 0xFF: Auto +**/ + UINT8 PcieRefPllSsc; + +/** Offset 0x094A - Refresh Watermarks + Refresh Watermark, High, Low + 1:Enable Refresh Watermark High (Default), 0:Enable Refresh Watermark Low +**/ + UINT8 RefreshWm; + +/** Offset 0x094B +**/ + UINT8 UnusedUpdSpace27[4]; + +/** Offset 0x094F +**/ + UINT8 ReservedFspmUpd2[1]; } FSP_M_CONFIG; /** Fsp M UPD Configuration diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index 9969c73..569eaea 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -123,9 +123,9 @@ **/ UINT8 ShowSpiController; -/** Offset 0x0036 - Reserved +/** Offset 0x0036 **/ - UINT8 Reserved0[2]; + UINT8 UnusedUpdSpace0[2]; /** Offset 0x0038 - MicrocodeRegionBase Memory Base of Microcode Updates @@ -179,9 +179,9 @@ **/ UINT8 XdciEnable; -/** Offset 0x006D - Reserved +/** Offset 0x006D **/ - UINT8 Reserved1[3]; + UINT8 UnusedUpdSpace1[3]; /** Offset 0x0070 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. @@ -227,9 +227,9 @@ **/ UINT8 PchHdaVerbTableEntryNum; -/** Offset 0x0082 - Reserved +/** Offset 0x0082 **/ - UINT8 Reserved2[2]; + UINT8 UnusedUpdSpace2[2]; /** Offset 0x0084 - PCH HDA Verb Table Pointer Pointer to Array of pointers to Verb Table. @@ -265,9 +265,10 @@ **/ UINT8 SerialIoSpiCsPolarity[14]; -/** Offset 0x00A0 - Reserved +/** Offset 0x00A0 - SPI<N> Chip Select Enable + 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled **/ - UINT8 Reserved3[14]; + UINT8 SerialIoSpiCsEnable[14]; /** Offset 0x00AE - SPIn Default Chip Select Output Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available @@ -294,9 +295,9 @@ **/ UINT8 SerialIoUartMode[7]; -/** Offset 0x00CA - Reserved +/** Offset 0x00CA **/ - UINT8 Reserved4[2]; + UINT8 UnusedUpdSpace3[2]; /** Offset 0x00CC - Default BaudRate for each Serial IO UART Set default BaudRate Supported from 0 - default to 6000000 @@ -334,9 +335,9 @@ **/ UINT8 SerialIoUartAutoFlow[7]; -/** Offset 0x0112 - Reserved +/** Offset 0x0112 **/ - UINT8 Reserved5[2]; + UINT8 UnusedUpdSpace4[2]; /** Offset 0x0114 - SerialIoUartRtsPinMuxPolicy Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* @@ -401,9 +402,155 @@ **/ UINT8 PchSerialIoI2cPadsTermination[8]; -/** Offset 0x01DC - Reserved +/** Offset 0x01DC - ISH GP GPIO Pin Muxing + Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER **/ - UINT8 Reserved6[184]; + UINT32 IshGpGpioPinMuxing[8]; + +/** Offset 0x01FC - ISH UART Rx Pin Muxing + Determines ISH UART Rx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_TXD_* +**/ + UINT32 IshUartRxPinMuxing[3]; + +/** Offset 0x0208 - ISH UART Tx Pin Muxing + Determines ISH UART Tx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_RXD_* +**/ + UINT32 IshUartTxPinMuxing[3]; + +/** Offset 0x0214 - ISH UART Rts Pin Muxing + Select ISH UART Rts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_RTS_* for possible values. +**/ + UINT32 IshUartRtsPinMuxing[3]; + +/** Offset 0x0220 - ISH UART Rts Pin Muxing + Select ISH UART Cts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_CTS_* for possible values. +**/ + UINT32 IshUartCtsPinMuxing[3]; + +/** Offset 0x022C - ISH I2C SDA Pin Muxing + Select ISH I2C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SDA_* for possible values. +**/ + UINT32 IshI2cSdaPinMuxing[3]; + +/** Offset 0x0238 - ISH I2C SCL Pin Muxing + Select ISH I2C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SCL_* for possible values. +**/ + UINT32 IshI2cSclPinMuxing[3]; + +/** Offset 0x0244 - ISH SPI MOSI Pin Muxing + Select ISH SPI MOSI Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MOSI_* for possible values. +**/ + UINT32 IshSpiMosiPinMuxing[2]; + +/** Offset 0x024C - ISH SPI MISO Pin Muxing + Select ISH SPI MISO Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MISO_* for possible values. +**/ + UINT32 IshSpiMisoPinMuxing[2]; + +/** Offset 0x0254 - ISH SPI CLK Pin Muxing + Select ISH SPI CLK Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CLK_* for possible values. +**/ + UINT32 IshSpiClkPinMuxing[2]; + +/** Offset 0x025C - ISH SPI CS#N Pin Muxing + Select ISH SPI CS#N Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CS<N>_* for possible + values. N-SPI number, 0-1. +**/ + UINT32 IshSpiCsPinMuxing[4]; + +/** Offset 0x026C - ISH GP GPIO Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo GP#N GPIO pads termination + respectively. #N are GP_NUMBER, not strictly relate to indexes of this table. Index + 0-23 -> ISH_GP_0-23, Index 24-25 -> ISH_GP_30-31 +**/ + UINT8 IshGpGpioPadTermination[8]; + +/** Offset 0x0274 - ISH UART Rx Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rx pads termination + respectively. #N-byte for each controller, byte0 for UART0 Rx, byte1 for UART1 + Rx, and so on. +**/ + UINT8 IshUartRxPadTermination[3]; + +/** Offset 0x0277 - ISH UART Tx Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Tx pads termination + respectively. #N-byte for each controller, byte0 for UART0 Tx, byte1 for UART1 + Tx, and so on. +**/ + UINT8 IshUartTxPadTermination[3]; + +/** Offset 0x027A - ISH UART Rts Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rts pads termination + respectively. #N-byte for each controller, byte0 for UART0 Rts, byte1 for UART1 + Rts, and so on. +**/ + UINT8 IshUartRtsPadTermination[3]; + +/** Offset 0x027D - ISH UART Rts Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Cts pads termination + respectively. #N-byte for each controller, byte0 for UART0 Cts, byte1 for UART1 + Cts, and so on. +**/ + UINT8 IshUartCtsPadTermination[3]; + +/** Offset 0x0280 - ISH I2C SDA Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination + respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda, + and so on. +**/ + UINT8 IshI2cSdaPadTermination[3]; + +/** Offset 0x0283 - ISH I2C SCL Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination + respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl, + and so on. +**/ + UINT8 IshI2cSclPadTermination[3]; + +/** Offset 0x0286 - ISH SPI MOSI Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Mosi pads termination + respectively. #N-byte for each controller, byte0 for SPI0 Mosi, byte1 for SPI1 + Mosi, and so on. +**/ + UINT8 IshSpiMosiPadTermination[2]; + +/** Offset 0x0288 - ISH SPI MISO Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Miso pads termination + respectively. #N-byte for each controller, byte0 for SPI0 Miso, byte1 for SPI1 + Miso, and so on. +**/ + UINT8 IshSpiMisoPadTermination[2]; + +/** Offset 0x028A - ISH SPI CLK Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Clk pads termination + respectively. #N-byte for each controller, byte0 for SPI0 Clk, byte1 for SPI1 Clk, + and so on. +**/ + UINT8 IshSpiClkPadTermination[2]; + +/** Offset 0x028C - ISH SPI CS#N Pad termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Cs#M pads termination + respectively. N*M-byte for each controller, byte0 for SPI0 Cs0, byte1 for SPI1 + Cs1, SPI1 Cs0, byte2, SPI1 Cs1, byte3 +**/ + UINT8 IshSpiCsPadTermination[4]; + +/** Offset 0x0290 - Enable PCH ISH SPI Cs#N pins assigned + Set if ISH SPI Cs#N pins are to be enabled by BIOS. 0: Disable; 1: Enable. N-Cs + number: 0-1 +**/ + UINT8 PchIshSpiCsEnable[4]; /** Offset 0x0294 - USB Per Port HS Preemphasis Bias USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, @@ -491,18 +638,46 @@ **/ UINT8 PchLanEnable; -/** Offset 0x034D - Reserved +/** Offset 0x034D - Enable PCH TSN + Enable/disable TSN on the PCH. + $EN_DIS **/ - UINT8 Reserved7[11]; + UINT8 PchTsnEnable; + +/** Offset 0x034E - TSN Link Speed + Set TSN Link Speed. + 0: 24Mhz 2.5Gbps, 1: 24Mhz 1Gbps, 2: 38.4Mhz 2.5Gbps, 3: 38.4Mhz 1Gbps +**/ + UINT8 PchTsnLinkSpeed; + +/** Offset 0x034F +**/ + UINT8 UnusedUpdSpace5; + +/** Offset 0x0350 - PCH TSN0 MAC Address High Bits + Set TSN0 MAC Address High. +**/ + UINT32 PchTsn0MacAddressHigh; + +/** Offset 0x0354 - PCH TSN0 MAC Address Low Bits + Set TSN0 MAC Address Low. +**/ + UINT32 PchTsn0MacAddressLow; /** Offset 0x0358 - PCIe PTM enable/disable Enable/disable Precision Time Measurement for PCIE Root Ports. **/ UINT8 PciePtm[24]; -/** Offset 0x0370 - Reserved +/** Offset 0x0370 - PCIe DPC enable/disable + Enable/disable Downstream Port Containment for PCIE Root Ports. **/ - UINT8 Reserved8[48]; + UINT8 PcieDpc[24]; + +/** Offset 0x0388 - PCIe DPC extensions enable/disable + Enable/disable Downstream Port Containment Extensions for PCIE Root Ports. +**/ + UINT8 PcieEdpc[24]; /** Offset 0x03A0 - USB PDO Programming Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming @@ -511,9 +686,9 @@ **/ UINT8 UsbPdoProgramming; -/** Offset 0x03A1 - Reserved +/** Offset 0x03A1 **/ - UINT8 Reserved9[3]; + UINT8 UnusedUpdSpace6[3]; /** Offset 0x03A4 - Power button debounce configuration Debounce time for PWRBTN in microseconds. For values not supported by HW, they will @@ -563,9 +738,9 @@ **/ UINT8 PchFivrExtVnnRailSupportedVoltageStates; -/** Offset 0x03B1 - Reserved +/** Offset 0x03B1 **/ - UINT8 Reserved10; + UINT8 UnusedUpdSpace7; /** Offset 0x03B2 - External Vnn Voltage Value that will be used in S0ix/Sx states Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420 @@ -618,9 +793,9 @@ **/ UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime; -/** Offset 0x03BE - Reserved +/** Offset 0x03BE **/ - UINT8 Reserved11[2]; + UINT8 UnusedUpdSpace8[2]; /** Offset 0x03C0 - Trace Hub Memory Base If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate @@ -636,9 +811,9 @@ **/ UINT8 PmcDbgMsgEn; -/** Offset 0x03C5 - Reserved +/** Offset 0x03C5 **/ - UINT8 Reserved12[3]; + UINT8 UnusedUpdSpace9[3]; /** Offset 0x03C8 - Pointer of ChipsetInit Binary ChipsetInit Binary Pointer. @@ -656,18 +831,61 @@ **/ UINT8 PchFivrDynPm; -/** Offset 0x03D1 - Reserved +/** Offset 0x03D1 **/ - UINT8 Reserved13; + UINT8 UnusedUpdSpace10; /** Offset 0x03D2 - External V1P05 Icc Max Value Granularity of this setting is 1mA and maximal possible value is 500mA **/ UINT16 PchFivrExtV1p05RailIccMaximum; -/** Offset 0x03D4 - Reserved +/** Offset 0x03D4 - External Vnn Icc Max Value that will be used in S0ix/Sx states + Granularity of this setting is 1mA and maximal possible value is 500mA **/ - UINT8 Reserved14[16]; + UINT16 PchFivrExtVnnRailIccMaximum; + +/** Offset 0x03D6 - External Vnn Icc Max Value that will be used in Sx states + Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting + is 1mA and maximal possible value is 500mA +**/ + UINT16 PchFivrExtVnnRailSxIccMaximum; + +/** Offset 0x03D8 - PCH eSPI Link Configuration Lock (SBLCL) + Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI slaves + addresseses from range 0x0 - 0x7FF + $EN_DIS +**/ + UINT8 PchEspiLockLinkConfiguration; + +/** Offset 0x03D9 - Extented BIOS Direct Read Decode enable + Enable/Disable access to bigger than 16MB BIOS Region through Direct Memory Reads. + 0: disabled (default), 1: enabled + $EN_DIS +**/ + UINT8 PchSpiExtendedBiosDecodeRangeEnable; + +/** Offset 0x03DA - Enforce Enhanced Debug Mode + Determine if ME should enter Enhanced Debug Mode. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 EnforceEDebugMode; + +/** Offset 0x03DB - PchPostMemRsvd + Reserved for PCH Post-Mem + $EN_DIS +**/ + UINT8 PchPostMemRsvd[1]; + +/** Offset 0x03DC - Extended BIOS Direct Read Decode Range base + Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode. +**/ + UINT32 PchSpiExtendedBiosDecodeRangeBase; + +/** Offset 0x03E0 - Extended BIOS Direct Read Decode Range limit + Bits of 31:16 of a memory address that'll be a limit for Extended BIOS Direct Read Decode. +**/ + UINT32 PchSpiExtendedBiosDecodeRangeLimit; /** Offset 0x03E4 - CNVi Configuration This option allows for automatic detection of Connectivity Solution. [Auto Detection] @@ -688,9 +906,9 @@ **/ UINT8 CnviBtAudioOffload; -/** Offset 0x03E7 - Reserved +/** Offset 0x03E7 **/ - UINT8 Reserved15; + UINT8 UnusedUpdSpace11; /** Offset 0x03E8 - CNVi RF_RESET pin muxing Select CNVi RF_RESET# pin depending on board routing. TGP-LP: GPP_A8 = 0x2942E408(default) @@ -731,9 +949,15 @@ **/ UINT8 PchEspiLgmrEnable; -/** Offset 0x03F4 - Reserved +/** Offset 0x03F4 - External V1P05 Control Ramp Timer value + Hold off time to be used when changing the v1p05_ctrl for external bypass value in us **/ - UINT8 Reserved16[2]; + UINT8 PchFivrExtV1p05RailCtrlRampTmr; + +/** Offset 0x03F5 - External VNN Control Ramp Timer value + Hold off time to be used when changing the vnn_ctrl for external bypass value in us +**/ + UINT8 PchFivrExtVnnRailCtrlRampTmr; /** Offset 0x03F6 - Set SATA DEVSLP GPIO Reset Config Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset, @@ -801,9 +1025,9 @@ **/ UINT8 AmtSolEnabled; -/** Offset 0x0407 - Reserved +/** Offset 0x0407 **/ - UINT8 Reserved17; + UINT8 UnusedUpdSpace12; /** Offset 0x0408 - OS Timer 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0. @@ -850,9 +1074,9 @@ **/ UINT8 PcieRpEnableCpm[24]; -/** Offset 0x0457 - Reserved +/** Offset 0x0457 **/ - UINT8 Reserved18; + UINT8 UnusedUpdSpace13[1]; /** Offset 0x0458 - PCIE RP Detect Timeout Ms The number of milliseconds within 0~65535 in reference code will wait for link to @@ -868,9 +1092,19 @@ **/ UINT8 PmcModPhySusPgEnable; -/** Offset 0x0489 - Reserved +/** Offset 0x0489 - V1p05-PHY supply external FET control + Enable/Disable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY + supply. 0: disable, 1: enable + $EN_DIS **/ - UINT8 Reserved19[2]; + UINT8 PmcV1p05PhyExtFetControlEn; + +/** Offset 0x048A - V1p05-IS supply external FET control + Enable/Disable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS + supply. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PmcV1p05IsExtFetControlEn; /** Offset 0x048B - Enable/Disable PavpEnable Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable @@ -929,9 +1163,16 @@ **/ UINT8 ITbtPcieTunnelingForUsb4; -/** Offset 0x04BA - Reserved +/** Offset 0x04BA - Enable/Disable SkipFspGop + Enable: Skip FSP provided GOP driver, Disable(Default): Use FSP provided GOP driver + $EN_DIS **/ - UINT8 Reserved20[2]; + UINT8 SkipFspGop; + +/** Offset 0x04BB - TC State in TCSS + This TC C-State Limit in IOM +**/ + UINT8 TcCstateLimit; /** Offset 0x04BC - Disable TC code On USB Connect Enable: Unsupported TC cold capability on Usb Connected, Disable(default): Supported @@ -940,9 +1181,21 @@ **/ UINT8 DisableTccoldOnUsbConnected; -/** Offset 0x04BD - Reserved +/** Offset 0x04BD - Set Iom stay in TC cold seconds in TCSS + Set Iom stay in TC cold seconds in IOM **/ - UINT8 Reserved21[4]; + UINT8 IomStayInTCColdeSeconds; + +/** Offset 0x04BE - Set Iom before entering TC cold seconds in TCSS + Set Iom before entering TC cold seconds in IOM +**/ + UINT8 IomBeforeEnteringTCCodeSeconds; + +/** Offset 0x04BF - SaPostMemRsvd + Reserved for PCH Post-Mem + $EN_DIS +**/ + UINT8 SaPostMemRsvd[2]; /** Offset 0x04C1 - Enable VMD controller Enable/disable to VMD controller.0: Disable(Default); 1: Enable @@ -974,9 +1227,10 @@ **/ UINT8 VmdPortD; -/** Offset 0x04C6 - Reserved +/** Offset 0x04C6 - VMD Config Bar size + Set The VMD Config Bar Size. **/ - UINT8 Reserved22; + UINT8 VmdCfgBarSize; /** Offset 0x04C7 - VMD Config Bar Attributes 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH(Default) @@ -984,9 +1238,10 @@ **/ UINT8 VmdCfgBarAttr; -/** Offset 0x04C8 - Reserved +/** Offset 0x04C8 - VMD Mem Bar1 size + Set The VMD Mem Bar1 Size. **/ - UINT8 Reserved23; + UINT8 VmdMemBarSize1; /** Offset 0x04C9 - VMD Mem Bar1 Attributes 0: VMD_32BIT_NONPREFETCH(Default), 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH @@ -994,9 +1249,10 @@ **/ UINT8 VmdMemBar1Attr; -/** Offset 0x04CA - Reserved +/** Offset 0x04CA - VMD Mem Bar2 size + Set The VMD Mem Bar2 Size. **/ - UINT8 Reserved24; + UINT8 VmdMemBarSize2; /** Offset 0x04CB - VMD Mem Bar2 Attributes 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH @@ -1010,9 +1266,9 @@ **/ UINT8 PmcPdEnable; -/** Offset 0x04CD - Reserved +/** Offset 0x04CD **/ - UINT8 Reserved25; + UINT8 UnusedUpdSpace14; /** Offset 0x04CE - TCSS Aux Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides @@ -1097,9 +1353,9 @@ **/ UINT8 SaPcieItbtRpSnoopLatencyOverrideMultiplier[4]; -/** Offset 0x04F3 - Reserved +/** Offset 0x04F3 **/ - UINT8 Reserved26; + UINT8 UnusedUpdSpace15[1]; /** Offset 0x04F4 - PCIE RP Snoop Latency Override Value Latency Tolerance Reporting, Snoop Latency Override Value. @@ -1149,9 +1405,9 @@ **/ UINT8 Psi4Enable[5]; -/** Offset 0x051F - Reserved +/** Offset 0x051F **/ - UINT8 Reserved27; + UINT8 UnusedUpdSpace16[1]; /** Offset 0x0520 - Imon slope correction PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. @@ -1225,9 +1481,11 @@ **/ UINT8 EnableMultiPhaseSiliconInit; -/** Offset 0x0556 - Reserved +/** Offset 0x0556 - Thermal Design Current current limit + PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. + Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes **/ - UINT8 Reserved28[10]; + UINT16 TdcCurrentLimit[5]; /** Offset 0x0560 - AcLoadline PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is @@ -1275,8 +1533,9 @@ UINT8 SendVrMbxCmd; /** Offset 0x05A7 - Reserved + Reserved **/ - UINT8 Reserved29; + UINT8 Reserved2; /** Offset 0x05A8 - Enable or Disable TXT Enable or Disable TXT; 0: Disable; 1: Enable. @@ -1305,9 +1564,9 @@ **/ UINT8 FivrSpreadSpectrum; -/** Offset 0x05AD - Reserved +/** Offset 0x05AD **/ - UINT8 Reserved30[3]; + UINT8 UnusedUpdSpace17[3]; /** Offset 0x05B0 - CpuBistData Pointer CPU BIST Data @@ -1326,9 +1585,42 @@ **/ UINT32 CpuMpHob; -/** Offset 0x05BC - Reserved +/** Offset 0x05BC - RFI Mitigation + Enable or Disable RFI Mitigation. 0: Disable - DCM is the IO_N default; 1: + Enable - Enable IO_N DCM/CCM switching as RFI mitigation. + $EN_DIS **/ - UINT8 Reserved31[16]; + UINT8 RfiMitigation; + +/** Offset 0x05BD - FIVR RFI Spread Spectrum Enable or disable + Enable or Disable FIVR RFI Spread Spectrum. 0: Disable ; 1: Enable +**/ + UINT8 FivrSpectrumEnable; + +/** Offset 0x05BE - Pre Wake Randomization time + PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum pre-wake + randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation + is enabled. Range 0-255 0. +**/ + UINT8 PreWake; + +/** Offset 0x05BF - Ramp Up Randomization time + PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum Ramp Up + randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation + is enabled.Range 0-255 0. +**/ + UINT8 RampUp; + +/** Offset 0x05C0 - Ramp Down Randomization time + PCODE MMIO Mailbox: Acoustic Noise Mitigation Range.Defines the maximum Ramp Down + randomization time in micro ticks.This can be programmed only if AcousticNoiseMitigation + is enabled.Range 0-255 0. +**/ + UINT8 RampDown; + +/** Offset 0x05C1 +**/ + UINT8 CpuPostMemRsvd[11]; /** Offset 0x05CC - PpinSupport to view Protected Processor Inventory Number Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this @@ -1367,9 +1659,35 @@ **/ UINT16 MinVoltageC8; -/** Offset 0x05DE - Reserved +/** Offset 0x05DE - Platform Psys offset correction + PCODE MMIO Mailbox: Platform Psys offset correction. 0 - Auto Units 1/1000, + Range 0-63999. For an offset of 25.348, enter 25348. **/ - UINT8 Reserved32[10]; + UINT16 PsysOffset1; + +/** Offset 0x05E0 - Smbios Type4 Max Speed Override + Provide the option for platform to override the MaxSpeed field of Smbios Type 4. + If this value is not zero, it dominates the field. +**/ + UINT16 SmbiosType4MaxSpeedOverride; + +/** Offset 0x05E2 - AvxDisable + Enable or Disable AVX Support. + 0: Enable, 1: Disable +**/ + UINT8 AvxDisable; + +/** Offset 0x05E3 - Avx3Disable + Enable or Disable AVX3 Support + 0: Enable, 1: Disable +**/ + UINT8 Avx3Disable; + +/** Offset 0x05E4 - ReservedCpuPostMemProduction + Reserved for CPU Post-Mem Production + $EN_DIS +**/ + UINT8 ReservedCpuPostMemProduction[4]; /** Offset 0x05E8 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. @@ -1387,9 +1705,9 @@ **/ UINT8 PchReadProtectionEnable[5]; -/** Offset 0x05F3 - Reserved +/** Offset 0x05F3 **/ - UINT8 Reserved33; + UINT8 UnusedUpdSpace18[1]; /** Offset 0x05F4 - PCH Protect Range Limit Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for @@ -1414,9 +1732,11 @@ **/ UINT8 PchHdaLinkFrequency; -/** Offset 0x060A - Reserved +/** Offset 0x060A - PchPostMemRsvd + Reserved for PCH Post-Mem + $EN_DIS **/ - UINT8 Reserved34[3]; + UINT8 PchPostMemRsvd4[3]; /** Offset 0x060D - Enable PCH ISH SPI Cs0 pins assigned Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. @@ -1479,9 +1799,11 @@ **/ UINT8 PchCrid; -/** Offset 0x0622 - Reserved +/** Offset 0x0622 - RTC BIOS Interface Lock + Enable RTC BIOS interface lock. When set, prevents RTC TS (BUC.TS) from being changed. + $EN_DIS **/ - UINT8 Reserved35; + UINT8 RtcBiosInterfaceLock; /** Offset 0x0623 - RTC Cmos Memory Lock Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper @@ -1561,9 +1883,15 @@ **/ UINT8 ThcPort0Assignment; -/** Offset 0x075D - Reserved +/** Offset 0x075D **/ - UINT8 Reserved36[7]; + UINT8 UnusedUpdSpace19[3]; + +/** Offset 0x0760 - THC Port 0 Interrupt Pin Mux + Set THC Port 0 Pin Muxing Value if signal can be enabled on multiple pads. Refer + to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values. +**/ + UINT32 ThcPort0InterruptPinMuxing; /** Offset 0x0764 - Touch Host Controller Port 1 Assignment Assign THC Port 1 @@ -1571,9 +1899,27 @@ **/ UINT8 ThcPort1Assignment; -/** Offset 0x0765 - Reserved +/** Offset 0x0765 - Touch Host Controller Port 1 ReadFrequency + Set THC Port 1 Read Frequency (THC_PORT_FREQUENCY enum): 0:2p1MHz,1:2p5Mz,2:3Mz,3:3p75Mz,4:5MHz,5:7p5MHz,6:15MHz,7:17MHz,8:20MHz,9:24MHz,10:30MHz + 0:2p1MHz,1:2p5Mz,2:3Mz,3:3p75Mz,4:5MHz,5:7p5MHz,6:15MHz,7:17MHz,8:20MHz,9:24MHz,10:30MHz **/ - UINT8 Reserved37[7]; + UINT8 ThcPort1ReadFrequency; + +/** Offset 0x0766 - Touch Host Controller Port 1 WriteFrequency + Set THC Port 1 Write Frequency (THC_PORT_FREQUENCY enum): 0:2p1MHz,1:2p5Mz,2:3Mz,3:3p75Mz,4:5MHz,5:7p5MHz,6:15MHz,7:17MHz,8:20MHz,9:24MHz,10:30MHz + 0:2p1MHz,1:2p5Mz,2:3Mz,3:3p75Mz,4:5MHz,5:7p5MHz,6:15MHz,7:17MHz,8:20MHz,9:24MHz,10:30MHz +**/ + UINT8 ThcPort1WriteFrequency; + +/** Offset 0x0767 +**/ + UINT8 UnusedUpdSpace20; + +/** Offset 0x0768 - THC Port 1 Interrupt Pin Mux + Set THC Port 1 Pin Muxing Value if signal can be enabled on multiple pads. Refer + to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values. +**/ + UINT32 ThcPort1InterruptPinMuxing; /** Offset 0x076C - PCIE RP Pcie Speed Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: @@ -1613,9 +1959,66 @@ **/ UINT8 PcieRpLtrConfigLock[24]; -/** Offset 0x0814 - Reserved +/** Offset 0x0814 - PCIe override default settings for EQ + Choose PCIe EQ method + $EN_DIS **/ - UINT8 Reserved38[45]; + UINT8 PcieEqOverrideDefault; + +/** Offset 0x0815 - PCIe choose EQ method + Choose PCIe EQ method + 0: HardwareEq, 1: FixedEq +**/ + UINT8 PcieEqMethod; + +/** Offset 0x0816 - PCIe choose EQ mode + Choose PCIe EQ mode + 0: PresetEq, 1: CoefficientEq +**/ + UINT8 PcieEqMode; + +/** Offset 0x0817 - PCIe EQ local transmitter override + Enable/Disable local transmitter override + $EN_DIS +**/ + UINT8 PcieEqLocalTransmitterOverrideEnable; + +/** Offset 0x0818 - PCIe number of valid list entries + Select number of presets or coefficients depending on the mode +**/ + UINT8 PcieEqPh3NumberOfPresetsOrCoefficients; + +/** Offset 0x0819 - PCIe pre-cursor coefficient list + Provide a list of pre-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieEqPh3PreCursorList[10]; + +/** Offset 0x0823 - PCIe post-cursor coefficient list + Provide a list of post-cursor coefficients to be used during phase 3 EQ +**/ + UINT8 PcieEqPh3PostCursorList[10]; + +/** Offset 0x082D - PCIe preset list + Provide a list of presets to be used during phase 3 EQ +**/ + UINT8 PcieEqPh3PresetList[11]; + +/** Offset 0x0838 - PCIe EQ phase 1 downstream transmitter port preset + Allows to select the downstream port preset value that will be used during phase + 1 of equalization +**/ + UINT32 PcieEqPh1DownstreamPortTransmitterPreset; + +/** Offset 0x083C - PCIe EQ phase 1 upstream tranmitter port preset + Allows to select the upstream port preset value that will be used during phase 1 + of equalization +**/ + UINT32 PcieEqPh1UpstreamPortTransmitterPreset; + +/** Offset 0x0840 - PCIe EQ phase 2 local transmitter override preset + Allows to select the value of the preset used during phase 2 local transmitter override +**/ + UINT8 PcieEqPh2LocalTransmitterOverridePreset; /** Offset 0x0841 - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform. @@ -1636,9 +2039,19 @@ **/ UINT8 PcieRpFunctionSwap; -/** Offset 0x0844 - Reserved +/** Offset 0x0844 - Enable/Disable PEG GEN3 Static EQ Phase1 programming + Program Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets + Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming + $EN_DIS **/ - UINT8 Reserved39[2]; + UINT8 CpuPcieGen3ProgramStaticEq; + +/** Offset 0x0845 - Enable/Disable GEN4 Static EQ Phase1 programming + Program Gen4 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets + Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming + $EN_DIS +**/ + UINT8 CpuPcieGen4ProgramStaticEq; /** Offset 0x0846 - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. @@ -1832,9 +2245,9 @@ **/ UINT8 SataPortsDmVal[8]; -/** Offset 0x0899 - Reserved +/** Offset 0x0899 **/ - UINT8 Reserved40; + UINT8 UnusedUpdSpace21[1]; /** Offset 0x089A - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. @@ -1939,9 +2352,11 @@ **/ UINT8 UfsEnable[2]; -/** Offset 0x08C9 - Reserved +/** Offset 0x08C9 - IEH Mode + Integrated Error Handler Mode, 0: Bypass, 1: Enable + 0: Bypass, 1:Enable **/ - UINT8 Reserved41; + UINT8 IehMode; /** Offset 0x08CA - Thermal Throttling Custimized T0Level Value Custimized T0Level value. @@ -2114,9 +2529,9 @@ **/ UINT8 PchMemoryPinSelection[2]; -/** Offset 0x08EF - Reserved +/** Offset 0x08EF **/ - UINT8 Reserved42; + UINT8 UnusedUpdSpace22; /** Offset 0x08F0 - Thermal Device Temperature Decides the temperature. @@ -2139,9 +2554,9 @@ **/ UINT8 PchUsbLtrOverrideEnable; -/** Offset 0x090D - Reserved +/** Offset 0x090D **/ - UINT8 Reserved43[3]; + UINT8 UnusedUpdSpace23[3]; /** Offset 0x0910 - xHCI High Idle Time LTR override Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting @@ -2201,9 +2616,9 @@ **/ UINT8 HybridStorageMode; -/** Offset 0x0922 - Reserved +/** Offset 0x0922 **/ - UINT8 Reserved44[6]; + UINT8 UnusedUpdSpace24[6]; /** Offset 0x0928 - BgpdtHash[4] BgpdtHash values @@ -2215,9 +2630,9 @@ **/ UINT32 BiosGuardAttr; -/** Offset 0x094C - Reserved +/** Offset 0x094C **/ - UINT8 Reserved45[4]; + UINT8 UnusedUpdSpace25[4]; /** Offset 0x0950 - BiosGuardModulePtr BiosGuardModulePtr default values @@ -2241,9 +2656,9 @@ **/ UINT8 EcCmdLock; -/** Offset 0x0962 - Reserved +/** Offset 0x0962 **/ - UINT8 Reserved46[6]; + UINT8 UnusedUpdSpace26[6]; /** Offset 0x0968 - SgxEpoch0 SgxEpoch0 default values @@ -2267,9 +2682,28 @@ **/ UINT8 SiCsmFlag; -/** Offset 0x097A - Reserved +/** Offset 0x097A - Skip Ssid Programming. + When set to TRUE, silicon code will not do any SSID programming and platform code + needs to handle that by itself properly. + $EN_DIS **/ - UINT8 Reserved47[6]; + UINT8 SiSkipSsidProgramming; + +/** Offset 0x097B +**/ + UINT8 UnusedUpdSpace27; + +/** Offset 0x097C - Change Default SVID + Change the default SVID used in FSP to programming internal devices. This is only + valid when SkipSsidProgramming is FALSE. +**/ + UINT16 SiCustomizedSvid; + +/** Offset 0x097E - Change Default SSID + Change the default SSID used in FSP to programming internal devices. This is only + valid when SkipSsidProgramming is FALSE. +**/ + UINT16 SiCustomizedSsid; /** Offset 0x0980 - SVID SDID table Poniter. The address of the table of SVID SDID to customize each SVID SDID entry. This is @@ -2335,17 +2769,296 @@ **/ UINT8 PmcOsIdleEnable; -/** Offset 0x099D - Reserved +/** Offset 0x099D - S0ix Auto-Demotion + Enable/Disable the Low Power Mode Auto-Demotion Host Control feature. + $EN_DIS **/ - UINT8 Reserved48[315]; + UINT8 PchS0ixAutoDemotion; + +/** Offset 0x099E - Latch Events C10 Exit + When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are + captured on C10 exit (instead of C10 entry which is default) + $EN_DIS +**/ + UINT8 PchPmLatchEventsC10Exit; + +/** Offset 0x099F - PCIE Eq Ph3 Lane Param Cm + CPU_PCIE_EQ_LANE_PARAM. Coefficient C-1. +**/ + UINT8 CpuPcieEqPh3LaneParamCm[32]; + +/** Offset 0x09BF - PCIE Eq Ph3 Lane Param Cp + CPU_PCIE_EQ_LANE_PARAM. Coefficient C+1. +**/ + UINT8 CpuPcieEqPh3LaneParamCp[32]; + +/** Offset 0x09DF - PCIE Hw Eq Gen3 CoeffList Cm + CPU_PCIE_EQ_PARAM. Coefficient C-1. +**/ + UINT8 CpuPcieHwEqGen3CoeffListCm[5]; + +/** Offset 0x09E4 - PCIE Hw Eq Gen3 CoeffList Cp + CPU_PCIE_EQ_PARAM. Coefficient C+1. +**/ + UINT8 CpuPcieHwEqGen3CoeffListCp[5]; + +/** Offset 0x09E9 - PCIE Hw Eq Gen4 CoeffList Cm + CPU_PCIE_EQ_PARAM. Coefficient C-1. +**/ + UINT8 CpuPcieHwEqGen4CoeffListCm[5]; + +/** Offset 0x09EE - PCIE Hw Eq Gen4 CoeffList Cp + CPU_PCIE_EQ_PARAM. Coefficient C+1. +**/ + UINT8 CpuPcieHwEqGen4CoeffListCp[5]; + +/** Offset 0x09F3 - Gen3 Root port preset values per lane + Used for programming Pcie Gen3 preset values per lane. Range: 0-9, 8 is default + for each lane +**/ + UINT8 CpuPcieGen3RootPortPreset[20]; + +/** Offset 0x0A07 - Pcie Gen4 Root port preset values per lane + Used for programming Pcie Gen4 preset values per lane. Range: 0-9, 8 is default + for each lane +**/ + UINT8 CpuPcieGen4RootPortPreset[20]; + +/** Offset 0x0A1B - Pcie Gen3 End port preset values per lane + Used for programming Pcie Gen3 preset values per lane. Range: 0-9, 7 is default + for each lane +**/ + UINT8 CpuPcieGen3EndPointPreset[20]; + +/** Offset 0x0A2F - Pcie Gen4 End port preset values per lane + Used for programming Pcie Gen4 preset values per lane. Range: 0-9, 7 is default + for each lane +**/ + UINT8 CpuPcieGen4EndPointPreset[20]; + +/** Offset 0x0A43 - Pcie Gen3 End port Hint values per lane + Used for programming Pcie Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane +**/ + UINT8 CpuPcieGen3EndPointHint[20]; + +/** Offset 0x0A57 - Pcie Gen4 End port Hint values per lane + Used for programming Pcie Gen4 Hint values per lane. Range: 0-6, 2 is default for each lane +**/ + UINT8 CpuPcieGen4EndPointHint[20]; + +/** Offset 0x0A6B - CPU PCIe Fia Programming + Load Fia configuration if enable. 0: Disable; 1: Enable(Default). + $EN_DIS +**/ + UINT8 CpuPcieFiaProgramming; + +/** Offset 0x0A6C - CPU PCIe RootPort Clock Gating + Describes whether the PCI Express Clock Gating for each root port is enabled by + platform modules. 0: Disable; 1: Enable(Default). + $EN_DIS +**/ + UINT8 CpuPcieClockGating; + +/** Offset 0x0A6D - CPU PCIe RootPort Power Gating + Describes whether the PCI Express Power Gating for each root port is enabled by + platform modules. 0: Disable; 1: Enable(Default). + $EN_DIS +**/ + UINT8 CpuPciePowerGating; + +/** Offset 0x0A6E - PCIE Compliance Test Mode + Compliance Test Mode shall be enabled when using Compliance Load Board. + $EN_DIS +**/ + UINT8 CpuPcieComplianceTestMode; + +/** Offset 0x0A6F - PCIE Secure Register Lock + Describes whether Secure Register Lock is enaled or disabled. When it will be enbaled, + load CpuPcieRpSetSecuredRegisterLock recipe. DEPRECATED 0: Disable(Default); 1: Enable + $EN_DIS +**/ + UINT8 CpuPcieSetSecuredRegisterLock; + +/** Offset 0x0A70 - PCIE Enable Peer Memory Write + This member describes whether Peer Memory Writes are enabled on the platform. + $EN_DIS +**/ + UINT8 CpuPcieEnablePeerMemoryWrite; + +/** Offset 0x0A71 - PCIE Rp Function Swap + Allows BIOS to use root port function number swapping when root port of function + 0 is disabled. + $EN_DIS +**/ + UINT8 CpuPcieRpFunctionSwap; + +/** Offset 0x0A72 - PCI Express Slot Selection + Select the PCIe M2 or CEMx4 slot.0: CEMx4 slot; 1: M2 slot(Default). + $EN_DIS +**/ + UINT8 CpuPcieSlotSelection; + +/** Offset 0x0A73 +**/ + UINT8 UnusedUpdSpace28; + +/** Offset 0x0A74 - CPU PCIE device override table pointer + The PCIe device table is being used to override PCIe device ASPM settings. This + is a pointer points to a 32bit address. And it's only used in PostMem phase. Please + refer to CPU_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId + must be 0. +**/ + UINT32 CpuPcieDeviceOverrideTablePtr; + +/** Offset 0x0A78 - Enable PCIE RP HotPlug + Indicate whether the root port is hot plug available. +**/ + UINT8 CpuPcieRpHotPlug[4]; + +/** Offset 0x0A7C - Enable PCIE RP Pm Sci + Indicate whether the root port power manager SCI is enabled. +**/ + UINT8 CpuPcieRpPmSci[4]; + +/** Offset 0x0A80 - Enable PCIE RP Transmitter Half Swing + Indicate whether the Transmitter Half Swing is enabled. +**/ + UINT8 CpuPcieRpTransmitterHalfSwing[4]; + +/** Offset 0x0A84 - PCIE RP Access Control Services Extended Capability + Enable/Disable PCIE RP Access Control Services Extended Capability +**/ + UINT8 CpuPcieRpAcsEnabled[4]; + +/** Offset 0x0A88 - PCIE RP Clock Power Management + Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal + can still be controlled by L1 PM substates mechanism +**/ + UINT8 CpuPcieRpEnableCpm[4]; + +/** Offset 0x0A8C - PCIE RP Advanced Error Report + Indicate whether the Advanced Error Reporting is enabled. +**/ + UINT8 CpuPcieRpAdvancedErrorReporting[4]; + +/** Offset 0x0A90 - PCIE RP Unsupported Request Report + Indicate whether the Unsupported Request Report is enabled. +**/ + UINT8 CpuPcieRpUnsupportedRequestReport[4]; + +/** Offset 0x0A94 - PCIE RP Fatal Error Report + Indicate whether the Fatal Error Report is enabled. +**/ + UINT8 CpuPcieRpFatalErrorReport[4]; + +/** Offset 0x0A98 - PCIE RP No Fatal Error Report + Indicate whether the No Fatal Error Report is enabled. +**/ + UINT8 CpuPcieRpNoFatalErrorReport[4]; + +/** Offset 0x0A9C - PCIE RP Correctable Error Report + Indicate whether the Correctable Error Report is enabled. +**/ + UINT8 CpuPcieRpCorrectableErrorReport[4]; + +/** Offset 0x0AA0 - PCIE RP System Error On Fatal Error + Indicate whether the System Error on Fatal Error is enabled. +**/ + UINT8 CpuPcieRpSystemErrorOnFatalError[4]; + +/** Offset 0x0AA4 - PCIE RP System Error On Non Fatal Error + Indicate whether the System Error on Non Fatal Error is enabled. +**/ + UINT8 CpuPcieRpSystemErrorOnNonFatalError[4]; + +/** Offset 0x0AA8 - PCIE RP System Error On Correctable Error + Indicate whether the System Error on Correctable Error is enabled. +**/ + UINT8 CpuPcieRpSystemErrorOnCorrectableError[4]; + +/** Offset 0x0AAC - PCIE RP Max Payload + Max Payload Size supported, Default 128B, see enum CPU_PCIE_MAX_PAYLOAD. +**/ + UINT8 CpuPcieRpMaxPayload[4]; + +/** Offset 0x0AB0 - DPC for PCIE RP Mask + Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable. + One bit for each port, bit0 for port1, bit1 for port2, and so on. +**/ + UINT8 CpuPcieRpDpcEnabled[4]; + +/** Offset 0x0AB4 - DPC Extensions PCIE RP Mask + Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit + for each port, bit0 for port1, bit1 for port2, and so on. +**/ + UINT8 CpuPcieRpDpcExtensionsEnabled[4]; + +/** Offset 0x0AB8 - CPU PCIe root port connection type + 0: built-in device, 1:slot +**/ + UINT8 CpuPcieRpSlotImplemented[4]; + +/** Offset 0x0ABC - PCIE RP Gen3 Equalization Phase Method + PCIe Gen3 Eq Ph3 Method (see CPU_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; + 1: hardware equalization; 4: Fixed Coeficients. +**/ + UINT8 CpuPcieRpGen3EqPh3Method[4]; + +/** Offset 0x0AC0 - PCIE RP Gen4 Equalization Phase Method + PCIe Gen4 Eq Ph3 Method (see CPU_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; + 1: hardware equalization; 4: Fixed Coeficients. +**/ + UINT8 CpuPcieRpGen4EqPh3Method[4]; + +/** Offset 0x0AC4 - PCIE RP Physical Slot Number + Indicates the slot number for the root port. Default is the value as root port index. +**/ + UINT8 CpuPcieRpPhysicalSlotNumber[4]; + +/** Offset 0x0AC8 - PCIE RP Aspm + The ASPM configuration of the root port (see: CPU_PCIE_ASPM_CONTROL).0: Disable; + 2: CpuPcieAspmL1(Default) +**/ + UINT8 CpuPcieRpAspm[4]; + +/** Offset 0x0ACC - PCIE RP L1 Substates + The L1 Substates configuration of the root port (see: CPU_PCIE_L1SUBSTATES_CONTROL). + Default is CpuPcieL1SubstatesL1_1_2. +**/ + UINT8 CpuPcieRpL1Substates[4]; + +/** Offset 0x0AD0 - PCIE RP Ltr Enable + Latency Tolerance Reporting Mechanism. +**/ + UINT8 CpuPcieRpLtrEnable[4]; + +/** Offset 0x0AD4 - PCIE RP Ltr Config Lock + 0: Disable; 1: Enable. +**/ + UINT8 CpuPcieRpLtrConfigLock[4]; /** Offset 0x0AD8 - RpPtmBytes **/ UINT8 RpPtmBytes[4]; -/** Offset 0x0ADC - Reserved +/** Offset 0x0ADC - PCIE RP Detect Timeout Ms + The number of milliseconds within 0~65535 in reference code will wait for link to + exit Detect state for enabled ports before assuming there is no device and potentially + disabling the port. **/ - UINT8 Reserved49[16]; + UINT16 CpuPcieRpDetectTimeoutMs[4]; + +/** Offset 0x0AE4 - VC for PCIE RP Mask + Enable/disable Virtual Channel for PCIE Root Ports. 0: disable, 1: enable. One bit + for each port, bit0 for port1, bit1 for port2, and so on. +**/ + UINT8 CpuPcieRpVcEnabled[4]; + +/** Offset 0x0AE8 - Multi-VC for PCIE RP Mask + Enable/disable Multiple Virtual Channel for PCIE Root Ports. 0: disable, 1: enable. + One bit for each port, bit0 for port1, bit1 for port2, and so on. +**/ + UINT8 CpuPcieRpMultiVcEnabled[4]; /** Offset 0x0AEC - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each @@ -2454,9 +3167,29 @@ **/ UINT8 SkipCdClockInit; -/** Offset 0x0B44 - Reserved +/** Offset 0x0B44 - Enable RC1p frequency request to PMA (provided all other conditions are met) + 0(Default)=Disable, 1=Enable + $EN_DIS **/ - UINT8 Reserved50[16]; + UINT8 RC1pFreqEnable; + +/** Offset 0x0B45 - Enable TSN Multi-VC + Enable/disable Multi Virtual Channels(VC) in TSN. + $EN_DIS +**/ + UINT8 PchTsnMultiVcEnable; + +/** Offset 0x0B46 - SaPostMemTestRsvd + Reserved for SA Post-Mem Test + $EN_DIS +**/ + UINT8 SaPostMemTestRsvd[13]; + +/** Offset 0x0B53 - RSR feature + Enable or Disable RSR feature; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnableRsr; /** Offset 0x0B54 - 1-Core Ratio Limit 1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused @@ -2736,9 +3469,11 @@ **/ UINT8 DisableVrThermalAlert; -/** Offset 0x0B82 - Reserved +/** Offset 0x0B82 - Enable or Disable Thermal Reporting + Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. + $EN_DIS **/ - UINT8 Reserved51; + UINT8 EnableAllThermalFunctions; /** Offset 0x0B83 - Enable or Disable Thermal Monitor Enable or Disable Thermal Monitor; 0: Disable; 1: Enable @@ -2874,9 +3609,9 @@ **/ UINT8 StateRatioMax16[16]; -/** Offset 0x0BCF - Reserved +/** Offset 0x0BCF **/ - UINT8 Reserved52; + UINT8 UnusedUpdSpace29; /** Offset 0x0BD0 - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. @@ -3112,18 +3847,40 @@ **/ UINT8 EnableFastMsrHwpReq; -/** Offset 0x0C22 - Reserved +/** Offset 0x0C22 - Enable Configurable TDP + Applies TDP initialization settings based on non-cTDP or cTDP.; 0: Applies to non-cTDP; + 1: Applies to cTDP + $EN_DIS **/ - UINT8 Reserved53[17]; + UINT8 ApplyConfigTdp; + +/** Offset 0x0C23 - Enable VccIn Demotion Override Configuration + Enable VccIn Demotion Override Configuration. The timing can be configured by VccInDemotionMs. + $EN_DIS +**/ + UINT8 VccInDemotionOverride; + +/** Offset 0x0C24 - Customize the VccIn Demotion in ms. + Customize the VccIn Demotion in ms accordingly. Values used by OEM expected to be + in lower end of 1-30 ms range. Value 1 means 1ms, value 2 means 2ms, and so on. + Value 0 will disable VccIn Demotion knob. It's 30ms by silicon default +**/ + UINT32 VccInDemotionMs; + +/** Offset 0x0C28 - ReservedCpuPostMemTest + Reserved for CPU Post-Mem Test + $EN_DIS +**/ + UINT8 ReservedCpuPostMemTest[11]; /** Offset 0x0C33 - SgxSinitDataFromTpm SgxSinitDataFromTpm default values **/ UINT8 SgxSinitDataFromTpm; -/** Offset 0x0C34 - Reserved +/** Offset 0x0C34 **/ - UINT8 Reserved54[16]; + UINT8 SecurityPostMemRsvd[16]; /** Offset 0x0C44 - End of Post message Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): @@ -3255,9 +4012,185 @@ **/ UINT8 MctpBroadcastCycle; -/** Offset 0x0DB9 - Reserved +/** Offset 0x0DB9 **/ - UINT8 Reserved55[239]; + UINT8 UnusedUpdSpace30[1]; + +/** Offset 0x0DBA - PCIE RP Ltr Max Snoop Latency + Latency Tolerance Reporting, Max Snoop Latency. +**/ + UINT16 CpuPcieRpLtrMaxSnoopLatency[4]; + +/** Offset 0x0DC2 - PCIE RP Ltr Max No Snoop Latency + Latency Tolerance Reporting, Max Non-Snoop Latency. +**/ + UINT16 CpuPcieRpLtrMaxNoSnoopLatency[4]; + +/** Offset 0x0DCA - PCIE RP Snoop Latency Override Mode + Latency Tolerance Reporting, Snoop Latency Override Mode. +**/ + UINT8 CpuPcieRpSnoopLatencyOverrideMode[4]; + +/** Offset 0x0DCE - PCIE RP Snoop Latency Override Multiplier + Latency Tolerance Reporting, Snoop Latency Override Multiplier. +**/ + UINT8 CpuPcieRpSnoopLatencyOverrideMultiplier[4]; + +/** Offset 0x0DD2 - PCIE RP Snoop Latency Override Value + Latency Tolerance Reporting, Snoop Latency Override Value. +**/ + UINT16 CpuPcieRpSnoopLatencyOverrideValue[4]; + +/** Offset 0x0DDA - PCIE RP Non Snoop Latency Override Mode + Latency Tolerance Reporting, Non-Snoop Latency Override Mode. +**/ + UINT8 CpuPcieRpNonSnoopLatencyOverrideMode[4]; + +/** Offset 0x0DDE - PCIE RP Non Snoop Latency Override Multiplier + Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. +**/ + UINT8 CpuPcieRpNonSnoopLatencyOverrideMultiplier[4]; + +/** Offset 0x0DE2 - PCIE RP Non Snoop Latency Override Value + Latency Tolerance Reporting, Non-Snoop Latency Override Value. +**/ + UINT16 CpuPcieRpNonSnoopLatencyOverrideValue[4]; + +/** Offset 0x0DEA - PCIE RP Upstream Port Transmiter Preset + Used during Gen3 Link Equalization. Used for all lanes. Default is 7. +**/ + UINT8 CpuPcieRpGen3Uptp[4]; + +/** Offset 0x0DEE - PCIE RP Downstream Port Transmiter Preset + Used during Gen3 Link Equalization. Used for all lanes. Default is 7. +**/ + UINT8 CpuPcieRpGen3Dptp[4]; + +/** Offset 0x0DF2 - PCIE RP Upstream Port Transmiter Preset + Used during Gen4 Link Equalization. Used for all lanes. Default is 8. +**/ + UINT8 CpuPcieRpGen4Uptp[4]; + +/** Offset 0x0DF6 - PCIE RP Downstream Port Transmiter Preset + Used during Gen4 Link Equalization. Used for all lanes. Default is 9. +**/ + UINT8 CpuPcieRpGen4Dptp[4]; + +/** Offset 0x0DFA - PMC C10 dynamic threshold dajustment enable + Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs + $EN_DIS +**/ + UINT8 PmcC10DynamicThresholdAdjustment; + +/** Offset 0x0DFB - FOMS Control Policy + Choose the Foms Control Policy, Default = 0 + 0: Auto, 1: Gen3 Foms, 2: Gen4 Foms, 3: Gen3 and Gen4 Foms +**/ + UINT8 CpuPcieFomsCp[4]; + +/** Offset 0x0DFF +**/ + UINT8 UnusedUpdSpace31; + +/** Offset 0x0E00 - LogoPixelHeight Address + Address of LogoPixelHeight +**/ + UINT32 LogoPixelHeight; + +/** Offset 0x0E04 - LogoPixelWidth Address + Address of LogoPixelWidth +**/ + UINT32 LogoPixelWidth; + +/** Offset 0x0E08 - P2P mode for PCIE RP + Enable/disable peer to peer mode for PCIE Root Ports. 0: Disable, 1: Enable. + 0: Disable, 1: Enable +**/ + UINT8 CpuPcieRpPeerToPeerMode[4]; + +/** Offset 0x0E0C - Map port under VMD + Map/UnMap port under VMD + $EN_DIS +**/ + UINT8 VmdPort[31]; + +/** Offset 0x0E2B - VMD Port Device + VMD Root port device number. +**/ + UINT8 VmdPortDev[31]; + +/** Offset 0x0E4A - VMD Port Func + VMD Root port function number. +**/ + UINT8 VmdPortFunc[31]; + +/** Offset 0x0E69 +**/ + UINT8 UnusedUpdSpace32[3]; + +/** Offset 0x0E6C - VMD Variable + VMD Variable Pointer. +**/ + UINT32 VmdVariablePtr; + +/** Offset 0x0E70 - Thermal Design Current time window + PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. + Range 1ms to 448s +**/ + UINT32 TdcTimeWindow1[5]; + +/** Offset 0x0E84 - Temporary CfgBar address for VMD + PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. + Range 1ms to 448s +**/ + UINT32 VmdCfgBarBase; + +/** Offset 0x0E88 - Temporary MemBar1 address for VMD + PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. + Range 1ms to 448s +**/ + UINT32 VmdMemBar1Base; + +/** Offset 0x0E8C - Temporary MemBar2 address for VMD + PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. + Range 1ms to 448s +**/ + UINT32 VmdMemBar2Base; + +/** Offset 0x0E90 - PCH TSN1 MAC Address High Bits + Set TSN1 MAC Address High. +**/ + UINT32 PchTsn1MacAddressHigh; + +/** Offset 0x0E94 - PCH TSN1 MAC Address Low Bits + Set TSN1 MAC Address Low. +**/ + UINT32 PchTsn1MacAddressLow; + +/** Offset 0x0E98 - FspEventHandler + Optional pointer to the boot loader's implementation of FSP_EVENT_HANDLER. +**/ + UINT32 FspEventHandler; + +/** Offset 0x0E9C - Enable VMD Global Mapping + Enable/disable to VMD controller.0: Disable(Default); 1: Enable + $EN_DIS +**/ + UINT8 VmdGlobalMapping; + +/** Offset 0x0E9D - PCH XHCI LTR Mode Enable + Enable/Disable PCH XHCI LTR Mode.0: Disable; 1: Enable(Default). + $EN_DIS +**/ + UINT8 PchXhciLtrModeEnable; + +/** Offset 0x0E9E +**/ + UINT8 UnusedUpdSpace33[3]; + +/** Offset 0x0EA1 +**/ + UINT8 ReservedFspsUpd[7]; } FSP_S_CONFIG; /** Fsp S UPD Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/54811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I493391294391c1222a1aa5fdb86baad968abf7a6 Gerrit-Change-Number: 54811 Gerrit-PatchSet: 3 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: arch/x86/timestamp.inc: Remove unused file
by Felix Held (Code Review) 28 May '21

28 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55007 ) Change subject: arch/x86/timestamp.inc: Remove unused file ...................................................................... arch/x86/timestamp.inc: Remove unused file This is a romcc compiled bootblock leftover. Change-Id: I8d4f8bcdac7e15d60540157e9d2ac98603320977 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55007 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- D src/arch/x86/timestamp.inc 1 file changed, 0 insertions(+), 23 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/arch/x86/timestamp.inc b/src/arch/x86/timestamp.inc deleted file mode 100644 index 032a011..0000000 --- a/src/arch/x86/timestamp.inc +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * Store the initial timestamp for booting in mmx registers. This works - * because the bootblock isn't being compiled with MMX support so mm1 and - * mm2 will be preserved into romstage. - */ - .code32 - -.global stash_timestamp -stash_timestamp: - - /* Save the BIST value */ - movl %eax, %ebx - - finit - rdtsc - movd %ebx, %mm0 - movd %eax, %mm1 - movd %edx, %mm2 - - /* Restore the BIST value to %eax */ - movl %ebx, %eax -- To view, visit https://review.coreboot.org/c/coreboot/+/55007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d4f8bcdac7e15d60540157e9d2ac98603320977 Gerrit-Change-Number: 55007 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer/var/collis: Update DPTF parameters
by Felix Held (Code Review) 28 May '21

28 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54858 ) Change subject: mb/google/volteer/var/collis: Update DPTF parameters ...................................................................... mb/google/volteer/var/collis: Update DPTF parameters Update the first version DPTF parameters received from the thermal team. BUG=b:188936764 TEST=emerge-volteer coreboot chromeos-bootimage Cq-Depend: chrome-internal:3851737 Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: Id14b1d0bdd48c65eafbdd2e80b4611c86781be00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54858 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/volteer/variants/collis/overridetree.cb 1 file changed, 42 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved Frank Chu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/volteer/variants/collis/overridetree.cb b/src/mainboard/google/volteer/variants/collis/overridetree.cb index fda59e5..00ec738 100644 --- a/src/mainboard/google/volteer/variants/collis/overridetree.cb +++ b/src/mainboard/google/volteer/variants/collis/overridetree.cb @@ -50,6 +50,48 @@ }" device domain 0 on + device ref dptf on + chip drivers/intel/dptf + ## Disable Active Policy + register "policies.active" = "{[0] = {.target=DPTF_NONE}}" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 52, 10000), + [1] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 53, 30000)}" + + ## Power Limits Control + # 7-9W PL1 in 200mW increments, avg over 28-32s interval + # PL2 is fixed at 40W, avg over 28-32s interval + register "controls.power_limits" = "{ + .pl1 = {.min_power = 7000, + .max_power = 9000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}, + .pl2 = {.min_power = 40000, + .max_power = 40000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 2500 }, + [1] = { 24, 1900 }, + [2] = { 16, 1500 }, + [3] = { 8, 1000 }}" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{[0] = {0}}" + + ## Fan options + register "options.fan.fine_grained_control" = "0" + register "options.fan.step_size" = "0" + + device generic 0 on end + end + end device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" -- To view, visit https://review.coreboot.org/c/coreboot/+/54858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id14b1d0bdd48c65eafbdd2e80b4611c86781be00 Gerrit-Change-Number: 54858 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede: Update Storo setting for PEN detection.
by Felix Held (Code Review) 28 May '21

28 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54762 ) Change subject: mb/google/dedede: Update Storo setting for PEN detection. ...................................................................... mb/google/dedede: Update Storo setting for PEN detection. Update devicetree and gpio driving of storo that enable stylus Updates the GPIO configuration for GPP_C12 to PAD_CFG_GPI_GPIO_DRIVER and device tree entry for PENH device to use WAKEUP_ROUTE_GPIO_IRQ. BUG=b:188519508,b:188365033 BRANCH=dedede TEST=build bios and the pen behavior can be detected. Change-Id: I2ffc969569b3ca29ba76326140f958a9707199f7 Signed-off-by: Zanxi Chen <chenzanxi(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54762 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/variants/storo/gpio.c M src/mainboard/google/dedede/variants/storo/overridetree.cb 2 files changed, 15 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/storo/gpio.c b/src/mainboard/google/dedede/variants/storo/gpio.c index 71e78dc..3d830e7 100644 --- a/src/mainboard/google/dedede/variants/storo/gpio.c +++ b/src/mainboard/google/dedede/variants/storo/gpio.c @@ -11,6 +11,9 @@ /* B7 : PCIE_CLKREQ2_N ==> WWAN_SAR_DETECT_ODL*/ PAD_CFG_GPI_IRQ_WAKE(GPP_B7, NONE, DEEP, LEVEL, INVERT), + /* C12 : AP_PEN_DET_ODL */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, UP_20K, DEEP), + /* D15 : EN_PP3300_CAMERA */ PAD_CFG_GPO(GPP_D15, 1, PLTRST), /* D22 : AP_I2C_SUB_SDA*/ diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb index 14eed3d..40b17df 100644 --- a/src/mainboard/google/dedede/variants/storo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb @@ -13,7 +13,7 @@ #| | for TPM communication | #| | before memory is up | #| I2C0 | Trackpad | - #| I2C1 | Digitizer | + #| I2C1 | Digitizer, Stylus | #| I2C2 | Touchscreen | #| I2C3 | Camera | #| I2C4 | Audio | @@ -119,6 +119,17 @@ end end #I2C 0 device pci 15.2 on + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_C12)" + register "key.wakeup_route" = "WAKEUP_ROUTE_GPIO_IRQ" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end chip drivers/i2c/hid register "generic.hid" = ""ELAN9008"" register "generic.desc" = ""ELAN Touchscreen"" -- To view, visit https://review.coreboot.org/c/coreboot/+/54762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ffc969569b3ca29ba76326140f958a9707199f7 Gerrit-Change-Number: 54762 Gerrit-PatchSet: 4 Gerrit-Owner: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/amd/bilby,cereme,mandolin: change PSPP policy to balanced
by Felix Held (Code Review) 28 May '21

28 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54935 ) Change subject: mb/amd/bilby,cereme,mandolin: change PSPP policy to balanced ...................................................................... mb/amd/bilby,cereme,mandolin: change PSPP policy to balanced Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7571ed92b3c3fa79581e2c7342960ca31451af1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54935 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/amd/bilby/devicetree.cb M src/mainboard/amd/mandolin/variants/cereme/devicetree.cb M src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb 3 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/mainboard/amd/bilby/devicetree.cb b/src/mainboard/amd/bilby/devicetree.cb index 7797c3e..8adbaa2 100644 --- a/src/mainboard/amd/bilby/devicetree.cb +++ b/src/mainboard/amd/bilby/devicetree.cb @@ -136,7 +136,7 @@ register "gpp_clk_config[5]" = "GPP_CLK_REQ" register "gpp_clk_config[6]" = "GPP_CLK_REQ" - register "pspp_policy" = "DXIO_PSPP_POWERSAVE" + register "pspp_policy" = "DXIO_PSPP_BALANCED" device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb index 9a3e78e..f82f958 100644 --- a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb @@ -136,7 +136,7 @@ register "gpp_clk_config[5]" = "GPP_CLK_OFF" register "gpp_clk_config[6]" = "GPP_CLK_OFF" - register "pspp_policy" = "DXIO_PSPP_POWERSAVE" + register "pspp_policy" = "DXIO_PSPP_BALANCED" device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index 826a84b..c82f388 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -136,7 +136,7 @@ register "gpp_clk_config[5]" = "GPP_CLK_REQ" register "gpp_clk_config[6]" = "GPP_CLK_REQ" - register "pspp_policy" = "DXIO_PSPP_POWERSAVE" + register "pspp_policy" = "DXIO_PSPP_BALANCED" device cpu_cluster 0 on device lapic 0 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/54935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7571ed92b3c3fa79581e2c7342960ca31451af1f Gerrit-Change-Number: 54935 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: arch/x86/acpi_bert_storage: change return type of bert_errors_present
by Felix Held (Code Review) 28 May '21

28 May '21

Attention is currently required from: Angel Pons. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55023 ) Change subject: arch/x86/acpi_bert_storage: change return type of bert_errors_present ...................................................................... Patch Set 4: (1 comment) File src/arch/x86/acpi_bert_storage.c: https://review.coreboot.org/c/coreboot/+/55023/comment/2b6bcc3f_8ac1c3dc PS3, Line 38: !! > the double negation is not needed. as expected the resulting binary stays the same in a timeless build -- To view, visit https://review.coreboot.org/c/coreboot/+/55023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13d6472deeb26ba92d257761df069e32d9b2e5d4 Gerrit-Change-Number: 55023 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 28 May 2021 18:15:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/acpi_bert_storage: change return type of bert_errors_present
by Felix Held (Code Review) 28 May '21

28 May '21

Attention is currently required from: Felix Held. Hello build bot (Jenkins), Paul Menzel, Angel Pons, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55023 to look at the new patch set (#4). Change subject: arch/x86/acpi_bert_storage: change return type of bert_errors_present ...................................................................... arch/x86/acpi_bert_storage: change return type of bert_errors_present The return value is a boolean, so use the bool type. Also add the types.h header to have the bool type defined. Also change type of bert_region_broken static variable to bool. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I13d6472deeb26ba92d257761df069e32d9b2e5d4 --- M src/arch/x86/acpi_bert_storage.c M src/arch/x86/include/arch/bert_storage.h 2 files changed, 8 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/55023/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/55023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13d6472deeb26ba92d257761df069e32d9b2e5d4 Gerrit-Change-Number: 55023 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021