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Change subject: configs: Update configs for OCP Delta Lake for coreboot/LinuxBoot
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55058/comment/5c2128c1_bc1cda7e
PS1, Line 12: Linux OS
Nit: GNU/Linux
Would be nice if you mentioned the distribution.
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Change subject: configs: Update configs for OCP Delta Lake for coreboot/LinuxBoot
......................................................................
Patch Set 1:
(4 comments)
File configs/builder/config.ocp.deltalake:
https://review.coreboot.org/c/coreboot/+/55058/comment/beb3e59d_e7ff3b35
PS1, Line 10: CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
Please also mention this in the commit message.
https://review.coreboot.org/c/coreboot/+/55058/comment/5c09d19c_21ad0142
PS1, Line 23: CONFIG_CONSOLE_SERIAL_57600=y
Please mention in the commit message, why that speed is selected.
https://review.coreboot.org/c/coreboot/+/55058/comment/a709cda8_2a73c605
PS1, Line 24: CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4=y
Please mention in the commit message, why the reduced log level is useful.
https://review.coreboot.org/c/coreboot/+/55058/comment/7046acc1_0fbc770a
PS1, Line 26: CONFIG_PAYLOAD_FILE="site-local/deltalake/linuxboot_uroot_ttys0"
Is that file present on the builder?
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Change subject: mb/adl: Update power limits with SKU specific values
......................................................................
Patch Set 4:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/54926/comment/2c68d3ee_32c7404b
PS4, Line 8:
Please state the problem. Something like:
> Currently, only one power limit entry is hard-coded, which is only correct for for google/brya (282), and incorrect for other SKUs.
https://review.coreboot.org/c/coreboot/+/54926/comment/3824d87b_5b0c93b5
PS4, Line 9: CL 54676
CB:54676
Maybe even reference the Change-Id.
https://review.coreboot.org/c/coreboot/+/54926/comment/347d3b64_9a39147f
PS4, Line 10: alderlake
Alder Lake
https://review.coreboot.org/c/coreboot/+/54926/comment/9586fecc_54b97eb2
PS4, Line 11: entries
Singular: entry?
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Change subject: soc/intel/adl: Add SKU specific power limits support
......................................................................
Patch Set 6:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/54676/comment/7cb6cd41_6c79ef62
PS6, Line 9: depends
depend
https://review.coreboot.org/c/coreboot/+/54676/comment/d804eaaa_1dbcf7d4
PS6, Line 11: and
remove
File src/soc/intel/alderlake/systemagent.c:
https://review.coreboot.org/c/coreboot/+/54676/comment/63aeedfa_079c5ea0
PS6, Line 63: sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF;
Move the assignments right before the switch statement?
https://review.coreboot.org/c/coreboot/+/54676/comment/d290c62f_0ef93c65
PS6, Line 78: */
You might want to use the concise style:
/* Choose a power limits configuration based on the SoC SKU type,
differentiated here based on SA PCI ID. */
https://review.coreboot.org/c/coreboot/+/54676/comment/6518d8eb_c7e247a2
PS6, Line 94: "configuration\n", sa_pci_id);
Please put the string on one line.
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Change subject: src/... - Add Boot Guard support
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55048/comment/cc57c28d_68d78a24
PS3, Line 7: src/... - Add Boot Guard support
Please use:
> src: Add Intel Boot Guard support
or
> intel: Add Boot Guard support
https://review.coreboot.org/c/coreboot/+/55048/comment/d8dfd0a7_72da2e8b
PS3, Line 10: src/mainboard/prodrive/hermes/Kconfig - Add FIX_BOOTBLOCK_SIZE
Please do this in a separate commit.
https://review.coreboot.org/c/coreboot/+/55048/comment/56a0a8d2_5b9d6f7d
PS3, Line 12:
Instead of listing the paths, could you please reference the documentation needed for the implementation, and if possible summarize what Intel Boot Guard does, and what coreboot needs to do to implement it.
Documenting it in `Documentation/` would be even better.
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Change subject: src/intel/xeon_sp: add hardware error support (HEST)
......................................................................
Patch Set 19:
(2 comments)
File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/52090/comment/3e6b7f45_3bef4771
PS18, Line 149: * +--------------------------+ cbmem_top
: * | HEST ELOG | (CONFIG_ERROR_LOG_BUFFER_SIZE)
: * +--------------------------+
> 1. Done...corrected the map so that HEST ELOG is above cbmem_top.
> 2. Yes, it cannot be part of CBMEM because in the E820 table, CBMEM is labeled as type16 memory (Unknown to the OS) and therefore ACPI drivers fail to acknowledge this memory and generate ACPI errors, unable to load HEST.
type16? That's probably an error in the Linux trampoline then? It should be type 2. I'll try to figure out what is going on there.
File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/52090/comment/2fde047b_6cfeb0aa
PS19, Line 96: const uintptr_t cbmem_top_mb = ALIGN_UP((uintptr_t)cbmem_top(), MiB) / MiB;
It will conflict with DPR.
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Change subject: mb/google/dedede/var/sasukette: Modify the touch pad slave address
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55035/comment/6957f340_7249e3ba
PS1, Line 10: It will cause one of the touch pad hid identification error.
Please paste that error, and summarize the bug report.
https://review.coreboot.org/c/coreboot/+/55035/comment/8de4ba17_ca8106bb
PS1, Line 14: TEST=Verify OK
Please be more specific.
https://review.coreboot.org/c/coreboot/+/55035/comment/bd8a5da0_da0cb7d2
PS1, Line 17: Change-Id: I09bc12eeca7f34f6e9424e5cbb7f812f3bbfe0de
Please remove this line, as the Change-Id below is used. (Please also remove the blank line.)
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Change subject: [WIP]Allow to build romstage sources inside the bootblock
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55068/comment/cb8aa6e4_c918eecb
PS1, Line 9: H
> or when the romstage is too large because it doesn't call into an external blob ;-)
A large romstage inside the bootblock is not an issue if there are no size limitations. This now the case for most x86 targets.
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Change subject: use initial_lapicid() instead of opencoding it
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Build error is:
src/soc/intel/xeon_sp/smmrelocate.c: In function 'update_save_state':
src/soc/intel/xeon_sp/smmrelocate.c:90:6: error: unused variable 'apic_id' [-Werror=unused-variable]
int apic_id;
^~~~~~~
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55067 )
Change subject: arch/x86: Add a common romstage entry
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
CC bootblock/lib/prog_loaders.o
src/lib/prog_loaders.c:19:10: fatal error: romstage_common.h: No such file or directory
#include <romstage_common.h>
^~~~~~~~~~~~~~~~~~~
compilation terminated.
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