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Change subject: mb/google/dedede: Bump mainboard mem version
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Idwer Vollering has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55039 )
Change subject: util/cbfstool/flashmap/fmap.c: fix fmaptool endianness bugs on BE
......................................................................
Patch Set 2:
(1 comment)
File util/cbfstool/flashmap/fmap.c:
https://review.coreboot.org/c/coreboot/+/55039/comment/f49acd45_1c8596b6
PS2, Line 18: #include <commonlib/endian.h>
For portability reasons, can you change this to include commonlib/bsd/sysincludes.h instead?
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Change subject: [NOTFORMERGE]link Agesa into bootblock
......................................................................
Patch Set 1:
(1 comment)
File src/drivers/amd/agesa/bootblock.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120279):
https://review.coreboot.org/c/coreboot/+/55070/comment/18db0291_eeef764c
PS1, Line 47: void (*ap_romstage_entry)(void) = get_ap_entry_ptr();
function definition argument 'void' should also have an identifier name
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Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55070 )
Change subject: [NOTFORMERGE]link Agesa into bootblock
......................................................................
[NOTFORMERGE]link Agesa into bootblock
Untested but it does seem to build for AGESA targets.
For AGESA targets the APs are started by the BSP in romstage and need
to jump past the bootblock into the romstage. When there is a separate
romstage this is complicated as the APs in boot need to know where
to jump in romstage. This is done by setting a pointer in BIOSRAM.
When the romstage is linked inside the bootblock there is no need for
such tricks as the symbol for the AP jump address can directly be
referenced.
Change-Id: Ic4c71b9c9a245e07d713839fb3628cbfc0dc3457
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/Kconfig
M src/arch/x86/bootblock.ld
M src/arch/x86/car.ld
M src/cpu/amd/agesa/Kconfig
M src/drivers/amd/agesa/bootblock.c
M src/drivers/amd/agesa/romstage.c
M src/northbridge/amd/agesa/agesa_helper.h
M src/vendorcode/amd/agesa/Makefile.inc
8 files changed, 28 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/55070/1
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index a488b55..4e7d799 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -189,7 +189,7 @@
config C_ENV_BOOTBLOCK_SIZE
hex
- default 0x40000 if !FIXED_BOOTBLOCK_SIZE
+ default 0x100000 if !FIXED_BOOTBLOCK_SIZE
help
This is only the default maximum of bootblock size for linking
purposes. Platforms may provide different limit and need to
diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld
index 3cd0900..b66f1cc 100644
--- a/src/arch/x86/bootblock.ld
+++ b/src/arch/x86/bootblock.ld
@@ -22,6 +22,11 @@
_bootblock = .;
+.data . : {
+ *(.data);
+ *(.data.*);
+}
+
INCLUDE "bootblock/lib/program.ld"
/*
@@ -29,7 +34,7 @@
* may cause the total size of a section to change when the start
* address gets applied.
*/
- PROGRAM_SZ = SIZEOF(.text) + 512;
+ PROGRAM_SZ = SIZEOF(.text) + 512 + SIZEOF(.data);
. = MIN(_ID_SECTION, _FIT_POINTER) - EARLYASM_SZ;
. = CONFIG(SIPI_VECTOR_IN_ROM) ? ALIGN(4096) : ALIGN(16);
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
index 5a46b8b..39c9305 100644
--- a/src/arch/x86/car.ld
+++ b/src/arch/x86/car.ld
@@ -115,8 +115,8 @@
. = 0xffffff00;
.illegal_globals . : {
- *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
- *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
+ *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/bootblock*/buildOpts.o" "*/bootblock*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
+ *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/bootblock*/buildOpts.o" "*/bootblock*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
}
_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index 51b61a1..7ce80fb 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -47,7 +47,7 @@
config S3_DATA_POS
hex
- default 0xFFFF0000
+ default 0xFFF00000
config S3_DATA_SIZE
int
diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c
index df9876a..c8e4330 100644
--- a/src/drivers/amd/agesa/bootblock.c
+++ b/src/drivers/amd/agesa/bootblock.c
@@ -8,6 +8,7 @@
#include <cpu/amd/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/lapic.h>
+#include <northbridge/amd/agesa/agesa_helper.h>
#define EARLY_VMTRR_FLASH 6
@@ -42,7 +43,13 @@
if (CONFIG(UDELAY_LAPIC))
enable_lapic();
- void (*ap_romstage_entry)(void) = get_ap_entry_ptr();
- ap_romstage_entry(); /* execution does not return */
+ if (CONFIG(SEPARATE_ROMSTAGE)) {
+ void (*ap_romstage_entry)(void) = get_ap_entry_ptr();
+ ap_romstage_entry(); /* execution does not return */
+ } else {
+ /* We can just call that function directly as romstage symbols
+ are in the bootblock */
+ ap_romstage_main();
+ }
halt();
}
diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c
index 6255970..f00aaab 100644
--- a/src/drivers/amd/agesa/romstage.c
+++ b/src/drivers/amd/agesa/romstage.c
@@ -27,11 +27,6 @@
agesa_set_interface(cb);
}
-/* APs will enter directly here from bootblock, bypassing verstage
- * and potential fallback / normal bootflow detection.
- */
-static void ap_romstage_main(void);
-
void romstage_main(void)
{
struct postcar_frame pcf;
@@ -79,7 +74,10 @@
/* We do not return. */
}
-static void ap_romstage_main(void)
+/* APs will enter directly here from bootblock, bypassing verstage
+ * and potential fallback / normal bootflow detection.
+ */
+void ap_romstage_main(void)
{
struct sysinfo romstage_state;
struct sysinfo *cb = &romstage_state;
diff --git a/src/northbridge/amd/agesa/agesa_helper.h b/src/northbridge/amd/agesa/agesa_helper.h
index 120e74a..08ca68e 100644
--- a/src/northbridge/amd/agesa/agesa_helper.h
+++ b/src/northbridge/amd/agesa/agesa_helper.h
@@ -42,4 +42,6 @@
void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size);
const void *OemS3Saved_MTRR_Storage(void);
+void ap_romstage_main(void);
+
#endif /* _AGESA_HELPER_H_ */
diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc
index b96af84..68d9b8c 100644
--- a/src/vendorcode/amd/agesa/Makefile.inc
+++ b/src/vendorcode/amd/agesa/Makefile.inc
@@ -27,13 +27,16 @@
@printf " AGESA $(subst $(obj)/,,$(@))\n"
$(AR_libagesa) rcsDT $@ $+
+bootblock-libs += $(obj)/libagesa.a
romstage-libs += $(obj)/libagesa.a
ramstage-libs += $(obj)/libagesa.a
# buildOpts should be in libagesa
+$(obj)/bootblock/mainboard/$(MAINBOARDDIR)/buildOpts.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES)
$(obj)/romstage/mainboard/$(MAINBOARDDIR)/buildOpts.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES)
$(obj)/ramstage/mainboard/$(MAINBOARDDIR)/buildOpts.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES)
+$(obj)/bootblock/vendorcode/amd/agesa/common/agesa-entry.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES)
$(obj)/romstage/vendorcode/amd/agesa/common/agesa-entry.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES)
$(obj)/ramstage/vendorcode/amd/agesa/common/agesa-entry.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES)
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zanxi chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54249 )
Change subject: mb/google/dedede/var/blipper: Configure I2C times for touchpad/touchpanel/codec
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/54249/comment/f84ae58a_ce57459f
PS3, Line 15: audio codec RT5682: 385 kHz
> Do you also have the values before the patch? If yes, please add them too.
Hi Paul,
I don't understand the values you mentioned. Please tell me more about it and where should I add them(commit message/code).
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55068 )
Change subject: [WIP]Allow to build romstage sources inside the bootblock
......................................................................
Patch Set 1:
(3 comments)
File src/drivers/amd/agesa/def_callouts.c:
https://review.coreboot.org/c/coreboot/+/55068/comment/7782f079_52671ba7
PS1, Line 132: if (!(ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE)))
> Would defining both `ENV_BOOTBLOCK` and `ENV_ROMSTAGE` for the combined stage work? Or does existing code rely on the assumption that they're mutually exclusive?
I thought the linker scripts would disagree but that was easy to fix :-)
File src/lib/prog_loaders.c:
https://review.coreboot.org/c/coreboot/+/55068/comment/69bf7d5d_d6114b82
PS1, Line 19: #include <romstage_common.h>
> x86-specific, apparently.
Hence the WIP
File src/southbridge/intel/bd82x6x/early_pch.c:
https://review.coreboot.org/c/coreboot/+/55068/comment/193612e0_ec861e55
PS1, Line 313: if (ENV_ROMSTAGE || (ENV_BOOTBLOCK && !CONFIG(SEPARATE_ROMSTAGE)))
> This guard exists because this function is called twice: once in bootblock, once in romstage. I had some patches to clean it up, but they're probably stale by now...
>
> src/southbridge/intel/bd82x6x/bootblock.c: early_pch_init();
> src/northbridge/intel/sandybridge/romstage.c: early_pch_init();
Yeah that needs to be fixed. That was done for some weird compatibility reasons but there is no need for that anymore.
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Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Philipp Hug, Patrick Georgi, ron minnich, Subrata Banik, Julius Werner, Andrey Petrov, Aaron Durbin, Patrick Rudolph, Piotr Król, Jason Glenesk, Michał Żygowski, Martin Roth, Marshall Dawson, Ron Minnich, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/55068
to look at the new patch set (#2).
Change subject: [WIP]Allow to build romstage sources inside the bootblock
......................................................................
[WIP]Allow to build romstage sources inside the bootblock
Having a separate romstage is only desirable:
- with advanced setups like vboot or normal/fallback
- boot medium is slow at startup (some ARM SOCs)
- bootblock is limited in size (Intel APL 32K)
When this is not the case there is no need for the extra complexity
that romstage brings. Including the romstage sources inside the
bootblock substantially reduces the total code footprint. Often the
resulting code is 10-20k smaller.
For now this feature is x86 only, but it would be easy to change that
for other arch.
TODO make this option only visible when it makes sense
TESTED: works on qemu x86
Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M Makefile.inc
M src/Kconfig
M src/arch/x86/Makefile.inc
M src/include/memlayout.h
M src/include/rules.h
M src/lib/prog_loaders.c
6 files changed, 20 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/55068/2
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