coreboot-gerrit April 2021

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Change in coreboot[master]: vc/eltan/security/mboot/Kconfig: Add dependency of VBOOT
by Frans Hendriks (Code Review) 01 Apr '21

01 Apr '21

Attention is currently required from: Wim Vervoorn. Hello Wim Vervoorn, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52021 to look at the new patch set (#2). Change subject: vc/eltan/security/mboot/Kconfig: Add dependency of VBOOT ...................................................................... vc/eltan/security/mboot/Kconfig: Add dependency of VBOOT VENDORCODE_ELTAN_MBOOT should not be used when VBOOT is enabled. Hide VENDOCODE_ELTAN_MBOOT when VBOOT is enabled. BUG = N/A TEST = run `make menuconfig` and boot Facebook FBG1701 Change-Id: Iac57103431cc7efac5b6019f180572d255e683ab Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/vendorcode/eltan/security/mboot/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/52021/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac57103431cc7efac5b6019f180572d255e683ab Gerrit-Change-Number: 52021 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vc/eltan/security/mboot/Kconfig: Add dependency of VBOOT
by Frans Hendriks (Code Review) 01 Apr '21

01 Apr '21

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52021 ) Change subject: vc/eltan/security/mboot/Kconfig: Add dependency of VBOOT ...................................................................... vc/eltan/security/mboot/Kconfig: Add dependency of VBOOT VENDORCODE_ELTAN_MBOOT should not be used when VBOOT is enabled. Hide VENDOCODE_ELTAN_MBOOT when VBOOT is enabled. BUG = N/A TEST = run `make menuconfig` and boot Facebook FBG1701 vc/eltan/security/mboot/Kconfig: Add dependency of VBOOT VENDORCODE_ELTAN_MBOOT can be enabled when VBOOT is enabled. Hide VENDOCODE_ELTAN_MBOOT when VBOOT is enabled. Change-Id: Iac57103431cc7efac5b6019f180572d255e683ab Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/vendorcode/eltan/security/mboot/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/52021/1 diff --git a/src/vendorcode/eltan/security/mboot/Kconfig b/src/vendorcode/eltan/security/mboot/Kconfig index 540b7b2..4e30cf5 100644 --- a/src/vendorcode/eltan/security/mboot/Kconfig +++ b/src/vendorcode/eltan/security/mboot/Kconfig @@ -4,6 +4,7 @@ config VENDORCODE_ELTAN_MBOOT bool "Measure firmware with mboot." + depends on !VBOOT default n select VBOOT_LIB help -- To view, visit https://review.coreboot.org/c/coreboot/+/52021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac57103431cc7efac5b6019f180572d255e683ab Gerrit-Change-Number: 52021 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] alderlake: enable DPTF functionality for ADL-RVP board
by Sumeet R Pawnikar (Code Review) 01 Apr '21

01 Apr '21

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52020 ) Change subject: [WIP] alderlake: enable DPTF functionality for ADL-RVP board ...................................................................... [WIP] alderlake: enable DPTF functionality for ADL-RVP board Enable DPTF functionality for alderlake based ADL-RVP board BRANCH=None BUG=None TEST=Built for adlrvp and tested on adlrvp board Change-Id: I319bb0ddb9cd9bbe48c8ee09c2742a78da230b7b Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/drivers/intel/dptf/dptf.c M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/devicetree.cb 3 files changed, 73 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/52020/1 diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index 1713e72..d816847 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -18,9 +18,17 @@ #define GENERIC_HID_EISAID "INT3403" #define FAN_HID_EISAID "INT3404" +#if 0 +/* Below are ACPI IDs for Tiger Lake SoC */ #define DPTF_DEVICE_HID "INTC1040" #define GENERIC_HID "INTC1043" #define FAN_HID "INTC1044" +#endif + +/* Below are ACPI IDs for Alder Lake SoC */ +#define DPTF_DEVICE_HID "INTC1041" +#define GENERIC_HID "INTC1046" +#define FAN_HID "INTC1048" /* * Helper method to determine if a device is "used" (called out anywhere as a source or a target diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index c1c4586..8a64e49 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -10,6 +10,7 @@ select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC select DRIVERS_INTEL_SOUNDWIRE + select DRIVERS_INTEL_DPTF select DRIVERS_INTEL_PMC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC select DRIVERS_USB_ACPI select DRIVERS_SPI_ACPI diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index cade987..dc531d5 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -132,6 +132,12 @@ register "TcssAuxOri" = "0" register "s0ix_enable" = "1" + register "dptf_enable" = "1" + + register "power_limits_config" = "{ + .tdp_pl1_override = 45, + .tdp_pl2_override = 56, + }" register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -209,7 +215,64 @@ device pci 00.0 on end # Host Bridge device pci 01.0 on end # PEG10 device pci 02.0 on end # Graphics - device pci 04.0 on end # DPTF + device pci 04.0 on + chip drivers/intel/dptf + + ## sensor information + register "options.tsr[0].desc" = ""Ambient"" + register "options.tsr[1].desc" = ""Battery"" + register "options.tsr[2].desc" = ""DDR"" + register "options.tsr[3].desc" = ""Skin"" + + ## Passive Policy + # TODO: below values are initial reference values only + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 10000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 50000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 50000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 50000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 85, 50000), + }" + + ## Critical Policy + # TODO: below values are initial reference values only + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 95, SHUTDOWN), + }" + + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 35000, + .max_power = 45000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 56000, + .max_power = 56000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + device generic 0 on end + end + end # DPTF device pci 05.0 on end # IPU device pci 06.0 on end # PEG60 device pci 06.2 on end # PEG62 -- To view, visit https://review.coreboot.org/c/coreboot/+/52020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I319bb0ddb9cd9bbe48c8ee09c2742a78da230b7b Gerrit-Change-Number: 52020 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Add entry for PSP NVRAM data & RPMC data
by ritul guru (Code Review) 01 Apr '21

01 Apr '21

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held. ritul guru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51836 ) Change subject: soc/amd/picasso: Add entry for PSP NVRAM data & RPMC data ...................................................................... Patch Set 8: (1 comment) File src/soc/amd/picasso/fw.cfg: https://review.coreboot.org/c/coreboot/+/51836/comment/0f835902_96aa3534 PS8, Line 9: PSPNVRAM_FILE How will we access these regions without names? like RPMC/PSP_NVRAM region is read/write, when access TA apps request read/write access to PSP which trigger smi to coreboot to access SPI accordingly. -- To view, visit https://review.coreboot.org/c/coreboot/+/51836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e0c9d651b7c544eabbed8acc0d26ae55960ca3f Gerrit-Change-Number: 51836 Gerrit-PatchSet: 8 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 01 Apr 2021 11:28:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: add new driver 'msdc' for eMMC
by Wenbin Mei (Code Review) 01 Apr '21

01 Apr '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Wenbin Mei has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51966 ) Change subject: soc/mediatek: add new driver 'msdc' for eMMC ...................................................................... Patch Set 5: (3 comments) File src/soc/mediatek/common/msdc.c: https://review.coreboot.org/c/coreboot/+/51966/comment/e71b31ea_db4bb7c9 PS4, Line 61: > space Ack https://review.coreboot.org/c/coreboot/+/51966/comment/6cb45b45_b2ce0e96 PS4, Line 133: MSDC_PAD_TUNE_CMD_SEL > Move to the previous line Done https://review.coreboot.org/c/coreboot/+/51966/comment/e8f335a8_2fbf3a62 PS4, Line 459: "%s > Align with BIOS_ERR Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/51966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54a7749ed167c00cd631a76af7c67c654c7bc725 Gerrit-Change-Number: 51966 Gerrit-PatchSet: 5 Gerrit-Owner: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 01 Apr 2021 11:01:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/asurada: early-init eMMC
by Wenbin Mei (Code Review) 01 Apr '21

01 Apr '21

Attention is currently required from: Paul Menzel, Yu-Ping Wu. Wenbin Mei has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51973 ) Change subject: mb/google/asurada: early-init eMMC ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/asurada/mainboard.c: https://review.coreboot.org/c/coreboot/+/51973/comment/388bf9b4_4a28b491 PS2, Line 29: > Use tabs for alignment Done -- To view, visit https://review.coreboot.org/c/coreboot/+/51973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f58d203e969dc1a13a479d7dc63b1b162a9ae3f Gerrit-Change-Number: 51973 Gerrit-PatchSet: 3 Gerrit-Owner: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 01 Apr 2021 11:00:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/asurada: early-init eMMC
by Wenbin Mei (Code Review) 01 Apr '21

01 Apr '21

Attention is currently required from: Paul Menzel, Wenbin Mei. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51973 to look at the new patch set (#3). Change subject: mb/google/asurada: early-init eMMC ...................................................................... mb/google/asurada: early-init eMMC Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to access eMMC in the very early stage (for example, Depthcharge needs it 20ms after started) so we have to start initialization in coreboot. On Hayato Chromebook this can save ~100ms in total. BUG=b:177389446 TEST=emerge-asurada coreboot BRANCH=asurada Signed-off-by: Wenbin Mei <wenbin.mei(a)mediatek.com> Change-Id: I2f58d203e969dc1a13a479d7dc63b1b162a9ae3f --- M src/mainboard/google/asurada/mainboard.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/51973/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/51973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f58d203e969dc1a13a479d7dc63b1b162a9ae3f Gerrit-Change-Number: 51973 Gerrit-PatchSet: 3 Gerrit-Owner: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: add new driver 'msdc' for eMMC
by Wenbin Mei (Code Review) 01 Apr '21

01 Apr '21

Attention is currently required from: Hung-Te Lin, Wenbin Mei. Hello Hung-Te Lin, Xi Chen, build bot (Jenkins), Patrick Georgi, Martin Roth, Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51966 to look at the new patch set (#5). Change subject: soc/mediatek: add new driver 'msdc' for eMMC ...................................................................... soc/mediatek: add new driver 'msdc' for eMMC Add MTK host mmc driver support. MTK host controller support eMMC5.1 spec. BUG=b:177389446 TEST=emerge-asurada coreboot BRANCH=asurada Signed-off-by: Wenbin Mei <wenbin.mei(a)mediatek.com> Change-Id: I54a7749ed167c00cd631a76af7c67c654c7bc725 --- M src/commonlib/include/commonlib/sd_mmc_ctrlr.h A src/soc/mediatek/common/include/soc/msdc.h A src/soc/mediatek/common/msdc.c M src/soc/mediatek/mt8192/Makefile.inc 4 files changed, 685 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/51966/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/51966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54a7749ed167c00cd631a76af7c67c654c7bc725 Gerrit-Change-Number: 51966 Gerrit-PatchSet: 5 Gerrit-Owner: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: device/i2c_bus.c: Correct code style
by Angel Pons (Code Review) 01 Apr '21

01 Apr '21

Attention is currently required from: Frans Hendriks. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50190 ) Change subject: device/i2c_bus.c: Correct code style ...................................................................... Patch Set 3: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/50190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78ce97b0ce1587119a71893c867c2dd062552a31 Gerrit-Change-Number: 50190 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Comment-Date: Thu, 01 Apr 2021 10:21:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: device/i2c_bus.c: Correct code style
by Wim Vervoorn (Code Review) 01 Apr '21

01 Apr '21

Attention is currently required from: Frans Hendriks. Wim Vervoorn has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50190 ) Change subject: device/i2c_bus.c: Correct code style ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78ce97b0ce1587119a71893c867c2dd062552a31 Gerrit-Change-Number: 50190 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Comment-Date: Thu, 01 Apr 2021 10:20:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2021