coreboot-gerrit April 2021

coreboot-gerrit@coreboot.org

1 participants
6269 discussions

Change in coreboot[master]: soc/mediatek: add new driver 'msdc' for eMMC
by Yu-Ping Wu (Code Review) 01 Apr '21

01 Apr '21

Attention is currently required from: Hung-Te Lin, Wenbin Mei. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51966 ) Change subject: soc/mediatek: add new driver 'msdc' for eMMC ...................................................................... Patch Set 4: (38 comments) File src/commonlib/include/commonlib/sd_mmc_ctrlr.h: https://review.coreboot.org/c/coreboot/+/51966/comment/47c62757_7ab5fe12 PS2, Line 15: MMC_CMD1_READY > I think you tried to use -1 as well, so let's add […] Done File src/mainboard/google/asurada/Kconfig: https://review.coreboot.org/c/coreboot/+/51966/comment/5f94fa52_15018f11 PS3, Line 33: select COMMONLIB_STORAGE_MMC > Please do the board changes in a separate commit. Done File src/mainboard/google/asurada/mainboard.c: https://review.coreboot.org/c/coreboot/+/51966/comment/0b47294e_b2ea2ddd PS2, Line 23: #include <commonlib/storage/sd_mmc.h> : #include <commonlib/sd_mmc_ctrlr.h> : #include <commonlib/storage.h> : #include <cbmem.h> : #include <soc/msdc.h> > Sort Ack https://review.coreboot.org/c/coreboot/+/51966/comment/77ba8534_8e14826c PS2, Line 33: > Align using tabs Ack https://review.coreboot.org/c/coreboot/+/51966/comment/2bedcb15_471850eb PS2, Line 242: i > I Done https://review.coreboot.org/c/coreboot/+/51966/comment/35e1b1f4_5d833dff PS2, Line 247: 400*1000 > 400 * 1000 Done File src/soc/mediatek/common/include/soc/msdc.h: https://review.coreboot.org/c/coreboot/+/51966/comment/ba6a3f7f_fb032be6 PS3, Line 2: #ifndef __MSDC_H_ > Please add a blank line above. Done File src/soc/mediatek/common/include/soc/msdc.h: https://review.coreboot.org/c/coreboot/+/51966/comment/b4887896_aa11dcee PS2, Line 167: min > MIN() is already defined in commonlib/bsd/include/commonlib/bsd/helpers. […] Done File src/soc/mediatek/common/msdc.c: https://review.coreboot.org/c/coreboot/+/51966/comment/e854e075_298f20dd PS2, Line 24: * > Remove this Done https://review.coreboot.org/c/coreboot/+/51966/comment/b2a57634_15070b0d PS2, Line 25: msdc_poll_timeout - > No need for this Done https://review.coreboot.org/c/coreboot/+/51966/comment/b250fecc_3309c32c PS2, Line 31: > Extra blank line Done https://review.coreboot.org/c/coreboot/+/51966/comment/3578a001_4fa9b6bc PS2, Line 35: status > This is always NULL in all calls. Done https://review.coreboot.org/c/coreboot/+/51966/comment/d19b6325_e6301ef1 PS2, Line 42: timeout == 0 > Use "!--timeout" as in msdc_wait_done(). Done https://review.coreboot.org/c/coreboot/+/51966/comment/74cd12d2_74f9718b PS2, Line 43: 0x%x > %#x Ack https://review.coreboot.org/c/coreboot/+/51966/comment/2b8b58d5_d45fc9d1 PS2, Line 43: 0x%x > %#x Ack https://review.coreboot.org/c/coreboot/+/51966/comment/8d9ba35b_0b7f438d PS2, Line 58: /* This is a private function to wait for a bit mask in a given register */ : /* To avoid endless loops, a time-out is implemented here. */ > Format: […] Done https://review.coreboot.org/c/coreboot/+/51966/comment/33f1a079_5b921e47 PS2, Line 65: if (reg & mask) : goto end; > This can be removed if we replace the do-while loop with while-do loop. Done https://review.coreboot.org/c/coreboot/+/51966/comment/d929b81d_d2668425 PS2, Line 77: > space Done https://review.coreboot.org/c/coreboot/+/51966/comment/622bf46a_a1468cc3 PS2, Line 120: MSDC_PATCH_BIT1_STOP_DLY > Align with "host->base". Same below. Done https://review.coreboot.org/c/coreboot/+/51966/comment/30aeb1db_a2889138 PS2, Line 129: MSDC_PB2_RESPWAIT, 3); > Fit in one line Done https://review.coreboot.org/c/coreboot/+/51966/comment/883fe18f_c0c57f94 PS2, Line 136: u > U Done https://review.coreboot.org/c/coreboot/+/51966/comment/eaef07a4_df9ffc66 PS2, Line 136: need > need to Done https://review.coreboot.org/c/coreboot/+/51966/comment/db9e49a1_0bdc5467 PS2, Line 138: MSDC_PATCH_BIT2_CFGRESP); > Fit in one line Done https://review.coreboot.org/c/coreboot/+/51966/comment/39e5ebae_3582cdbe PS2, Line 155: /* > Wrong format Done https://review.coreboot.org/c/coreboot/+/51966/comment/944e4e0f_05484b60 PS2, Line 156: it's must otherwise sdio cmd5 failed > Otherwise, sdio cmd5 will fail. Done https://review.coreboot.org/c/coreboot/+/51966/comment/f42931d9_37e74368 PS2, Line 183: > Indent Ack https://review.coreboot.org/c/coreboot/+/51966/comment/57366807_043fdf02 PS2, Line 211: 0x%x > %#x Done https://review.coreboot.org/c/coreboot/+/51966/comment/3fd3e164_b091d527 PS2, Line 219: 0x%x > %#x Done https://review.coreboot.org/c/coreboot/+/51966/comment/a28c7f2a_75d34171 PS2, Line 234: unsigned int > uint32_t Done https://review.coreboot.org/c/coreboot/+/51966/comment/5d307118_96fc95fe PS2, Line 318: (read32(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || : read32(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT > Just […] Done https://review.coreboot.org/c/coreboot/+/51966/comment/b180f9a9_5b90cbd8 PS2, Line 359: div_width > Add 'const', and no need to assert(div_width > 0) Done https://review.coreboot.org/c/coreboot/+/51966/comment/e5e9412b_4ced392f PS2, Line 454: 0x%08x > %#010x Done https://review.coreboot.org/c/coreboot/+/51966/comment/b7b032d8_fca95986 PS2, Line 461: 0x%08x > %#010x Done File src/soc/mediatek/common/msdc.c: https://review.coreboot.org/c/coreboot/+/51966/comment/d388e635_9935aa38 PS3, Line 465: printk(BIOS_INFO, "status = %d\n", status); > Info level messages should be understandable for users. Please rephrase or make it a debug message. Done File src/soc/mediatek/common/msdc.c: https://review.coreboot.org/c/coreboot/+/51966/comment/6a86bf7f_3895b2eb PS4, Line 61: space https://review.coreboot.org/c/coreboot/+/51966/comment/68ff974c_c4056e4e PS4, Line 133: MSDC_PAD_TUNE_CMD_SEL Move to the previous line https://review.coreboot.org/c/coreboot/+/51966/comment/a72e5166_fee21d5b PS4, Line 459: "%s Align with BIOS_ERR File src/soc/mediatek/mt8192/Makefile.inc: https://review.coreboot.org/c/coreboot/+/51966/comment/8b6206ea_a8e51daf PS2, Line 65: ramstage-y += ../common/msdc.c > Sort Done -- To view, visit https://review.coreboot.org/c/coreboot/+/51966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54a7749ed167c00cd631a76af7c67c654c7bc725 Gerrit-Change-Number: 51966 Gerrit-PatchSet: 4 Gerrit-Owner: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Thu, 01 Apr 2021 10:09:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/asurada: early-init eMMC
by Yu-Ping Wu (Code Review) 01 Apr '21

01 Apr '21

Attention is currently required from: Paul Menzel, Wenbin Mei. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51973 ) Change subject: mb/google/asurada: early-init eMMC ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/asurada/mainboard.c: https://review.coreboot.org/c/coreboot/+/51973/comment/cb6ff41a_260d06ca PS2, Line 29: Use tabs for alignment -- To view, visit https://review.coreboot.org/c/coreboot/+/51973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f58d203e969dc1a13a479d7dc63b1b162a9ae3f Gerrit-Change-Number: 51973 Gerrit-PatchSet: 2 Gerrit-Owner: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Thu, 01 Apr 2021 10:01:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: include/cbfsglue.h: Use BIOS_INFO for LOG macro
by Wim Vervoorn (Code Review) 01 Apr '21

01 Apr '21

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52019 ) Change subject: include/cbfsglue.h: Use BIOS_INFO for LOG macro ...................................................................... include/cbfsglue.h: Use BIOS_INFO for LOG macro The ERROR() and LOG() macros both used BIOS_ERR as the error level. The messages generated by the LOG() macro are informational items. Change to BIOS_INFO to reflect that. BUG=N/A TEST=tested on facebook monolith Change-Id: I3827a7d65a9d70045a36fb8db4b2c129e1045122 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/include/cbfs_glue.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/52019/1 diff --git a/src/include/cbfs_glue.h b/src/include/cbfs_glue.h index ffca83e..3170c37 100644 --- a/src/include/cbfs_glue.h +++ b/src/include/cbfs_glue.h @@ -20,7 +20,7 @@ (CONFIG(TOCTOU_SAFETY) || ENV_INITIAL_STAGE)) #define ERROR(...) printk(BIOS_ERR, "CBFS ERROR: " __VA_ARGS__) -#define LOG(...) printk(BIOS_ERR, "CBFS: " __VA_ARGS__) +#define LOG(...) printk(BIOS_INFO, "CBFS: " __VA_ARGS__) #define DEBUG(...) do { \ if (CONFIG(DEBUG_CBFS)) \ printk(BIOS_SPEW, "CBFS DEBUG: " __VA_ARGS__); \ -- To view, visit https://review.coreboot.org/c/coreboot/+/52019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3827a7d65a9d70045a36fb8db4b2c129e1045122 Gerrit-Change-Number: 52019 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/facebook/monolith: Remove disabled devices from devicetree
by Wim Vervoorn (Code Review) 01 Apr '21

01 Apr '21

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52018 ) Change subject: mb/facebook/monolith: Remove disabled devices from devicetree ...................................................................... mb/facebook/monolith: Remove disabled devices from devicetree All known on-chip PCI devices are disabled in the chipset devicetree. So they are removed from the mainboard devicetree. BUG=N/A TEST=tested on facebook monolith Change-Id: Ie67cd8afc9ea92e9fd7caed4338cb25a68d94cb1 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/facebook/monolith/devicetree.cb 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/52018/1 diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 974d00e..13b3abc 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -225,12 +225,10 @@ device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 04.0 on end # Thermal Subsystem - device pci 05.0 off end # SA IMGU device pci 08.0 on end # Gaussian Mixture Model device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem - device pci 14.3 off end # Camera device pci 17.0 on end # SATA device pci 1c.2 on end # PCI Express Port 3 x1 baseboard WWAN device pci 1c.5 on end # PCI Express Port 6 x1 baseboard i210 -- To view, visit https://review.coreboot.org/c/coreboot/+/52018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie67cd8afc9ea92e9fd7caed4338cb25a68d94cb1 Gerrit-Change-Number: 52018 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/guybrush: Enable camera power GPIO
by Ivy Jian (Code Review) 01 Apr '21

01 Apr '21

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52017 ) Change subject: mb/google/guybrush: Enable camera power GPIO ...................................................................... mb/google/guybrush: Enable camera power GPIO Configure camera power GPIO to high BUG=b:182207799 TEST=Build and boot to OS then checked camera device existence with lsusb Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Change-Id: Ie894167e3c4f8efdb3710599c6ff3a9fc975adb6 --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/52017/1 diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index e386658..1921411 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -87,7 +87,7 @@ /* RAM_ID_2 / DEV_BEEP_LRCLK */ PAD_GPI(GPIO_75, PULL_NONE), /* EN_PP3300_CAM */ - PAD_GPO(GPIO_76, LOW), + PAD_GPO(GPIO_76, HIGH), /* GPIO_77 - GPIO_83: Not available */ /* EC_SOC_INT_ODL */ PAD_GPI(GPIO_84, PULL_NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/52017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie894167e3c4f8efdb3710599c6ff3a9fc975adb6 Gerrit-Change-Number: 52017 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/kukui: katsu: update the EDID and initial code
by Yu-Ping Wu (Code Review) 01 Apr '21

01 Apr '21

Attention is currently required from: Hung-Te Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51918 ) Change subject: mb/google/kukui: katsu: update the EDID and initial code ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/51918/comment/73941346_8cc1da0d PS1, Line 7: intial > Yes!it is~ Ack https://review.coreboot.org/c/coreboot/+/51918/comment/b6f9bf4c_40a110d0 PS1, Line 11: None > ok, i will create an issue tracker and add vendor in it. Done https://review.coreboot.org/c/coreboot/+/51918/comment/03e25936_98cd0746 PS1, Line 12: TEST=Boots on Chromebook Katsu and displayed developer firmware screen successfully. > YES,but the vendor update the EDID information and initial code to fix the mipi test fail issue. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/51918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e72c072b47d2be264ed7f0700812a6c704a104 Gerrit-Change-Number: 51918 Gerrit-PatchSet: 4 Gerrit-Owner: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Thu, 01 Apr 2021 09:08:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/kukui: katsu: update the EDID and initial code
by Sunwei Li (Code Review) 01 Apr '21

01 Apr '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu. Sunwei Li has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51918 ) Change subject: mb/google/kukui: katsu: update the EDID and initial code ...................................................................... Patch Set 4: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/51918/comment/0dcbe57a_0a22219c PS1, Line 7: intial > initial, but maybe you mean *panel init*? Yes!it is~ https://review.coreboot.org/c/coreboot/+/51918/comment/a71f3c0b_03bb1106 PS1, Line 11: None > Do you have an issue created there? it's probably to have an issue created, even better if the vendo […] ok, i will create an issue tracker and add vendor in it. https://review.coreboot.org/c/coreboot/+/51918/comment/f03f2e87_353dce95 PS1, Line 12: TEST=Boots on Chromebook Katsu and displayed developer firmware screen successfully. > Did it work before? YES,but the vendor update the EDID information and initial code to fix the mipi test fail issue. Commit Message: https://review.coreboot.org/c/coreboot/+/51918/comment/18a0e590_55c0051b PS2, Line 9: from STA, the vendor. > provided by STA (the vendor). Done https://review.coreboot.org/c/coreboot/+/51918/comment/c4b818dc_95c88afd PS2, Line 11: None > b:183969078 Done https://review.coreboot.org/c/coreboot/+/51918/comment/536e6e5d_f704488d PS2, Line 12: successfully. > move to next line Done Commit Message: https://review.coreboot.org/c/coreboot/+/51918/comment/6a112a07_2f5a88e5 PS3, Line 9: ( > nit: One space before "(" Done -- To view, visit https://review.coreboot.org/c/coreboot/+/51918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e72c072b47d2be264ed7f0700812a6c704a104 Gerrit-Change-Number: 51918 Gerrit-PatchSet: 4 Gerrit-Owner: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 01 Apr 2021 08:43:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/asurada: Add Chrome OS GPIOs
by Yidi Lin (Code Review) 01 Apr '21

01 Apr '21

Hello Hung-Te Lin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46386 to review the following change. Change subject: mb/google/asurada: Add Chrome OS GPIOs ...................................................................... mb/google/asurada: Add Chrome OS GPIOs Add the Chrome OS specific GPIOs (WP, EC, H1, ...) GPIOs. BUG=None TEST=emerge-asurada coreboot; # also boots into emmc BRANCH=None Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Change-Id: Ieeeee88a09ae4c3af15e2ae93a29684d30dde493 --- M src/mainboard/google/asurada/Makefile.inc M src/mainboard/google/asurada/bootblock.c M src/mainboard/google/asurada/chromeos.c A src/mainboard/google/asurada/gpio.h 4 files changed, 48 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/46386/1 diff --git a/src/mainboard/google/asurada/Makefile.inc b/src/mainboard/google/asurada/Makefile.inc index c742539..02fb830 100644 --- a/src/mainboard/google/asurada/Makefile.inc +++ b/src/mainboard/google/asurada/Makefile.inc @@ -2,12 +2,15 @@ bootblock-y += memlayout.ld bootblock-y += bootblock.c +bootblock-y += chromeos.c verstage-y += memlayout.ld +verstage-y += chromeos.c verstage-y += reset.c romstage-y += memlayout.ld romstage-y += boardid.c +romstage-y += chromeos.c romstage-y += romstage.c romstage-y += sdram_configs.c diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c index 3eb05e1..04e8898 100644 --- a/src/mainboard/google/asurada/bootblock.c +++ b/src/mainboard/google/asurada/bootblock.c @@ -3,9 +3,12 @@ #include <bootblock_common.h> #include <soc/spi.h> +#include "gpio.h" + void bootblock_mainboard_init(void) { mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); - //gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING); + setup_chromeos_gpios(); + gpio_eint_configure(GPIO_H1_AP_INT, IRQ_TYPE_EDGE_RISING); } diff --git a/src/mainboard/google/asurada/chromeos.c b/src/mainboard/google/asurada/chromeos.c index 8f9fa53..18a350b 100644 --- a/src/mainboard/google/asurada/chromeos.c +++ b/src/mainboard/google/asurada/chromeos.c @@ -5,16 +5,35 @@ #include <gpio.h> #include <security/tpm/tis.h> +#include "gpio.h" + +void setup_chromeos_gpios(void) +{ + gpio_input(GPIO_WP); + gpio_input_pullup(GPIO_EC_AP_INT); + gpio_input_pullup(GPIO_EC_IN_RW); + gpio_input_pullup(GPIO_H1_AP_INT); + gpio_input_pullup(GPIO_SD_CD); + gpio_output(GPIO_RESET, 0); +} + void fill_lb_gpios(struct lb_gpios *gpios) { + struct lb_gpio chromeos_gpios[] = { + {GPIO_EC_IN_RW.id, ACTIVE_HIGH, -1, "EC in RW"}, + {GPIO_EC_AP_INT.id, ACTIVE_LOW, -1, "EC interrupt"}, + {GPIO_H1_AP_INT.id, ACTIVE_HIGH, -1, "TPM interrupt"}, + {GPIO_SD_CD.id, ACTIVE_HIGH, -1, "SD card detect"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_write_protect_state(void) { - return 0; + return !gpio_get(GPIO_WP); } int tis_plat_irq_status(void) { - return 0; + return gpio_eint_poll(GPIO_H1_AP_INT); } diff --git a/src/mainboard/google/asurada/gpio.h b/src/mainboard/google/asurada/gpio.h new file mode 100644 index 0000000..90de583 --- /dev/null +++ b/src/mainboard/google/asurada/gpio.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MAINBOARD_GOOGLE_ASURADA_GPIO_H__ +#define __MAINBOARD_GOOGLE_ASURADA_GPIO_H__ + +#include <soc/gpio.h> + +/* AP_FLASH_WP */ +#define GPIO_WP GPIO(EINT14) +#define GPIO_EC_AP_INT GPIO(EINT5) +#define GPIO_EC_IN_RW GPIO(ANT_SEL8) +#define GPIO_H1_AP_INT GPIO(ANT_SEL9) +/* SD Card Detection */ +#define GPIO_SD_CD GPIO(EINT17) +/* AP_EC_WARM_RST_REQ */ +#define GPIO_RESET GPIO(CAM_PDN2) + +void setup_chromeos_gpios(void); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieeeee88a09ae4c3af15e2ae93a29684d30dde493 Gerrit-Change-Number: 46386 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: mb/google/volteer/variants/copano: Modify touch controller power sequ...
by Wayne3 Wang (Code Review) 01 Apr '21

01 Apr '21

Attention is currently required from: Hao Chou, Paul2 Huang, Ken Lu. Wayne3 Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52015 ) Change subject: mb/google/volteer/variants/copano: Modify touch controller power sequence ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea84046c1b1f3fe6ab8bb89d86d00b1e89325f71 Gerrit-Change-Number: 52015 Gerrit-PatchSet: 2 Gerrit-Owner: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-CC: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-Attention: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Thu, 01 Apr 2021 08:28:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/amd/bilby: enable boot from NVMe SSD
by ritul guru (Code Review) 01 Apr '21

01 Apr '21

Attention is currently required from: Marshall Dawson, Felix Held. ritul guru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51674 ) Change subject: mb/amd/bilby: enable boot from NVMe SSD ...................................................................... Patch Set 6: Code-Review+1 (1 comment) File src/mainboard/amd/bilby/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/51674/comment/94d10bc2_f1a0c0ff PS2, Line 75: > Remove the extra tabs in the function Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/51674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4407f82122c04b13684d4176ba5cd5a9fe03f0db Gerrit-Change-Number: 51674 Gerrit-PatchSet: 6 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 01 Apr 2021 08:09:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2021