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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52026 )
Change subject: mb/facebook/fbg1701/vboot-rw.fmd: Expand RO_SECTION
......................................................................
Patch Set 1: Code-Review+2
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51958 )
Change subject: soc/amd/cezanne: Add device tree support for I2C
......................................................................
soc/amd/cezanne: Add device tree support for I2C
This allows the cr50 on guybrush to show up in ACPI.
BUG=b:183737011
TEST=Boot OS and see I2C devices initialized
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Ifb5679b7bbefbf753217981874bb1bdaef35f6db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51958
Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com>
Reviewed-by: Mathew King <mathewk(a)chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/amd/cezanne/chip.c
1 file changed, 8 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Felix Held: Looks good to me, approved
Marshall Dawson: Looks good to me, approved
Karthik Ramasubramanian: Looks good to me, approved
Mathew King: Looks good to me, approved
diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c
index 2612243..c2d7af7 100644
--- a/src/soc/amd/cezanne/chip.c
+++ b/src/soc/amd/cezanne/chip.c
@@ -10,6 +10,8 @@
#include <types.h>
#include "chip.h"
+/* Supplied by i2c.c */
+extern struct device_operations soc_amd_i2c_mmio_ops;
/* Supplied by uart.c */
extern struct device_operations cezanne_uart_mmio_ops;
@@ -42,6 +44,12 @@
static void set_mmio_dev_ops(struct device *dev)
{
switch (dev->path.mmio.addr) {
+ case APU_I2C0_BASE:
+ case APU_I2C1_BASE:
+ case APU_I2C2_BASE:
+ case APU_I2C3_BASE:
+ dev->ops = &soc_amd_i2c_mmio_ops;
+ break;
case APU_UART0_BASE:
case APU_UART1_BASE:
dev->ops = &cezanne_uart_mmio_ops;
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ritul guru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51836 )
Change subject: soc/amd/picasso: Add entry for PSP NVRAM data & RPMC data
......................................................................
Patch Set 8:
(1 comment)
File src/soc/amd/picasso/fw.cfg:
https://review.coreboot.org/c/coreboot/+/51836/comment/894be076_f32ad972
PS8, Line 9: PSPNVRAM_FILE
> We can access by Firmware type ID. RPMC is 0x54. PSP_NVRAM is 4. […]
i mean, will it be still part of cbfs? how it can be located in fmap.c?
,
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Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51836 )
Change subject: soc/amd/picasso: Add entry for PSP NVRAM data & RPMC data
......................................................................
Patch Set 8:
(1 comment)
File src/soc/amd/picasso/fw.cfg:
https://review.coreboot.org/c/coreboot/+/51836/comment/5c67fe7e_42285acd
PS8, Line 9: PSPNVRAM_FILE
> How will we access these regions without names? like RPMC/PSP_NVRAM region is read/write, when acces […]
We can access by Firmware type ID. RPMC is 0x54. PSP_NVRAM is 4.
(I dont quite understand the question and not sure if I answer the question).
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Attention is currently required from: Wim Vervoorn.
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52025 )
Change subject: vc/eltan/security/verified_boot/vboot_check.c: Add cbfs_map_compressed()
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52025/comment/54ddc2e8_053d28e4
PS1, Line 16: of compressed files. For non-compressed items the
> This sentence is not complete
Done.
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Hello Wim Vervoorn,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52025
to look at the new patch set (#2).
Change subject: vc/eltan/security/verified_boot/vboot_check.c: Add cbfs_map_compressed()
......................................................................
vc/eltan/security/verified_boot/vboot_check.c: Add cbfs_map_compressed()
CB:49334 removes possibility to use cbfs_map() for retrieving CBFS map
info of compressed files. cbfs_map() will return a NULL pointer for
compressed files.
The mapping and size of compressed items are used for verification and
measuring.
Add cbfs_map_compressed() to return mapping and compressed size
of files.
BUG = N/A
TEST = Boot Facebook FBG7101
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
Change-Id: Idc799f49ee198100deab1ecf66336831d9aed415
---
M src/vendorcode/eltan/security/verified_boot/vboot_check.c
1 file changed, 16 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/52025/2
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