Attention is currently required from: Kaiyen Chang, Patrick Rudolph.
Hello Kaiyen Chang, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52029
to look at the new patch set (#2).
Change subject: soc/intel/jasperlake: Update CpuRatio settings
......................................................................
soc/intel/jasperlake: Update CpuRatio settings
An extra reset is observed on JSL platform while the flex ratio in CPU
Straps is set to a non-zero value. The root cause is that the config of
CpuRatio on JSL is fixed to zero in fsp_param.c. While FSP finds the
value of CpuRatio from m_cfg is inconsistent with the value from CPU
straps, it will invoke a system reset to apply the value from m_cfg.
This change adds a mechanism to set CpuRatio to allowed maximum
processor non-turbo ratio (from CPU straps) when cpu_ratio_override is
not set, or overriding CpuRatio with the value of cpu_ratio_override
when cpu_ratio_override is set to a non-zero value instead of just
fixing CpuRatio to zero.
BUG=b:181588337
BRANCH=None
TEST=Boot JSL platform with a non-zero flex ratio set in CPU Straps and
observe there is no extra reset in meminit while cpu_ratio_override
is not set.
Change-Id: I20b9d5620b8e394201e82185eb28b67d6702b2d5
---
M src/soc/intel/jasperlake/romstage/fsp_params.c
1 file changed, 12 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/52029/2
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Attention is currently required from: Kaiyen Chang.
Hello Kaiyen Chang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/52029
to review the following change.
Change subject: soc/intel/jasperlake: Update CpuRatio settings
......................................................................
soc/intel/jasperlake: Update CpuRatio settings
An extra reset is observed on JSL platform while the flex ratio in CPU
Straps is set to a non-zero value. The root cause is that the config of
CpuRatio on JSL is fixed to zero in fsp_param.c. While FSP finds the
value of CpuRatio from m_cfg is inconsistent with the value from CPU
straps, it will invoke a system reset to apply the value from m_cfg.
This change adds a mechanism to set CpuRatio to allowed maximum
processor non-turbo ratio (from CPU straps) when cpu_ratio_override is
not set, or overriding CpuRatio with the value of cpu_ratio_override
when cpu_ratio_override is set to a non-zero value instead of just
fixing CpuRatio to zero.
BUG=b:181588337
BRANCH=None
TEST=Boot JSL platform and observe there is no extra reset in meminit.
Change-Id: I20b9d5620b8e394201e82185eb28b67d6702b2d5
---
M src/soc/intel/jasperlake/romstage/fsp_params.c
1 file changed, 12 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/52029/1
diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c
index cd70807..31c9f6f 100644
--- a/src/soc/intel/jasperlake/romstage/fsp_params.c
+++ b/src/soc/intel/jasperlake/romstage/fsp_params.c
@@ -2,9 +2,11 @@
#include <assert.h>
#include <console/console.h>
+#include <cpu/x86/msr.h>
#include <device/device.h>
#include <fsp/util.h>
#include <soc/iomap.h>
+#include <soc/msr.h>
#include <soc/pci_devs.h>
#include <soc/romstage.h>
#include <soc/soc_chip.h>
@@ -29,6 +31,16 @@
m_cfg->SaGv = config->SaGv;
m_cfg->RMT = config->RMT;
+ /* CpuRatio Settings */
+ if (config->cpu_ratio_override) {
+ m_cfg->CpuRatio = config->cpu_ratio_override;
+ } else {
+ /* Set CpuRatio to match existing MSR value */
+ msr_t flex_ratio;
+ flex_ratio = rdmsr(MSR_FLEX_RATIO);
+ m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
+ }
+
/* PCIe root port configuration */
for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
if (config->PcieRpEnable[i])
@@ -52,9 +64,6 @@
/* Disable BIOS Guard */
m_cfg->BiosGuard = 0;
- /* Set CPU Ratio */
- m_cfg->CpuRatio = 0;
-
/* Set debug interface flags */
m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ?
DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO;
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Attention is currently required from: Martin Roth, Arthur Heymans.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/51982
to look at the new patch set (#4).
Change subject: security/intel/cbnt: Allow for an externally provided bg-prov bin
......................................................................
security/intel/cbnt: Allow for an externally provided bg-prov bin
Building the bg-prov tool requires godeps which does not work if
offline. Therefor add an option to provide this binary via Kconfig.
It's the responsibility of the user to use a compatible binary then.
Change-Id: I06ff4ee01bf58cae45648ddb8a30a30b9a7e027a
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/security/intel/cbnt/Kconfig
M src/security/intel/cbnt/Makefile.inc
2 files changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/51982/4
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Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51197 )
Change subject: vc/amd/fsp/cezanne: add platform_descriptors.h
......................................................................
Patch Set 10:
(1 comment)
File src/vendorcode/amd/fsp/cezanne/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/51197/comment/1e4d7e0a_79a51db5
PS10, Line 196: Currently unused by FSP
Based on Matt's comment, I infer this should change too.
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52028 )
Change subject: vc/amd/fsp/picasso/platform_descriptors: fix typos in enum element names
......................................................................
Patch Set 1: Code-Review+2
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