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Change subject: [WIP] mb/google/guybrush: add DXIO and DDI descriptors
......................................................................
[WIP] mb/google/guybrush: add DXIO and DDI descriptors
TODO: The devices and function numbers of the PCIe bridges still need to
be verified to work.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Signed-off-by: Matt Papageorge <matthewpapa07(a)gmail.com>
Change-Id: Ic8a4349315f8759c79dc6b087b2a933c307cd573
---
M src/mainboard/google/guybrush/port_descriptors.c
1 file changed, 71 insertions(+), 0 deletions(-)
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Change subject: [WIP] mb/amd/majolica: add DXIO and DDI descriptors
......................................................................
[WIP] mb/amd/majolica: add DXIO and DDI descriptors
TODO: The devices and function numbers of the PCIe bridges still need to
be tested. The values used in the Majolica UEFI reference implementation
weren't consistent with the PPR.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
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Change-Id: I65c7e0ebf1e43fd4608d46bae8a176cfc3d0236b
---
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Change subject: vc/amd/fsp/cezanne: add platform_descriptors.h
......................................................................
vc/amd/fsp/cezanne: add platform_descriptors.h
Not sure if CLK_GPP_REQx in cpm_clk_req are valid options; left a TODO
in the code for that.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ib16f133b270c99c6e060e5bd0c156cbb03293474
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51949 )
Change subject: lib: Add obvious definition for `calloc`
......................................................................
Patch Set 8: Code-Review+2
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Change subject: mb/intel/adlrvp: Update VBT filenames
......................................................................
Patch Set 1: Code-Review+2
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Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52032 )
Change subject: mb/intel/adlrvp: Update VBT filenames
......................................................................
mb/intel/adlrvp: Update VBT filenames
These files were just renamed to put `adlrvp` in between `vbt`
and the memory technology type.
Change-Id: Icefbac462d0ec9c660541e9cf44686d6dcf82dfd
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/mainboard/intel/adlrvp/mainboard.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/52032/1
diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c
index 3946204..0ab80d2 100644
--- a/src/mainboard/intel/adlrvp/mainboard.c
+++ b/src/mainboard/intel/adlrvp/mainboard.c
@@ -46,9 +46,9 @@
switch (sku_id) {
case ADL_P_LP5_1:
case ADL_P_LP5_2:
- return "vbt_lp5.bin";
+ return "vbt_adlrvp_lp5.bin";
case ADL_P_DDR5:
- return "vbt_ddr5.bin";
+ return "vbt_adlrvp_ddr5.bin";
default:
return "vbt.bin";
}
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Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51949 )
Change subject: lib: Add obvious definition for `calloc`
......................................................................
Patch Set 8: Code-Review+1
(1 comment)
Patchset:
PS8:
All I can do now is +1, but it looks good to me :)
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Change subject: lib: Add obvious definition for `calloc`
......................................................................
Patch Set 7:
(1 comment)
File tests/lib/malloc-test.c:
https://review.coreboot.org/c/coreboot/+/51949/comment/683c9f2f_f03a2c8e
PS7, Line 150: assert_true(*p == 0);
> There is assert_int_equal(a, b) macro. Please use that instead.
Sure, I'm new to these unit tests 😉
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Hello build bot (Jenkins), Furquan Shaikh, Jakub Czapiga,
I'd like you to reexamine a change. Please visit
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Change subject: lib: Add obvious definition for `calloc`
......................................................................
lib: Add obvious definition for `calloc`
The calloc() function is useful in addition to malloc and friends, so
add the obvious definition.
Change-Id: I57a568e323344a97b35014b7b8bec16adc2fd720
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/include/stdlib.h
M src/lib/malloc.c
M tests/lib/malloc-test.c
3 files changed, 34 insertions(+), 1 deletion(-)
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Hello build bot (Jenkins), Kaiyen Chang, Patrick Rudolph,
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Change subject: soc/intel/jasperlake: Update CpuRatio settings
......................................................................
soc/intel/jasperlake: Update CpuRatio settings
An extra reset is observed on JSL platform while the flex ratio in CPU
Straps is set to a non-zero value. The root cause is that the config of
CpuRatio on JSL is fixed to zero in fsp_param.c. While FSP finds the
value of CpuRatio from m_cfg is inconsistent with the value from CPU
straps, it will invoke a system reset to apply the value from m_cfg.
This change adds a mechanism to set CpuRatio to allowed maximum
processor non-turbo ratio (from CPU straps) when cpu_ratio_override is
not set, or overriding CpuRatio with the value of cpu_ratio_override
when cpu_ratio_override is set to a non-zero value instead of just
fixing CpuRatio to zero.
BUG=b:181588337
BRANCH=None
TEST=Boot JSL platform with a non-zero flex ratio set in CPU Straps and
observe there is no extra reset in meminit while cpu_ratio_override
is not set.
Change-Id: I20b9d5620b8e394201e82185eb28b67d6702b2d5
Signed-off-by: Kaiyen Chang <kaiyen.chang(a)intel.corp-partner.google.com>
---
M src/soc/intel/jasperlake/romstage/fsp_params.c
1 file changed, 12 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/52029/3
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