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Change subject: mb/intel/adlrvp: Update VBT filenames
......................................................................
Patch Set 1: Code-Review+1
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Change subject: adlrvp: fix the names of vbt files
......................................................................
Abandoned
https://review.coreboot.org/c/coreboot/+/52032 is already in place.
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Hello YH Lin,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/52033
to review the following change.
Change subject: adlrvp: fix the names of vbt files
......................................................................
adlrvp: fix the names of vbt files
Cope with change of file names.
BUG=None
BRANCH=master
TEST=build with adlrvp
Signed-off-by: YH Lin <yueherngl(a)chromium.org>
Change-Id: I94f60d5a5ba718d83046d08e9e1dc9163bb6411d
---
M src/mainboard/intel/adlrvp/mainboard.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/52033/1
diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c
index 3946204..0ab80d2 100644
--- a/src/mainboard/intel/adlrvp/mainboard.c
+++ b/src/mainboard/intel/adlrvp/mainboard.c
@@ -46,9 +46,9 @@
switch (sku_id) {
case ADL_P_LP5_1:
case ADL_P_LP5_2:
- return "vbt_lp5.bin";
+ return "vbt_adlrvp_lp5.bin";
case ADL_P_DDR5:
- return "vbt_ddr5.bin";
+ return "vbt_adlrvp_ddr5.bin";
default:
return "vbt.bin";
}
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Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52031 )
Change subject: mb/google/dedede: add lalala variant
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/dedede/variants/lalala/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/52031/comment/c5d9e856_acd50305
PS2, Line 301: chip drivers/wifi/generic
: register "wake" = "GPE0_DW2_03"
: device pci 00.0 on end
: end
> Is it using Discrete WiFi? If not, this can be removed.
I was following magolor.
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Change subject: include/assert.h: Use mock_assert() for ENV_TEST targets
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Patch Set 1: Code-Review+2
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Change subject: include/rules.h: Add ENV_TEST definition
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Change subject: [WIP] mb/amd/majolica: add DXIO and DDI descriptors
......................................................................
Patch Set 5:
(2 comments)
File src/mainboard/amd/majolica/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/51956/comment/cca11185_77200cf8
PS3, Line 12: device_number = 2
> haven't checked if that's correct for the mainboard, but this should indeed be on device 1, since it […]
Done
https://review.coreboot.org/c/coreboot/+/51956/comment/cc7e276d_0beee835
PS3, Line 23: device_number = 1,
> yes, this should be behind some function of device 2 on bus 0. […]
done, but untested
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Change subject: soc/amd/cezanne: Pass DXIO and DDI Descriptors to FSP
......................................................................
Patch Set 6:
(2 comments)
File src/soc/amd/cezanne/fsp_m_params.c:
https://review.coreboot.org/c/coreboot/+/51948/comment/04210bed_4f1148c7
PS6, Line 20: for (i = 0; i < num; i++) {
braces {} are not necessary for single statement blocks
https://review.coreboot.org/c/coreboot/+/51948/comment/a21f7104_e885a3e4
PS6, Line 33: for (i = 0; i < num; i++) {
braces {} are not necessary for single statement blocks
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Change subject: vc/amd/fsp/cezanne: update UPD headers
......................................................................
Patch Set 8:
(1 comment)
File src/vendorcode/amd/fsp/cezanne/FspmUpd.h:
https://review.coreboot.org/c/coreboot/+/51806/comment/ee115ed5_bdaa88c4
PS7, Line 15: /** Offset 0x0040**/ uint32_t bert_size;
> We could take over 0x40 for version. […]
yeah, that would be a good idea to check if the upd is still compatible. iirc i opened a bug on that when working on zork
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Change subject: vc/amd/fsp/cezanne: add platform_descriptors.h
......................................................................
Patch Set 11:
(3 comments)
File src/vendorcode/amd/fsp/cezanne/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/51197/comment/254d6f6b_ee77cab5
PS10, Line 196: Currently unused by FSP
> Based on Matt's comment, I infer this should change too.
this is mostly a copy of PlatformHooksPeim.h. that struct field gets copied into some other data structure, but haven't further traced that data flow
File src/vendorcode/amd/fsp/cezanne/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/51197/comment/aa808259_456f3019
PS7, Line 179: port_params
> in short token and value pairs. […]
added a comment
File src/vendorcode/amd/fsp/cezanne/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/51197/comment/5770845d_ed6f70c0
PS4, Line 57: CLK_GPP_REQ0 = 0x09,
> added a TODO
the uefi reference implementation doesn't have those, so i remove them
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