coreboot-gerrit April 2021

coreboot-gerrit@coreboot.org

1 participants
6269 discussions

Change in coreboot[master]: drivers/intel/usb4: Dummy
by John Zhao (Code Review) 28 Apr '21

28 Apr '21

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52712 ) Change subject: drivers/intel/usb4: Dummy ...................................................................... drivers/intel/usb4: Dummy Along with upstream kernel for Retimer firmware update, coreboot provides DFPx under host router where each DFP has its PLD and DSM. The DFPx's functions encapsulates power control through GPIO, PD suspend/resume and modes setting for Retimer firmware update under NDA scenario. BUG=b:186521258 TEST=Booted to kernel and validated host router's DFPx properties after decomposing SSDT table. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I81bef80729f6df57119f5523358620cb015e5406 --- M src/drivers/intel/usb4/retimer/chip.h M src/drivers/intel/usb4/retimer/retimer.c M src/drivers/intel/usb4/retimer/retimer.h 3 files changed, 371 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/52712/1 diff --git a/src/drivers/intel/usb4/retimer/chip.h b/src/drivers/intel/usb4/retimer/chip.h index 789d824..15477ee 100644 --- a/src/drivers/intel/usb4/retimer/chip.h +++ b/src/drivers/intel/usb4/retimer/chip.h @@ -4,10 +4,20 @@ #define __DRIVERS_INTEL_USB4_RETIMER_H__ #include <acpi/acpi_device.h> +#include <acpi/acpi.h> +#include <acpi/acpi_pld.h> + +#define DFP_NUM_MAX 2 struct drivers_intel_usb4_retimer_config { - /* GPIO used to control power of retimer device. */ - struct acpi_gpio power_gpio; + /* Downstream facing port(DFP) */ + uint8_t dfp_num; + struct { + /* GPIO used to control power of retimer device */ + struct acpi_gpio power_gpio; + /* _PLD setting */ + struct acpi_pld_group group; + } dfp[DFP_NUM_MAX]; }; #endif /* __DRIVERS_INTEL_USB4_RETIMER_H__ */ diff --git a/src/drivers/intel/usb4/retimer/retimer.c b/src/drivers/intel/usb4/retimer/retimer.c index fad353b..e84df36 100644 --- a/src/drivers/intel/usb4/retimer/retimer.c +++ b/src/drivers/intel/usb4/retimer/retimer.c @@ -2,141 +2,400 @@ #include <acpi/acpigen.h> #include <acpi/acpi_device.h> +#include <acpi/acpi_pld.h> #include <console/console.h> #include <device/device.h> #include <device/path.h> #include <gpio.h> - +#include <string.h> #include "chip.h" #include "retimer.h" /* Unique ID for the retimer _DSM. */ -#define INTEL_USB4_RETIMER_DSM_UUID "61788900-C470-42BB-80F0-23A313864593" +#define INTEL_USB4_RETIMER_DSM_UUID "E0053122-795B-4122-8A5E-57BE1D26ACB3" + +static const char *usb4_retimer_scope; +static const char *usb4_retimer_path_arg(const char *arg) +{ + /* \\_SB.PCI0.TDMx.ARG */ + static char name[DEVICE_PATH_MAX]; + snprintf(name, sizeof(name), "%s%c%s", usb4_retimer_scope, '.', arg); + return name; +} + +/* Each polling cycle takes up to 25 ms with a total of 12 of these iterations */ +#define usb4_retimer_iteration_num 12 +#define usb4_retimer_poll_cycle 25 +static void usb4_retimer_execute_ec_cmd(uint8_t port, uint8_t cmd, uint8_t match) +{ + const char *RFWU = ec_retimer_fw_update_path(); + uint8_t data = cmd << USB_RETIMER_FW_UPDATE_OP_SHIFT | port; + + /* Invoke EC Retimer firmware update command execution */ + ec_retimer_fw_update(data); + /* If RFWU has return value 0xfe, return error -1 */ + acpigen_write_if_lequal_namestr_int(RFWU, USB_RETIMER_FW_UPDATE_ERROR); + acpigen_write_return_integer(-1); + acpigen_pop_len(); /* If */ + + acpigen_write_store_int_to_op(usb4_retimer_iteration_num, LOCAL3_OP); + acpigen_emit_byte(WHILE_OP); + acpigen_write_len_f(); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_byte(LOCAL3_OP); + acpigen_emit_byte(ZERO_OP); + acpigen_write_if_lequal_namestr_int(RFWU, match); + acpigen_emit_byte(BREAK_OP); + acpigen_pop_len(); /* If */ + + if (cmd == USB_RETIMER_FW_UPDATE_SET_TBT) { + /* + * EC return either USB_PD_MUX_USB4_ENABLED or USB_PD_MUX_TBT_COMPAT_ENABLED + * to RFWU after the USB_RETIMER_FW_UPDATE_SET_TBT command execution. It is + * needed to add additional check for USB_PD_MUX_TBT_COMPAT_ENABLED. + */ + acpigen_write_if_lequal_namestr_int(RFWU, USB_PD_MUX_TBT_COMPAT_ENABLED); + acpigen_emit_byte(BREAK_OP); + acpigen_pop_len(); /* If */ + } + + acpigen_write_sleep(usb4_retimer_poll_cycle); + acpigen_emit_byte(DECREMENT_OP); + acpigen_emit_byte(LOCAL3_OP); + acpigen_pop_len(); /* While */ + + /* + * Check whether there is timeout error + * Return: -1 if timeout error occuring + */ + acpigen_write_if_lequal_op_int(LOCAL3_OP, 0); + acpigen_write_return_integer(-1); + acpigen_pop_len(); /* If */ +} + +static void enable_retimer_online_state(uint8_t port, struct acpi_gpio *power_gpio) +{ + uint8_t match; + + /* + * Enable_retimer_online_state under NDA + * 1. Force power on + * 2. Check if there is a device connected + * 3. Suspend PD + * 4. Set Mux to USB mode + * 5. Set Mux to Safe mode + * 6. Set Mux to TBT mode + */ + + /* Force power on for the retimer on the port */ + acpigen_enable_tx_gpio(power_gpio); + + /* + * Get MUX mode state + * Return -1 if there is a device connected on the port. + * Otherwise proceed Retimer firmware upgrade operation. + */ + match = USB_PD_MUX_NONE; + usb4_retimer_execute_ec_cmd(port, USB_RETIMER_FW_UPDATE_GET_MUX, match); + + /* + * Suspend PD + * Command: USB_RETIMER_FW_UPDATE_SUSPEND_PD + * Expect return value: 0 + */ + match = 0; + usb4_retimer_execute_ec_cmd(port, USB_RETIMER_FW_UPDATE_SUSPEND_PD, match); + + /* + * Set MUX USB Mode + * Command: USB_RETIMER_FW_UPDATE_SUSPEND_PD + * Expect return value: USB_PD_MUX_USB_ENABLED + */ + match = USB_PD_MUX_USB_ENABLED; + usb4_retimer_execute_ec_cmd(port, USB_RETIMER_FW_UPDATE_SET_USB, match); + + /* + * Set MUX Safe Mode + * Command: USB_RETIMER_FW_UPDATE_SET_SAFE + * Expect return value: USB_PD_MUX_SAFE_MODE + */ + match = USB_PD_MUX_SAFE_MODE; + usb4_retimer_execute_ec_cmd(port, USB_RETIMER_FW_UPDATE_SET_SAFE, match); + + /* + * Set MUX TBT Mode + * Command: USB_RETIMER_FW_UPDATE_SET_TBT + * Expect return value: USB_PD_MUX_USB4_ENABLED or USB_PD_MUX_TBT_COMPAT_ENABLED + */ + match = USB_PD_MUX_USB4_ENABLED; + usb4_retimer_execute_ec_cmd(port, USB_RETIMER_FW_UPDATE_SET_TBT, match); +} + +static void disable_retimer_online_state(uint8_t port, struct acpi_gpio *power_gpio) +{ + uint8_t match; + + /* + * Disable_retimer_online_state + * 1. Set Mux to disconnect mode + * 2. Resuem PD + * 3. Force power off + */ + + /* + * Set MUX Disconnect Mode + * Command: USB_RETIMER_FW_UPDATE_DISCONNECT + * Expect return value: 0 + */ + match = 0; + usb4_retimer_execute_ec_cmd(port, USB_RETIMER_FW_UPDATE_DISCONNECT, match); + + /* + * Resume PD + * Command: USB_RETIMER_FW_UPDATE_RESUME_PD + * Expect return value: 1 + */ + match = 1; + usb4_retimer_execute_ec_cmd(port, USB_RETIMER_FW_UPDATE_RESUME_PD, match); + + /* Force power off */ + acpigen_disable_tx_gpio(power_gpio); +} /* - * Arg0: UUID + * Arg0: UUID e0053122-795b-4122-8a5e-57be1d26acb3 * Arg1: Revision ID (set to 1) * Arg2: Function Index * 0: Query command implemented - * 1: Query force power enable state - * 2: Set force power state - * 3: Get Retimer FW Update EC Ram value - * 4: Set Retimer FW Update EC Ram value + * 1: Get power state + * 2: Set poewr state * Arg3: A package containing parameters for the function specified - * by the UUID, revision ID and function index. + * by the UUID, revision ID, function index and port index. */ - -static void usb4_retimer_cb_standard_query(void *arg) +static void usb4_retimer_cb_standard_query(uint8_t port, void *arg) { /* * ToInteger (Arg1, Local2) * If (Local2 == 1) { - * Return(Buffer() {0x1f}) + * Return(Buffer() {0x7}) * } * Return (Buffer() {0x01}) */ acpigen_write_to_integer(ARG1_OP, LOCAL2_OP); - /* Revision 1 supports 4 Functions beyond the standard query */ + /* Revision 1 supports 2 Functions beyond the standard query */ acpigen_write_if_lequal_op_int(LOCAL2_OP, 1); - acpigen_write_return_singleton_buffer(0x1f); + acpigen_write_return_singleton_buffer(0x7); acpigen_pop_len(); /* If */ /* Other revisions support no additional functions */ - acpigen_write_return_singleton_buffer(0); + acpigen_write_return_singleton_buffer(0x1); } -static void usb4_retimer_cb_get_power_state(void *arg) +static void usb4_retimer_cb_get_power_state(uint8_t port, void *arg) { - struct acpi_gpio *power_gpio = arg; + const char *PWR; + char pwr[DEVICE_PATH_MAX]; + + snprintf(pwr, sizeof(pwr), "HR.DFP%d%c%s", port, '.', "PWR"); + PWR = usb4_retimer_path_arg(pwr); /* - * Read power gpio into Local0 - * Store (\_SB.PCI0.GTXS (power_gpio), Local0) - * Return (Local0) + * If (PWR > 0) { + * Return (1) + * } */ - acpigen_get_tx_gpio(power_gpio); - acpigen_write_return_op(LOCAL0_OP); -} - -static void usb4_retimer_cb_set_power_state(void *arg) -{ - struct acpi_gpio *power_gpio = arg; + acpigen_write_if(); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_namestring(PWR); + acpigen_emit_byte(0); + acpigen_write_return_integer(1); /* - * Get information to set to retimer info from Arg3[0] + * Else { + * Return (0) + * } + */ + acpigen_write_else(); + acpigen_write_return_integer(0); + acpigen_pop_len(); +} + +static void usb4_retimer_cb_set_power_state(uint8_t port, void *arg) +{ + struct acpi_gpio *power_gpio = arg; + const char *PWR; + char pwr[DEVICE_PATH_MAX]; + + snprintf(pwr, sizeof(pwr), "HR.DFP%d%c%s", port, '.', "PWR"); + PWR = usb4_retimer_path_arg(pwr); + + /* + * Get information to set retimer power state from Arg3[0] * Local0 = DeRefOf (Arg3[0]) */ acpigen_get_package_op_element(ARG3_OP, 0, LOCAL0_OP); /* - * If (Local0 == 0) { - * // Turn power off - * \_SB.PCI0.CTXS (power_gpio) + * If ((Local0 == 0) && (PWR > 0)) { + * PWR-- + * If (PWR == 0) { + * // Disable retimer online state + * } * } */ - acpigen_write_if_lequal_op_int(LOCAL0_OP, 0); - acpigen_disable_tx_gpio(power_gpio); + acpigen_write_if(); + acpigen_emit_byte(LAND_OP); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_emit_byte(0); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_namestring(PWR); + acpigen_emit_byte(0); + /* PWR-- */ + acpigen_emit_byte(DECREMENT_OP); + acpigen_emit_namestring(PWR); + acpigen_write_if_lequal_namestr_int(PWR, 0); /* If (PWR == 0) */ + disable_retimer_online_state(port, power_gpio); + acpigen_pop_len(); /* If (PWR == 0) */ /* - * Else { - * // Turn power on - * \_SB.PCI0.STXS (power_gpio) + * Else If ((Local0 == 1) && (PWR == 0)) { + * // Enable retimer online state + * PWR++ * } */ acpigen_write_else(); - acpigen_enable_tx_gpio(power_gpio); - acpigen_pop_len(); - - /* Return (Zero) */ - acpigen_write_return_integer(0); -} - -static void usb4_retimer_cb_get_retimer_info(void *arg) -{ - const char *RFWU = ec_retimer_fw_update_path(); + acpigen_write_if(); + acpigen_emit_byte(LAND_OP); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_emit_byte(1); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_namestring(PWR); + acpigen_emit_byte(0); + enable_retimer_online_state(port, power_gpio); + /* PWR++ */ + acpigen_emit_byte(INCREMENT_OP); + acpigen_emit_namestring(PWR); /* - * Read Mux Retimer info from EC RAM - * Return RFWU if RFWU is not NULL. Otherwise return -1 to - * inform kernel about error. + * Else { + * Return (0) + * } */ - if (!RFWU) - acpigen_write_return_byte(-1); - else - acpigen_write_return_namestr(RFWU); + acpigen_write_else(); + acpigen_write_return_integer(0); + acpigen_pop_len(); /* Else */ + acpigen_pop_len(); /* If */ + + /* + * If (PWR == 1) { + * Return (1) + * } + */ + acpigen_write_if_lequal_namestr_int(PWR, 1); + acpigen_write_return_integer(1); + + /* + * Else { + * Return (0) + * } + */ + acpigen_write_else(); + acpigen_write_return_integer(0); + acpigen_pop_len(); } -static void usb4_retimer_cb_set_retimer_info(void *arg) -{ - ec_retimer_fw_update(arg); -} - -static void (*usb4_retimer_callbacks[5])(void *) = { +static void (*usb4_retimer_callbacks[3])(uint8_t port, void *) = { usb4_retimer_cb_standard_query, /* Function 0 */ - usb4_retimer_cb_get_power_state, /* Function 1 */ - usb4_retimer_cb_set_power_state, /* Function 2 */ - usb4_retimer_cb_get_retimer_info, /* Function 3 */ - usb4_retimer_cb_set_retimer_info, /* Function 4 */ + usb4_retimer_cb_get_power_state, /* Function 1 */ + usb4_retimer_cb_set_power_state, /* Function 2 */ }; +static void usb4_retimer_write_dsm(uint8_t port, const char *uuid, + void (**callbacks)(uint8_t port, void *), size_t count, void *arg) +{ + struct usb4_retimer_dsm_uuid id = DSM_UUID(uuid, callbacks, count, arg); + size_t i; + + acpigen_write_to_integer(ARG2_OP, LOCAL1_OP); + + for (i = 0; i < id.count; i++) { + /* If (LEqual (Local1, i)) */ + acpigen_write_if_lequal_op_int(LOCAL1_OP, i); + + /* Callback to write if handler. */ + if (id.callbacks[i]) + id.callbacks[i](port, id.arg); + + acpigen_pop_len(); /* If */ + } +} + static void usb4_retimer_fill_ssdt(const struct device *dev) { - const struct drivers_intel_usb4_retimer_config *config = dev->chip_info; - const char *scope = acpi_device_scope(dev); + struct drivers_intel_usb4_retimer_config *config = dev->chip_info; + static char dfp[DEVICE_PATH_MAX]; + struct acpi_pld pld; + uint8_t port; - if (!scope || !config) + usb4_retimer_scope = acpi_device_scope(dev); + if (!usb4_retimer_scope || !config) return; - if (!config->power_gpio.pin_count) { - printk(BIOS_ERR, "%s: Power GPIO required for %s\n", __func__, dev_path(dev)); - return; + /* Scope */ + acpigen_write_scope(usb4_retimer_scope); + + /* Host router */ + acpigen_write_device("HR"); + acpigen_write_ADR(0); + acpigen_write_STA(0xf); + + for(port = 0; port < config->dfp_num; port++) { + /* DFPx */ + snprintf(dfp, sizeof(dfp), "DFP%1x", port); + acpigen_write_device(dfp); + /* _ADR part is for the lane adapter*/ + acpigen_write_ADR(port*2 + 1); + + /* Fill _PLD with the same USB 3.x object on the Type-C connector */ + acpi_pld_fill_usb(&pld, UPC_TYPE_PROPRIETARY, &config->dfp[port].group); + pld.shape = PLD_SHAPE_OVAL; + pld.visible = 1; + acpigen_write_pld(&pld); + + /* Power online reference counter(_PWR) */ + acpigen_write_name("PWR"); + acpigen_write_zero(); + if (!config->dfp[port].power_gpio.pin_count) { + printk(BIOS_ERR, "%s: Power GPIO required for %s\n", __func__, + dev_path(dev)); + return; + } + + /* Method (_DSM, 4, Serialized) */ + acpigen_write_method_serialized("_DSM", 0x4); + /* ToBuffer (Arg0, Local0) */ + acpigen_write_to_buffer(ARG0_OP, LOCAL0_OP); + acpigen_write_if(); /* If (UUID != INTEL_USB4_RETIMER_DSM_UUID) */ + acpigen_emit_byte(LNOT_OP); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_uuid(INTEL_USB4_RETIMER_DSM_UUID); + /* Return (Buffer (One) { 0x0 }) */ + acpigen_write_return_singleton_buffer(0x0); + acpigen_pop_len(); + usb4_retimer_write_dsm(port, INTEL_USB4_RETIMER_DSM_UUID, + usb4_retimer_callbacks, ARRAY_SIZE(usb4_retimer_callbacks), + (void *)&config->dfp[port].power_gpio); + /* Default case: Return (Buffer (One) { 0x0 }) */ + acpigen_write_return_singleton_buffer(0x0); + + acpigen_pop_len(); /* Method _DSM */ + acpigen_pop_len(); /* DFP */ } - - /* Write the _DSM that toggles power with provided GPIO. */ - acpigen_write_scope(scope); - acpigen_write_dsm(INTEL_USB4_RETIMER_DSM_UUID, usb4_retimer_callbacks, - ARRAY_SIZE(usb4_retimer_callbacks), (void *)&config->power_gpio); + acpigen_pop_len(); /* Host Router */ acpigen_pop_len(); /* Scope */ printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name, @@ -164,6 +423,6 @@ return NULL; } -__weak void ec_retimer_fw_update(void *arg) +__weak void ec_retimer_fw_update(uint8_t data) { } diff --git a/src/drivers/intel/usb4/retimer/retimer.h b/src/drivers/intel/usb4/retimer/retimer.h index 4c4044a..5a040a0 100644 --- a/src/drivers/intel/usb4/retimer/retimer.h +++ b/src/drivers/intel/usb4/retimer/retimer.h @@ -3,7 +3,32 @@ #ifndef _DRIVERS_INTEL_USB4_RETIMER_H_ #define _DRIVERS_INTEL_USB4_RETIMER_H_ +/* Flags representing mux state */ +#define USB_PD_MUX_NONE 0 /* Open switch */ +#define USB_PD_MUX_USB_ENABLED BIT(0) /* USB connected */ +#define USB_PD_MUX_SAFE_MODE BIT(5) /* DP is in safe mode */ +#define USB_PD_MUX_TBT_COMPAT_ENABLED BIT(6) /* TBT compat enabled */ +#define USB_PD_MUX_USB4_ENABLED BIT(7) /* USB4 enabled */ + +#define USB_RETIMER_FW_UPDATE_OP_SHIFT 4 +#define USB_RETIMER_FW_UPDATE_ERROR 0xfe +/* Retimer firmware update operations */ +#define USB_RETIMER_FW_UPDATE_SUSPEND_PD 1 /* Suspend PD port */ +#define USB_RETIMER_FW_UPDATE_RESUME_PD 2 /* Resume PD port */ +#define USB_RETIMER_FW_UPDATE_GET_MUX 3 /* Read current USB MUX */ +#define USB_RETIMER_FW_UPDATE_SET_USB 4 /* Set MUX to USB mode */ +#define USB_RETIMER_FW_UPDATE_SET_SAFE 5 /* Set MUX to Safe mode */ +#define USB_RETIMER_FW_UPDATE_SET_TBT 6 /* Set MUX to TBT mode */ +#define USB_RETIMER_FW_UPDATE_DISCONNECT 7 /* Set MUX to disconnect */ + +struct usb4_retimer_dsm_uuid { + const char *uuid; + void (**callbacks)(uint8_t port, void *); + size_t count; + void *arg; +}; + const char *ec_retimer_fw_update_path(void); -void ec_retimer_fw_update(void *arg); +void ec_retimer_fw_update(uint8_t data); #endif /* _DRIVERS_INTEL_USB4_RETIMER_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81bef80729f6df57119f5523358620cb015e5406 Gerrit-Change-Number: 52712 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/alderlake: Add CrashLog implementation for Intel ADL
by Tim Wawrzynczak (Code Review) 28 Apr '21

28 Apr '21

Attention is currently required from: Francois Toguo Fotso, Paul Menzel, Tim Wawrzynczak. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52454 ) Change subject: soc/intel/alderlake: Add CrashLog implementation for Intel ADL ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52454/comment/c812b2b5_ef9d8a16 PS6, Line 11: 183981959 b:183981959 -- To view, visit https://review.coreboot.org/c/coreboot/+/52454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15ba0b41f73c1772f09584f13bcf5585caa90782 Gerrit-Change-Number: 52454 Gerrit-PatchSet: 6 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raj Astekar <raj.astekar(a)intel.com> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Tue, 27 Apr 2021 17:57:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: chromeec: Fix google_chromeec_status_check timeout
by Rob Barnes (Code Review) 28 Apr '21

28 Apr '21

Attention is currently required from: Furquan Shaikh, Martin Roth. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51775 ) Change subject: chromeec: Fix google_chromeec_status_check timeout ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: Ping. Any blockers on this CL? -- To view, visit https://review.coreboot.org/c/coreboot/+/51775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I363ff7453bcf81581884f92797629a6f96d42580 Gerrit-Change-Number: 51775 Gerrit-PatchSet: 6 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 27 Apr 2021 17:48:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/volteer: Remove power_gpio from baseboard
by John Zhao (Code Review) 28 Apr '21

28 Apr '21

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52711 ) Change subject: mb/google/volteer: Remove power_gpio from baseboard ...................................................................... mb/google/volteer: Remove power_gpio from baseboard Along with upstream kernel for Retimer firmware update, coreboot defines power control for each DFP respectively under host router. This change removes the power_gpio from baseboard. Individual DFPx power_gpio will be added once the dependent definition is complete. BUG=b:186521258 TEST=Build image successfully. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: Iec2437ab20d283d080752a80aa4514aa9af6897e --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/52711/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index fdac104..eddbddf 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -474,10 +474,6 @@ device ref tbt_dma0 on probe DB_USB USB4_GEN2 probe DB_USB USB4_GEN3 - chip drivers/intel/usb4/retimer - register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H10)" - device generic 0 on end - end end device ref gna on end device ref north_xhci on end -- To view, visit https://review.coreboot.org/c/coreboot/+/52711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec2437ab20d283d080752a80aa4514aa9af6897e Gerrit-Change-Number: 52711 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: ec/google/chromeec: Remove ec_retimer_fw_update
by John Zhao (Code Review) 28 Apr '21

28 Apr '21

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52710 ) Change subject: ec/google/chromeec: Remove ec_retimer_fw_update ...................................................................... ec/google/chromeec: Remove ec_retimer_fw_update Along with upstream kernel for Retimer firmware update, coreboot changes the ec_retimer_fw_update format. This change removes this API and will add implementation late once the dependent definition is complete. BUG=b:186521258 TEST=Build image successfully. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I2d074b84fb3cb87b443871104b72b6c316af5279 --- M src/ec/google/chromeec/ec_acpi.c 1 file changed, 0 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/52710/1 diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index bcecd89..8cfc7b1 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -241,25 +241,3 @@ { return "\\_SB_.PCI0.LPCB.EC0_.RFWU"; } - -void ec_retimer_fw_update(void *arg) -{ - const char *RFWU = ec_retimer_fw_update_path(); - - /* - * Get information to set retimer info from Arg3[0] - * Local0 = DeRefOf (Arg3[0]) - */ - acpigen_get_package_op_element(ARG3_OP, 0, LOCAL0_OP); - - /* - * Write the EC RAM for Retimer Upgrade - * RFWU = LOCAL0 - */ - acpigen_write_store(); - acpigen_emit_byte(LOCAL0_OP); - acpigen_emit_namestring(RFWU); - - /* Return (Zero) */ - acpigen_write_return_integer(0); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/52710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d074b84fb3cb87b443871104b72b6c316af5279 Gerrit-Change-Number: 52710 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/skylake: Add microcodes for Coffee Lake CPUs
by Timofey Komarov (Code Review) 28 Apr '21

28 Apr '21

Attention is currently required from: Timofey Komarov, Angel Pons, Patrick Rudolph. Hello build bot (Jenkins), Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52693 to look at the new patch set (#4). Change subject: soc/intel/skylake: Add microcodes for Coffee Lake CPUs ...................................................................... soc/intel/skylake: Add microcodes for Coffee Lake CPUs Signed-off-by: Timofey Komarov <happycorsair(a)yandex.ru> Change-Id: I479c648e40c4c607d29f8cdd913fdbd6d7d7d991 --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/52693/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/52693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I479c648e40c4c607d29f8cdd913fdbd6d7d7d991 Gerrit-Change-Number: 52693 Gerrit-PatchSet: 4 Gerrit-Owner: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/skylake: Add microcodes for Coffee Lake CPUs
by Timofey Komarov (Code Review) 28 Apr '21

28 Apr '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Timofey Komarov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52693 ) Change subject: soc/intel/skylake: Add microcodes for Coffee Lake CPUs ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52693/comment/e934eece_4688c87f PS1, Line 7: Add microcodes for Coffeelake CPUs > nit: Add a prefix, and spell it as `Coffee Lake`: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I479c648e40c4c607d29f8cdd913fdbd6d7d7d991 Gerrit-Change-Number: 52693 Gerrit-PatchSet: 2 Gerrit-Owner: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 27 Apr 2021 16:30:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya: Enable ELAN9050 touchscreen
by Tim Wawrzynczak (Code Review) 28 Apr '21

28 Apr '21

Attention is currently required from: Paul Menzel, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52665 ) Change subject: mb/google/brya: Enable ELAN9050 touchscreen ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c247fae33b9178c8706552aba2f950c9a674ecc Gerrit-Change-Number: 52665 Gerrit-PatchSet: 4 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 27 Apr 2021 16:29:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/skylake: Add microcodes for Coffee Lake CPUs
by Timofey Komarov (Code Review) 28 Apr '21

28 Apr '21

Attention is currently required from: Timofey Komarov, Patrick Rudolph. Hello build bot (Jenkins), Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52693 to look at the new patch set (#2). Change subject: soc/intel/skylake: Add microcodes for Coffee Lake CPUs ...................................................................... soc/intel/skylake: Add microcodes for Coffee Lake CPUs Signed-off-by: Timofey Komarov <happycorsair(a)yandex.ru> Change-Id: I479c648e40c4c607d29f8cdd913fdbd6d7d7d991 --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/52693/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I479c648e40c4c607d29f8cdd913fdbd6d7d7d991 Gerrit-Change-Number: 52693 Gerrit-PatchSet: 2 Gerrit-Owner: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/mancomb: Add STAPM values to overridetree
by chris wang (Code Review) 28 Apr '21

28 Apr '21

Attention is currently required from: Chris Wang. Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/52709 to review the following change. Change subject: mb/google/mancomb: Add STAPM values to overridetree ...................................................................... mb/google/mancomb: Add STAPM values to overridetree follow the FP6 IRM(#56328) to set the stapm parameter. and allow other mancomb variants boards can customize those parameters. BUG=b:1181157669 TEST=build. Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Ib3ed76e5212a5a8b5fb4fcc3d6884ceff82377b7 --- M src/mainboard/google/mancomb/variants/mancomb/overridetree.cb 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/52709/1 diff --git a/src/mainboard/google/mancomb/variants/mancomb/overridetree.cb b/src/mainboard/google/mancomb/variants/mancomb/overridetree.cb index 891b4eb..0662645 100644 --- a/src/mainboard/google/mancomb/variants/mancomb/overridetree.cb +++ b/src/mainboard/google/mancomb/variants/mancomb/overridetree.cb @@ -1,4 +1,14 @@ chip soc/amd/cezanne + + register "system_configuration" = "3" + + register "slow_ppt_limit_mW" = "37500" + register "fast_ppt_limit_mW" = "48000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "275" + register "sustained_power_limit_mW" = "25000" + register "thermctl_limit_degreeC" = "100" + device domain 0 on end # domain -- To view, visit https://review.coreboot.org/c/coreboot/+/52709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3ed76e5212a5a8b5fb4fcc3d6884ceff82377b7 Gerrit-Change-Number: 52709 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2021