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Change subject: mb/google/mancomb: Enable VBOOT_LID_SWITCH
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Patch Set 1:
(1 comment)
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https://review.coreboot.org/c/coreboot/+/52602/comment/c88374c1_60983d50
PS1, Line 13: TEST=Depthcharge no longer halts complaining that coreboot didn't sample
: the pin
> I am wondering if this is required on chromeboxes without a lid switch. […]
I like that suggestion.
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Change subject: mb/google/mancomb: Enable VBOOT_LID_SWITCH
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Patch Set 1: -Code-Review
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52602/comment/5f099191_bb3701e1
PS1, Line 13: TEST=Depthcharge no longer halts complaining that coreboot didn't sample
: the pin
I am wondering if this is required on chromeboxes without a lid switch. It seems we can always replace the lid switch with a fake gpio(flag_replace(FLAG_LIDSW, new_gpio_high());) in depthcharge to fix the issue.
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Change subject: drivers/pc80/rtc/option.c: Constrain API to integer values
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Patch Set 6: Code-Review+1
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Change subject: ec/lenovo/h8/h8.c: Skip setting volume if out of range
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Patch Set 1: Code-Review+2
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Change subject: superio/nuvoton/npcd378: Fall back to non-negative value
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Patch Set 2: Code-Review+2
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Change subject: docs/mb/supermicro/x11ssm-f: rework flashing section
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Patch Set 1: Code-Review+2
(1 comment)
File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md:
https://review.coreboot.org/c/coreboot/+/52679/comment/c8814762_f04cd814
PS1, Line 12: G2
S5 is probably more common.
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Change subject: mb/google/guybrush: Fix EC SCI configuration
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Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52673/comment/b2cb1450_0910809f
PS2, Line 14: Cezanne has added a new event source that directly exposes the SCI bit.
> I wouldn't move this to chipset since it's dependent on the EC implementation. […]
ackn.
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