coreboot-gerrit March 2021

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Change in coreboot[master]: util/inteltool: Add support for GLK
by Michał Żygowski (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Igor Bagnucki, Stefan Reinauer, Name of user not set #1003165, Piotr Król. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51130 ) Change subject: util/inteltool: Add support for GLK ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I see we have a duplicate here: CB:36033 -- To view, visit https://review.coreboot.org/c/coreboot/+/51130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I017789c9e23e355214deced29efcb3532c449981 Gerrit-Change-Number: 51130 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1003165 Gerrit-Reviewer: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Name of user not set #1003165 Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Mon, 01 Mar 2021 09:27:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: vendor: mediatek: Add mediatek mt8192 dram initialization codes
by Xi Chen (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Xi Chen, Hung-Te Lin, Nico Huber, Martin Roth, Paul Menzel, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Menzel, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50294 to look at the new patch set (#11). Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization codes ...................................................................... vendor: mediatek: Add mediatek mt8192 dram initialization codes Add the DRAM initialization code based on Mediatek reference implementation. Mediatek internally maintains the DRAM initialization code, following different coding style. To prevent maintaining a different branch for coreboot (which may lead to typo or errors which switching between different coding style), we want to directly use the reference implementation as vendor code. Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 --- M src/vendorcode/Makefile.inc A src/vendorcode/mediatek/Kconfig A src/vendorcode/mediatek/Makefile.inc A src/vendorcode/mediatek/mt8192/Makefile.inc A src/vendorcode/mediatek/mt8192/dramc/ANA_init_config.c A src/vendorcode/mediatek/mt8192/dramc/DIG_NONSHUF_config.c A src/vendorcode/mediatek/mt8192/dramc/DIG_SHUF_config.c A src/vendorcode/mediatek/mt8192/dramc/DRAMC_SUBSYS_config.c A src/vendorcode/mediatek/mt8192/dramc/DRAM_config_collctioin.c A src/vendorcode/mediatek/mt8192/dramc/Hal_io.c A src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c A src/vendorcode/mediatek/mt8192/dramc/Makefile.inc A src/vendorcode/mediatek/mt8192/dramc/dramc_actiming.c A src/vendorcode/mediatek/mt8192/dramc/dramc_dv_freq_related.c A src/vendorcode/mediatek/mt8192/dramc/dramc_dvfs.c A src/vendorcode/mediatek/mt8192/dramc/dramc_lowpower.c A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_calibration_api.c A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c A src/vendorcode/mediatek/mt8192/dramc/dramc_top.c A src/vendorcode/mediatek/mt8192/dramc/dramc_tracking.c A src/vendorcode/mediatek/mt8192/dramc/dramc_utility.c A src/vendorcode/mediatek/mt8192/dramc/emi.c A src/vendorcode/mediatek/mt8192/driver/Makefile.inc A src/vendorcode/mediatek/mt8192/driver/pmic_wrap.c A src/vendorcode/mediatek/mt8192/driver/timer.c A src/vendorcode/mediatek/mt8192/driver/uart.c A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_AO.h A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_MD32.h A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_NAO.h A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_AO.h A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_NAO.h A src/vendorcode/mediatek/mt8192/include/addressmap.h A src/vendorcode/mediatek/mt8192/include/custom_emi.h A src/vendorcode/mediatek/mt8192/include/ddrphy_nao_reg.h A src/vendorcode/mediatek/mt8192/include/ddrphy_pll_reg.h A src/vendorcode/mediatek/mt8192/include/ddrphy_wo_pll_reg.h A src/vendorcode/mediatek/mt8192/include/dramc_actiming.h A src/vendorcode/mediatek/mt8192/include/dramc_ch0_nao_reg.h A src/vendorcode/mediatek/mt8192/include/dramc_ch0_reg.h A src/vendorcode/mediatek/mt8192/include/dramc_common.h A src/vendorcode/mediatek/mt8192/include/dramc_dv_init.h A src/vendorcode/mediatek/mt8192/include/dramc_int_global.h A src/vendorcode/mediatek/mt8192/include/dramc_int_slt.h A src/vendorcode/mediatek/mt8192/include/dramc_pi_api.h A src/vendorcode/mediatek/mt8192/include/dramc_reg_base_addr.h A src/vendorcode/mediatek/mt8192/include/dramc_register.h A src/vendorcode/mediatek/mt8192/include/dramc_top.h A src/vendorcode/mediatek/mt8192/include/dramc_typedefs.h A src/vendorcode/mediatek/mt8192/include/emi.h A src/vendorcode/mediatek/mt8192/include/emi_hw.h A src/vendorcode/mediatek/mt8192/include/emi_mpu_mt.h A src/vendorcode/mediatek/mt8192/include/emi_mpu_v1.h A src/vendorcode/mediatek/mt8192/include/memory.h A src/vendorcode/mediatek/mt8192/include/pmic_wrap_init.h A src/vendorcode/mediatek/mt8192/include/print.h A src/vendorcode/mediatek/mt8192/include/reg.h A src/vendorcode/mediatek/mt8192/include/soc/dpm.h A src/vendorcode/mediatek/mt8192/include/soc/dramc_common_mt8192.h A src/vendorcode/mediatek/mt8192/include/soc/dramc_param.h A src/vendorcode/mediatek/mt8192/include/soc/emi.h A src/vendorcode/mediatek/mt8192/include/stdint.h A src/vendorcode/mediatek/mt8192/include/sv_c_data_traffic.h A src/vendorcode/mediatek/mt8192/include/sys/types.h A src/vendorcode/mediatek/mt8192/include/uart.h A src/vendorcode/mediatek/mt8192/include/x_hal_io.h A src/vendorcode/mediatek/mt8192/lib/Makefile.inc A src/vendorcode/mediatek/mt8192/lib/print.c 68 files changed, 87,537 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/50294/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/50294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 Gerrit-Change-Number: 50294 Gerrit-PatchSet: 11 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Cindy Ching <cindy.ching(a)mediatek.corp-partner.google.com> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vendor: mediatek: Add mediatek mt8192 dram initialization codes
by Xi Chen (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Hung-Te Lin, Nico Huber, Martin Roth, Paul Menzel, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Menzel, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50294 to look at the new patch set (#10). Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization codes ...................................................................... vendor: mediatek: Add mediatek mt8192 dram initialization codes Add the DRAM initialization code based on Mediatek reference implementation. Mediatek internally maintains the DRAM initialization code, following different coding style. To prevent maintaining a different branch for coreboot (which may lead to typo or errors which switching between different coding style), we want to directly use the reference implementation as vendor code. Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 --- M src/vendorcode/Makefile.inc A src/vendorcode/mediatek/Kconfig A src/vendorcode/mediatek/Makefile.inc A src/vendorcode/mediatek/mt8192/Makefile.inc A src/vendorcode/mediatek/mt8192/dramc/ANA_init_config.c A src/vendorcode/mediatek/mt8192/dramc/DIG_NONSHUF_config.c A src/vendorcode/mediatek/mt8192/dramc/DIG_SHUF_config.c A src/vendorcode/mediatek/mt8192/dramc/DRAMC_SUBSYS_config.c A src/vendorcode/mediatek/mt8192/dramc/DRAM_config_collctioin.c A src/vendorcode/mediatek/mt8192/dramc/Hal_io.c A src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c A src/vendorcode/mediatek/mt8192/dramc/Makefile.inc A src/vendorcode/mediatek/mt8192/dramc/dramc_actiming.c A src/vendorcode/mediatek/mt8192/dramc/dramc_dv_freq_related.c A src/vendorcode/mediatek/mt8192/dramc/dramc_dvfs.c A src/vendorcode/mediatek/mt8192/dramc/dramc_lowpower.c A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_calibration_api.c A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c A src/vendorcode/mediatek/mt8192/dramc/dramc_top.c A src/vendorcode/mediatek/mt8192/dramc/dramc_tracking.c A src/vendorcode/mediatek/mt8192/dramc/dramc_utility.c A src/vendorcode/mediatek/mt8192/dramc/emi.c A src/vendorcode/mediatek/mt8192/driver/Makefile.inc A src/vendorcode/mediatek/mt8192/driver/pmic_wrap.c A src/vendorcode/mediatek/mt8192/driver/timer.c A src/vendorcode/mediatek/mt8192/driver/uart.c A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_AO.h A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_MD32.h A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_NAO.h A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_AO.h A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_NAO.h A src/vendorcode/mediatek/mt8192/include/addressmap.h A src/vendorcode/mediatek/mt8192/include/custom_emi.h A src/vendorcode/mediatek/mt8192/include/ddrphy_nao_reg.h A src/vendorcode/mediatek/mt8192/include/ddrphy_pll_reg.h A src/vendorcode/mediatek/mt8192/include/ddrphy_wo_pll_reg.h A src/vendorcode/mediatek/mt8192/include/dramc_actiming.h A src/vendorcode/mediatek/mt8192/include/dramc_ch0_nao_reg.h A src/vendorcode/mediatek/mt8192/include/dramc_ch0_reg.h A src/vendorcode/mediatek/mt8192/include/dramc_common.h A src/vendorcode/mediatek/mt8192/include/dramc_dv_init.h A src/vendorcode/mediatek/mt8192/include/dramc_int_global.h A src/vendorcode/mediatek/mt8192/include/dramc_int_slt.h A src/vendorcode/mediatek/mt8192/include/dramc_pi_api.h A src/vendorcode/mediatek/mt8192/include/dramc_reg_base_addr.h A src/vendorcode/mediatek/mt8192/include/dramc_register.h A src/vendorcode/mediatek/mt8192/include/dramc_top.h A src/vendorcode/mediatek/mt8192/include/dramc_typedefs.h A src/vendorcode/mediatek/mt8192/include/emi.h A src/vendorcode/mediatek/mt8192/include/emi_hw.h A src/vendorcode/mediatek/mt8192/include/emi_mpu_mt.h A src/vendorcode/mediatek/mt8192/include/emi_mpu_v1.h A src/vendorcode/mediatek/mt8192/include/memory.h A src/vendorcode/mediatek/mt8192/include/pmic_wrap_init.h A src/vendorcode/mediatek/mt8192/include/print.h A src/vendorcode/mediatek/mt8192/include/reg.h A src/vendorcode/mediatek/mt8192/include/soc/dpm.h A src/vendorcode/mediatek/mt8192/include/soc/dramc_common_mt8192.h A src/vendorcode/mediatek/mt8192/include/soc/dramc_param.h A src/vendorcode/mediatek/mt8192/include/soc/emi.h A src/vendorcode/mediatek/mt8192/include/stdint.h A src/vendorcode/mediatek/mt8192/include/sv_c_data_traffic.h A src/vendorcode/mediatek/mt8192/include/sys/types.h A src/vendorcode/mediatek/mt8192/include/uart.h A src/vendorcode/mediatek/mt8192/include/x_hal_io.h A src/vendorcode/mediatek/mt8192/lib/Makefile.inc A src/vendorcode/mediatek/mt8192/lib/print.c 68 files changed, 87,544 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/50294/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/50294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 Gerrit-Change-Number: 50294 Gerrit-PatchSet: 10 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Cindy Ching <cindy.ching(a)mediatek.corp-partner.google.com> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/amd/majolica: Add eSPI support
by Bao Zheng (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49966 ) Change subject: mb/amd/majolica: Add eSPI support ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: > Are you actively working on this patch? Otherwise I can push my local patch. My board failed to boot and I am waiting for a new board. If you need to do this quickly, you can push your change and I can mark it. -- To view, visit https://review.coreboot.org/c/coreboot/+/49966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e82a51173f561df560c36528a9b7ec26cf489b5 Gerrit-Change-Number: 49966 Gerrit-PatchSet: 8 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Mar 2021 09:05:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: Add support for GLK
by Name of user not set (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Igor Bagnucki. Hello Igor Bagnucki, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/51130 to review the following change. Change subject: util/inteltool: Add support for GLK ...................................................................... util/inteltool: Add support for GLK Signed-off-by: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Change-Id: I017789c9e23e355214deced29efcb3532c449981 --- M util/inteltool/gpio_groups.c A util/inteltool/gpio_names/geminilake.h M util/inteltool/inteltool.h 3 files changed, 318 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/51130/1 diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 0ff1c86..ec2fc6b 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -14,6 +14,7 @@ #include "gpio_names/cannonlake.h" #include "gpio_names/cannonlake_lp.h" #include "gpio_names/denverton.h" +#include "gpio_names/geminilake.h" #include "gpio_names/icelake.h" #include "gpio_names/lewisburg.h" #include "gpio_names/sunrise.h" @@ -166,6 +167,10 @@ *community_count = ARRAY_SIZE(icelake_pch_h_communities); *pad_stepping = 16; return icelake_pch_h_communities; + case PCI_DEVICE_ID_INTEL_GLK_LPC: + *community_count = ARRAY_SIZE(geminilake_communities); + *pad_stepping = 16; + return geminilake_communities; default: return NULL; } diff --git a/util/inteltool/gpio_names/geminilake.h b/util/inteltool/gpio_names/geminilake.h new file mode 100644 index 0000000..2249dc3 --- /dev/null +++ b/util/inteltool/gpio_names/geminilake.h @@ -0,0 +1,311 @@ +#ifndef GPIO_NAMES_GEMINILAKE_H +#define GPIO_NAMES_GEMINILAKE_H + +#include "gpio_groups.h" + +/* + * Names prefixed with an *asterisk are the default. + * (if it's the first column, GPIO is the default, no matter the name) + */ + +static const char *const glk_group_northwest_names[] = { + "*GPIO_0", "JTAG_TCK", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_1", "JTAG_TRST_N", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_2", "JTAG_TMS", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_3", "JTAG_TDI", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_4", "JTAG_TDO", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_5", "JTAGX", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_6", "JTAG_PREQ_N", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_7", "JTAG_PRDY_N", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_8", "N/A", "N/A", "CNV_DEBUG_09", "CNV_DEBUG_00", "N/A", "N/A", + "*GPIO_9", "N/A", "N/A", "CNV_DEBUG_10", "CNV_DEBUG_01", "N/A", "N/A", + "*GPIO_10", "N/A", "N/A", "CNV_DEBUG_11", "CNV_DEBUG_02", "N/A", "N/A", + "*GPIO_11", "N/A", "N/A", "CNV_DEBUG_12", "GNV_DEBUG_03", "N/A", "N/A", + "*GPIO_12", "N/A", "N/A", "GNV_DEBUG_13", "GNV_DEBUG_04", "N/A", "N/A", + "*GPIO_13", "N/A", "N/A", "CNV_DEBUG_14", "CNV_DEBUG_05", "N/A", "N/A", + "*GPIO_14", "N/A", "N/A", "CNV_DEBUG_15", "CNV_DEBUG_06", "N/A", "N/A", + "*GPIO_15", "N/A", "N/A", "CNV_DEBUG_16", "CNV_DEBUG_07", "N/A", "N/A", + "*GPIO_16", "NA", "N/A", "CNV_DEBUG_17", "CNV_DEBUG_08", "N/A", "N/A", + "*GPIO_17", "NA", "CNV_MFUART0_RXD", "CNV_DEBUG_00", "N/A", "N/A", "N/A", + "*GPIO_18", "NA", "N/A", "CNV_MFUART0_TXD", "CNV_DEBUG_01", "N/A", "N/A", + "*GPIO_19", "NA", "N/A", "CNV_MFUART0_RTS_N", "CNV_DEBUG_02", "N/A", "N/A", + "*GPIO_20", "N/A", "CNV_MFUART0_CTS_N","CNV_DEBUG_03", "N/A", "N/A", "N/A", + "*GPIO_21", "N/A", "CNV_MFUART2_RXD", "CNV_DEBUG_04", "N/A", "N/A", "N/A", + "*GPIO_22", "N/A", "CNV_MFU_ART2_TXD", "CNV_DEBUG_05", "N/A", "N/A", "N/A", + "*GPIO_23", "N/A", "CNV_GNSS_PA_BLANKING","CNV_DEBUG_06", "PMIC_STDBY", "N/A", "N/A", + "*GPIO_24", "N/A", "CNV_GNSS_FTA", "CNV_DEBUG_07", "PMIC_PWRGOOD", "N/A", "N/A", + "*GPIO_25", "N/A", "CNV_GNSS_SYSCK", "CNV_DEBUG_08", "PMIC_RESET_N", "N/A", "N/A", + "*GPIO_26", "ISH_GPIO_0", "SIO_UART1_RXD", "ISH_UART1_RXD", "CNV_BT_UART_RXD", "N/A", "N/A", + "*GPIO_27", "ISH_GPIO_1", "SIO_UART1_TXD", "ISH_UART1_TXD", "CNV_BT_UART_TXD", "N/A", "N/A", + "*GPIO_28", "ISH_GPIO_2", "SIO_UART1_RST_N", "SIO_UART1_RST_N", "CNV_BT_UART_RTS_N","N/A", "N/A", + "*GPIO_29", "ISH_GPIO_3", "SIO_UART1_CTS_N", "SIO_UART1_CTS_N", "CNV_BT_UART_CTS_N","N/A", "N/A", + "*GPIO_30", "ISH_GPIO_4", "SATA_GP0", "N/A", "N/A", "N/A", "N/A", + "*GPIO_31", "ISH_GPIO_5", "SATA_GP1", "N/A", "N/A", "N/A", "N/A", + "*GPIO_32", "ISH_GPIO_6", "SATA_DEVSLP0", "N/A", "N/A", "N/A", "N/A", + "*GPIO_33", "ISH_GPIO_7", "SATA_DEVSLP1", "SUSCLK1", "N/A", "N/A", "N/A", + "*GPIO_34", "ISH_GPIO_8", "SATA_LEDN", "SUSCLK2", "N/A", "N/A", "N/A", + "*GPIO_35", "ISH_GPIO_9", "N/A", "N/A", "SPKR", "N/A", "BSSB_CLK", + "*GPIO_36", "N/A", "N/A", "CNV_BTEN", "N/A", "N/A", "BSSB_DI", + "*GPIO_37", "N/A", "N/A", "CNV_GNEN", "N/A", "N/A", "N/A", + "*GPIO_38", "N/A", "N/A", "CNV_WFEN", "N/A", "N/A", "N/A", + "*GPIO_39", "N/A", "N/A", "CNV_WCEN", "N/A", "N/A", "N/A", + "*GPIO_40", "N/A", "N/A", "CNV_BT_HOST_WAKE_N", "N/A", "N/A", "N/A", + "*GPIO_41", "N/A", "N/A", "CNV_GNSS_HOST_WAKEN", "N/A", "N/A", "N/A", + "*GPIO_42", "MDSI_A_TE", "PWM0", "N/A", "N/A", "N/A", "N/A", + "*GPIO_43", "MDSI_C_TE", "PWM1", "N/A", "N/A", "N/A", "N/A", + "*GPIO_44", "USB2_OC0_N", "PWM2", "N/A", "N/A", "N/A", "N/A", + "*GPIO_45", "USB2_OC1_N", "PWM3", "N/A", "N/A", "N/A", "N/A", + "*GPIO_46", "MIPI_I2C_SDA", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_47", "MIPI_I2C_SCL", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_48", "PMC_I2C_SDA", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_49", "PMC_I2C_SCL", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_50", "SIO_I2C0_SDA", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_51", "SIO_I2C0_SCL", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_52", "SIO_I2C1_SDA", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_53", "SIO_I2C1_SCL", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_54", "SIO_I2C2_SDA", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_55", "SIO_I2C2_SCL", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_56", "SIO_I2C3_SDA", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_57", "SIO_I2C3_SCL", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_58", "SIO_I2C4_SDA", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_59", "SIO_I2C4_SCL", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_60", "SIO_UART0_RXD", "ISH_UART0_RXD", "CNV_GNSS_UART_RXD", "N/A", "N/A", "N/A", + "*GPIO_61", "SIO_UART0_TXD", "ISH_UART0_TXD", "CNV_GNSS_UART_TXD", "N/A", "N/A", "N/A", + "*GPIO_62", "SIO_UART0_RTS_N", "ISH_UART0_RTS_N", "CNV_GNSS_UART_RTS_N", "N/A", "N/A", "N/A", + "*GPIO_63", "SIO_UART0_CTS_N", "ISH_UART0_CTS_N", "CNV_GBSS_UART_CTS_N", "N/A", "N/A", "N/A", + "*GPIO_64", "SIO_UART2_RXD", "ISH_UART2_RXD", "CNV_MFUA_RT1_RXD", "N/A", "N/A", "N/A", + "*GPIO_65", "SIO_UART2_TXD", "ISH_UART2_TXD", "CNV_MFUA_RT1_TXD", "N/A", "N/A", "N/A", + "*GPIO_66", "SIO_UART2_RTS_N", "ISH_UART2_RTS_N", "CNV_MFUA_RT1_RTS_N", "N/A", "N/A", "N/A", + "*GPIO_67", "SIO_UART2_CTS_N", "ISH_UART2_CTS_N", "CNV_MFUA_RT1_CTS_N", "N/A", "N/A", "N/A", + "*GPIO_68", "PMC_SPI_DS0", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_69", "PMC_SPI_DS1", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_70", "PMC_SPI_FS2", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_71", "PMC_SPI_RXD", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_72", "PMC_SPI_TXD", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_73", "PMC_SPI_CLK", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_74", "THERMTRIP_N", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_75", "PROCHOT_N", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_211","EMMC_RST_N", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_212","N/A", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_213","N/A", "N/A", "N/A", "N/A", "N/A", "N/A", + "*GPIO_214","N/A", "N/A", "N/A", "N/A", "N/A", "N/A", +}; + +static const char *const glk_group_north_names[] = { + "*GPIO_76", "SVID0_ALERT_N", "N/A", "N/A", "N/A", "N/A", + "*GPIO_77", "SCID0_DATA", "N/A", "N/A", "N/A", "N/A", + "*GPIO_78", "SVID0_CLK", "N/A", "N/A", "N/A", "N/A", + "*GPIO_79", "SIO_SPI_0_CLK", "ISH_SPI_0_CLK", "N/A", "N/A", "N/A", + "*GPIO_80", "SIO_SPI_0_FS0", "ISH_SPI_0_FS0", "N/A", "N/A", "N/A", + "*GPIO_81", "SIO_SPI_0_FS1", "ISH_SPI_0_FS1", "FST_SPI_CS2_N", "N/A", "N/A", + "*GPIO_82", "SIO_SPI_0_RXD", "ISH_SPI_0_RXD", "N/A", "N/A", "N/A", + "*GPIO_83", "SIO_SPI_0_TXD", "ISH_SPI_0_TXD", "N/A", "N/A", "N/A", + "*GPIO_84", "SIO_SPI_2_CLK", "ISH_SPI_1_CLK", "TOUCH_SPI_CLK", "N/A", "N/A", + "*GPIO_85", "SIO_SPI_2_FS0", "ISH_SPI_1_FS0", "TOUCH_SPI_FS0", "N/A", "N/A", + "*GPIO_86", "SIO_SPI_2_FS1", "ISH_SPI_1_FS1", "TOUCH_SPI_D0", "N/A", "N/A", + "*GPIO_87", "SIO_SPI_2_FS2", "N/A", "TOUCH_SPI_D1", "N/A", "N/A", + "*GPIO_88", "SIO_SPI_2_RXD", "ISH_SPI_1_RXD", "TOUCH_SPI_D2", "N/A", "N/A", + "*GPIO_89", "SIO_SPI_2_TXD", "ISH_SPI_1_TXD", "TOUCH_SPI_D3", "N/A", "N/A", + "*GPIO_90", "FST_SPI_CS0_N", "N/A", "N/A", "N/A", "N/A", + "*GPIO_91", "FST_SPI_CS1_N", "N/A", "N/A", "N/A", "N/A", + "*GPIO_92", "FST_SPI_MOSI_IO0", "N/A", "N/A", "N/A", "N/A", + "*GPIO_93", "FST_SPI_MISO_IO1", "N/A", "N/A", "N/A", "N/A", + "*GPIO_94", "FST_SPI_IO2", "N/A", "N/A", "N/A", "N/A", + "*GPIO_95", "FST_SPI_IO_3", "N/A", "N/A", "N/A", "N/A", + "*GPIO_96", "FST_SPI_CLK", "N/A", "N/A", "N/A", "N/A", + "*GPIO_98", "PMU_PLTRST_N", "N/A", "N/A", "N/A", "N/A", + "*GPIO_99", "PMU_PWRBTN_N", "N/A", "N/A", "N/A", "N/A", + "*GPIO_100","PMU_SLP_S_3_N", "N/A", "N/A", "N/A", "N/A", + "*GPIO_101","PMU_SLP_S_4_N", "N/A", "N/A", "N/A", "N/A", + "*GPIO_102","SUSPWRDNACK", "N/A", "N/A", "N/A", "N/A", + "*GPIO_103","EMMC_PWR_EN_N", "N/A", "N/A", "N/A", "N/A", + "*GPIO_104","JTAG_TRST_N", "N/A", "N/A", "N/A", "N/A", + "*GPIO_105","JTAG_TRST_N", "N/A", "N/A", "N/A", "N/A", + "*GPIO_106","PMU_BATLOW_N", "N/A", "N/A", "N/A", "N/A", + "*GPIO_107","PMU_RSTBTN_N", "N/A", "N/A", "N/A", "N/A", + "*GPIO_108","PMU_SUSCLK", "N/A", "N/A", "N/A", "N/A", + "*GPIO_109","SUS_STAT_N", "N/A", "N/A", "N/A", "N/A", + "*GPIO_110","SIO_I2C5_SDA", "ISH_I2C0_SDA", "N/A", "N/A", "N/A", + "*GPIO_111","SIO_I2C5_SCL", "ISH_I2C0_SCL", "N/A", "N/A", "N/A", + "*GPIO_112","SIO_I2C6_SDA", "ISH_I2C1_SDA", "N/A", "N/A", "N/A", + "*GPIO_113","SIO_I2C6_SCL", "ISH_I2C1_SCL", "N/A", "N/A", "N/A", + "*GPIO_114","SIO_I2C7_SDA", "ISH_I2C2_SDA", "N/A", "N/A", "N/A", + "*GPIO_115","SIO_I2C7_SCL", "ISH_I2C2_SCL", "N/A", "N/A", "N/A", + "*GPIO_116","PCIE_WAKE0_N", "N/A", "N/A", "N/A", "N/A", + "*GPIO_117","PCIE_WAKE1_N", "N/A", "N/A", "N/A", "N/A", + "*GPIO_118","PCIE_WAKE2_N", "N/A", "N/A", "N/A", "N/A", + "*GPIO_119","PCIE_WAKE3_N", "N/A", "N/A", "N/A", "N/A", + "*GPIO_120","PCIE_CLKREQ0_N", "N/A", "N/A", "N/A", "N/A", + "*GPIO_121","PCIE_CLKREQ1_N", "N/A", "N/A", "N/A", "N/A", + "*GPIO_122","PCIE_CLKREQ2_N", "N/A", "N/A", "N/A", "N/A", + "*GPIO_123","PCIE_CLKREQ3_N", "N/A", "N/A", "N/A", "N/A", + "*GPIO_124","DDI0_DDC_SDA", "N/A", "N/A", "N/A", "N/A", + "*GPIO_125","DDI0_DDC_SCL", "N/A", "N/A", "N/A", "N/A", + "*GPIO_126","DDI1_DDC_SDA", "SIO_I2C5_SDA", "N/A", "N/A", "N/A", + "*GPIO_127","DDI1_DDC_SCL", "SIO_I2C5_SCL", "N/A", "N/A", "N/A", + "*GPIO_128","PNL0_VDDEN", "N/A", "N/A", "N/A", "N/A", + "*GPIO_129","PNL0_BKLTEN", "N/A", "N/A", "N/A", "N/A", + "*GPIO_130","PNL0_BKLCTL", "N/A", "N/A", "N/A", "N/A", + "*GPIO_131","DDI0_HPD", "N/A", "N/A", "N/A", "N/A", + "*GPIO_132","DDI1_HPD", "N/A", "N/A", "N/A", "N/A", + "*GPIO_133","DDI2_HPD", "N/A", "N/A", "N/A", "N/A", + "*GPIO_134","N/A", "N/A", "N/A", "ISH_GPIO_10", "N/A", + "*GPIO_135","N/A", "N/A", "N/A", "ISH_GPIO_11", "N/A", + "*GPIO_136","N/A", "N/A", "N/A", "ISH_GPIO_12", "N/A", + "*GPIO_137","N/A", "N/A", "N/A", "ISH_GPIO_13", "N/A", + "*GPIO_138","N/A", "SIO_UART3_RXD", "ISH_UART0_RXD", "ISH_GPIO_14", "SATA_GP0", + "*GPIO_139","N/A", "SIO_UART3_TXD", "ISH_UART0_TXD", "ISH_GPIO_15", "SATA_GP1", + "*GPIO_140","N/A", "SIO_UART3_RTS_N", "ISH_UART0_RTS_N", "N/A", "SATA_DEVSLP0", + "*GPIO_141","N/A", "SIO_UART3_CTS_N", "SIO_UART0_CTS_N", "N/A", "SATA_DEVSLP1", + "*GPIO_142","N/A", "SIO_SPI_1_CLK", "ISH_SPI_0_CLK", "N/A", "SATA_LE_DN", + "*GPIO_143","N/A", "SIO_SPI_1_FS0", "ISH_SPI_0_FS0", "JTAG2_TCK", "N/A", + "*GPIO_144","N/A", "SIO_SPI_1_FS1", "ISH_SPI_0_FS1", "JTAG2_TDI", "PNL1_VDDEN", + "*GPIO_145","N/A", "SIO_SPI_1_RXD", "ISH_SPI_0_RXD", "JTAG2_TMS", "PNL1_BKLTEN", + "*GPIO_146","N/A", "SIO_SPI_1_TXD", "ISH_SPI_0_TXD", "JTAG2_TDO", "PNL1_BKLTCTL", + "*GPIO_147","LPC_SERIRQ", "ESPI_RESET_N", "N/A", "N/A", "N/A", + "*GPIO_148","LPC_CLKOUT0", "ESPI_CLK", "N/A", "N/A", "N/A", + "*GPIO_149","LPC_CLKOUT1", "N/A", "N/A", "N/A", "N/A", + "*GPIO_150","LPC_AD0", "ESPI_IO_0", "N/A", "N/A", "N/A", + "*GPIO_151","LPC_AD1", "ESPI_IO_1", "N/A", "N/A", "N/A", + "*GPIO_152","LPC_AD2", "ESPI_IO_2", "N/A", "N/A", "N/A", + "*GPIO_153","LPC_AD3", "ESPI_IO_3", "N/A", "N/A", "N/A", + "*GPIO_154","LPC_CLKRUN_N", "N/A", "N/A", "N/A", "N/A", + "*GPIO_155","LPC_FRAME_N", "ESPI_CS_N", "N/A", "N/A", "N/A", +}; + +static const char *const glk_group_audio_names[] = { + "*GPIO_156", "AVS_I2S0_MCLK", "N/A", "N/A", + "*GPIO_157", "AVS_I2S0_BCLK", "N/A", "N/A", + "*GPIO_158", "AVS_I2S0_WS_SYNC", "N/A", "N/A", + "*GPIO_159", "AVS_I2S0_SDI", "N/A", "N/A", + "*GPIO_160", "AVS_I2S0_SDO", "N/A", "N/A", + "*GPIO_161", "AVS_I2S1_MCLK", "N/A", "N/A", + "*GPIO_162", "AVS_I2S1_BCLK", "N/A", "CNV_BT_I2S_BCLK", + "*GPIO_163", "AVS_I2S1_WS_SYNC", "N/A", "CNV_BT_I2S_WS_SYNC", + "*GPIO_164", "AVS_I2S1_SDI", "N/A", "CNV_BT_I2S_SD1", + "*GPIO_165", "AVS_I2S1_SDO", "N/A", "CNV_BT_I2S_SD0", + "*GPIO_166", "AVS_HDA_B_CLK", "AVS_I2S2_BCLK", "N/A", + "*GPIO_167", "AVS_HDA_WS_SYNC", "AVS_I2S2_WS_SYNC", "N/A", + "*GPIO_168", "AVS_HDS_SDI", "AVS_I2S2_SDI", "N/A", + "*GPIO_169", "AVS_HDA_SDO", "AVS_I2S2_SDO", "N/A", + "*GPIO_170", "AVS_HDA_RST_N", "AVS_I2S1_MCLK", "N/A", + "*GPIO_171", "AVS_DMIC_CLK_A1", "N/A", "N/A", + "*GPIO_172", "AVS_DMIC_CLK_B1", "N/A", "N/A", + "*GPIO_173", "AVS_DMIC_DATA_1", "N/A", "N/A", + "*GPIO_174", "AVS_DMIC_CLK_AB2", "N/A", "N/A", + "*GPIO_175", "AVS_DMIC_DATA_2", "N/A", "N/A", +}; + +static const char *const glk_group_scc_names[] = { + "*GPIO_176","SMB_ALERT_N", "N/A", "N/A", + "*GPIO_177","SMB_CLK", "SIO_I2C7_SCL", "N/A", + "*GPIO_178","SMB_DATA", "SIO_I2C7_SDA", "N/A", + "*GPIO_179","SDACARD_CLK", "N/A", "N/A", + "*GPIO_181","SDCARD_D0", "N/A", "N/A", + "*GPIO_182","SDCARD_D1", "N/A", "N/A", + "*GPIO_183","SDCARD_D2", "N/A", "N/A", + "*GPIO_184","SDCARD_D3", "N/A", "N/A", + "*GPIO_185","SDCARD_CMD", "N/A", "N/A", + "*GPIO_186","SDCARD_CD_N", "N/A", "N/A", + "*GPIO_187","SDCARD_LVL_WP", "N/A", "N/A", + "*GPIO_188","SDCARD_PWR_DWN_N", "N/A", "N/A", + "*GPIO_210","N/A", "N/A", "N/A", + "*GPIO_189","OSC_CLK_OUT_0", "N/A", "N/A", + "*GPIO_190","OSC_CLK_OUT_1", "N/A", "N/A", + "*GPIO_191","CNV_BRI_DT", "N/A", "SIO_UART1_RTS_N", + "*GPIO_192","CNV_BRI_RSP", "N/A", "SIO_UART1_RXD", + "*GPIO_193","CNV_RGI_DT", "N/A", "SIO_UART1_TXD", + "*GPIO_194","CNV_RGI_RSP", "N/A", "SIO_UART1_CTS_N", + "*GPIO_195","CNV_RF_RESET_N", "N/A", "AVS_I2S1_WS_SYNC", + "*GPIO_196","XTAL_CLKREQ", "N/A", "AVS_I2S1_SDO", + "*GPIO_198","EMMC_CLK", "N/A", "N/A", + "*GPIO_200","EMMC_D0", "N/A", "N/A", + "*GPIO_201","EMMC_D1", "N/A", "N/A", + "*GPIO_202","EMMC_D2", "N/A", "N/A", + "*GPIO_203","EMMC_D3", "N/A", "N/A", + "*GPIO_204","EMMC_D4", "N/A", "N/A", + "*GPIO_205","EMMC_D5", "N/A", "N/A", + "*GPIO_206","EMMC_D6", "N/A", "N/A", + "*GPIO_207","EMMC_D7", "N/A", "N/A", + "*GPIO_208","EMMC_CMD", "N/A", "N/A", + "*GPIO_209","EMMC_RCLK", "N/A", "N/A", +}; + +static const struct gpio_group glk_group_northwest = { + .display = "----- GPIO Group NorthWest -----", + .pad_count = ARRAY_SIZE(glk_group_northwest_names) / 7, + .func_count = 7, + .pad_names = glk_group_north_names, +}; + +static const struct gpio_group *const glk_community_northwest_groups[] = { + &glk_group_northwest, +}; + +static const struct gpio_community glk_community_northwest = { + .name = "--- GPIO Community NorthWest ---", + .pcr_port_id = 0xc4, + .group_count = ARRAY_SIZE(glk_community_northwest_groups), + .groups = glk_community_northwest_groups, +}; + +static const struct gpio_group glk_group_north = { + .display = "------- GPIO Group North -------", + .pad_count = ARRAY_SIZE(glk_group_north_names) / 6, + .func_count = 6, + .pad_names = glk_group_north_names, +}; + +static const struct gpio_group *const glk_community_north_groups[] = { + &glk_group_north, +}; + +static const struct gpio_community glk_community_north = { + .name = "----- GPIO Community North -----", + .pcr_port_id = 0xc5, + .group_count = ARRAY_SIZE(glk_community_north_groups), + .groups = glk_community_north_groups, +}; + +static const struct gpio_group glk_group_audio = { + .display = "------- GPIO Group Audio -------", + .pad_count = ARRAY_SIZE(glk_group_audio_names) / 4, + .func_count = 4, + .pad_names = glk_group_audio_names, +}; + +static const struct gpio_group *const glk_community_audio_groups[] = { + &glk_group_audio, +}; + +static const struct gpio_community glk_community_audio = { + .name = "----- GPIO Community Audio -----", + .pcr_port_id = 0xc9, + .group_count = ARRAY_SIZE(glk_community_audio_groups), + .groups = glk_community_audio_groups, +}; + +static const struct gpio_group glk_group_scc = { + .display = "-------- GPIO Group SCC --------", + .pad_count = ARRAY_SIZE(glk_group_scc_names) / 4, + .func_count = 4, + .pad_names = glk_group_scc_names, +}; + +static const struct gpio_group *const glk_community_scc_groups[] = { + &glk_group_scc, +}; + +static const struct gpio_community glk_community_scc = { + .name = "------ GPIO Community SCC ------", + .pcr_port_id = 0xc8, + .group_count = ARRAY_SIZE(glk_community_scc_groups), + .groups = glk_community_scc_groups, +}; + +static const struct gpio_community *const geminilake_communities[] = { + &glk_community_northwest, &glk_community_north, + &glk_community_audio, &glk_community_scc, +}; + +#endif diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index a528485..0487b01 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -246,6 +246,8 @@ #define PCI_DEVICE_ID_INTEL_I5000V 0x25d4 #define PCI_DEVICE_ID_INTEL_I5000P 0x25d8 +#define PCI_DEVICE_ID_INTEL_GLK_LPC 0x31E8 + /* untested, but almost identical to D-series */ #define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010 -- To view, visit https://review.coreboot.org/c/coreboot/+/51130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I017789c9e23e355214deced29efcb3532c449981 Gerrit-Change-Number: 51130 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1003165 Gerrit-Reviewer: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Attention: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: vendor: mediatek: Add mediatek mt8192 dram initialization codes
by Xi Chen (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Hung-Te Lin, Nico Huber, Martin Roth, Paul Menzel, Yu-Ping Wu. Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50294 ) Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization codes ...................................................................... Patch Set 9: (6 comments) File src/vendorcode/Makefile.inc: https://review.coreboot.org/c/coreboot/+/50294/comment/f6db3e42_4306cbba PS8, Line 7: # > remove this comment? For build pass because coreboot soc dram calibration code already exists, will enable when vendorcode & soc code are ready. File src/vendorcode/mediatek/Kconfig: https://review.coreboot.org/c/coreboot/+/50294/comment/535772ef_44868f8e PS9, Line 9: config MT8192_DRAM_EMCP : bool : default y : help : The eMCP platform should select this option to run at different DRAM : frequencies. > Is this still used? I thought we are using sdram_params for EMCP now. no used, will remove. File src/vendorcode/mediatek/mt8192/Makefile.inc: https://review.coreboot.org/c/coreboot/+/50294/comment/a57d27e5_4128bbfa PS9, Line 7: ramstage-y += dpm.c > why is dpm included? will move to soc folder. https://review.coreboot.org/c/coreboot/+/50294/comment/2cd1ec72_a1b744cb PS9, Line 9: BL31_MAKEARGS += PLAT=mt8192 > we don't need this? yes, no need, will remove. File src/vendorcode/mediatek/mt8192/dpm.c: https://review.coreboot.org/c/coreboot/+/50294/comment/0db70b52_a83e12c8 PS9, Line 1: License > dpm should not be in DRAM code? will move to soc folder. File src/vendorcode/mediatek/mt8192/memory.c: https://review.coreboot.org/c/coreboot/+/50294/comment/2006dbf4_3ec01090 PS9, Line 1: License > this file should be in soc folder. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/50294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 Gerrit-Change-Number: 50294 Gerrit-PatchSet: 9 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Cindy Ching <cindy.ching(a)mediatek.corp-partner.google.com> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 01 Mar 2021 08:59:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: vendor: mediatek: Add mediatek mt8192 dram initialization codes
by Hung-Te Lin (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Xi Chen, Nico Huber, Martin Roth, Paul Menzel, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50294 ) Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization codes ...................................................................... Patch Set 9: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/50294/comment/41c7419d_21efc86b PS9, Line 9: Add the DRAM initialization code based on Mediatek reference implementation. This is the DRAM calibration code from the reference implementation (also known as ETT, EMI Timing Tuning) released by Mediatek for MT8192. https://review.coreboot.org/c/coreboot/+/50294/comment/52421c37_ecc8cf62 PS9, Line 11: Mediatek internally maintains the DRAM initialization code, following : different coding style. : : To prevent maintaining a different branch for coreboot : (which may lead to typo or errors which switching between different coding : style), we want to directly use the reference implementation as vendor code. The ETT is a standalone library, used by different boot loaders for initializing DRAM and following a different coding style (coreboot was using Linux Kernel coding style) so we have to put it in vendor code folder. File src/vendorcode/mediatek/mt8192/dram_init.c: https://review.coreboot.org/c/coreboot/+/50294/comment/b0ca5c62_053d8f2a PS9, Line 59: void _start(void *config) __attribute__((section(".text.start"))); : void _start(void *config) : { : dram_init(config); : } : I think we should remove this if you don't have a plan to build blob here. File src/vendorcode/mediatek/mt8192/memory.c: https://review.coreboot.org/c/coreboot/+/50294/comment/a3216246_b576d6d7 PS9, Line 1: License this file should be in soc folder. -- To view, visit https://review.coreboot.org/c/coreboot/+/50294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 Gerrit-Change-Number: 50294 Gerrit-PatchSet: 9 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Cindy Ching <cindy.ching(a)mediatek.corp-partner.google.com> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 01 Mar 2021 08:56:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: vendor: mediatek: Add mediatek mt8192 dram initialization codes
by Hung-Te Lin (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Xi Chen, Nico Huber, Martin Roth, Paul Menzel, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50294 ) Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization codes ...................................................................... Patch Set 9: (5 comments) File src/vendorcode/Makefile.inc: https://review.coreboot.org/c/coreboot/+/50294/comment/b2769ec1_839e1d3b PS8, Line 7: # remove this comment? File src/vendorcode/mediatek/Kconfig: https://review.coreboot.org/c/coreboot/+/50294/comment/f74dae0f_95c8e200 PS9, Line 9: config MT8192_DRAM_EMCP : bool : default y : help : The eMCP platform should select this option to run at different DRAM : frequencies. Is this still used? I thought we are using sdram_params for EMCP now. File src/vendorcode/mediatek/mt8192/Makefile.inc: https://review.coreboot.org/c/coreboot/+/50294/comment/59f4dca7_cd5c2cab PS9, Line 7: ramstage-y += dpm.c why is dpm included? https://review.coreboot.org/c/coreboot/+/50294/comment/57a8d5df_8f6e4783 PS9, Line 9: BL31_MAKEARGS += PLAT=mt8192 we don't need this? File src/vendorcode/mediatek/mt8192/dpm.c: https://review.coreboot.org/c/coreboot/+/50294/comment/86486115_980f5621 PS9, Line 1: License dpm should not be in DRAM code? -- To view, visit https://review.coreboot.org/c/coreboot/+/50294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 Gerrit-Change-Number: 50294 Gerrit-PatchSet: 9 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Cindy Ching <cindy.ching(a)mediatek.corp-partner.google.com> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 01 Mar 2021 08:39:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel: Include gfx.asl from northbridge
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49123 ) Change subject: soc/intel: Include gfx.asl from northbridge ...................................................................... soc/intel: Include gfx.asl from northbridge The iGPU is on the northbridge or system agent, not the southbridge. Change-Id: Ic63a7ad532fd1faa8e90d44bf7269040fa901757 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/apollolake/acpi/northbridge.asl M src/soc/intel/apollolake/acpi/southbridge.asl M src/soc/intel/cannonlake/acpi/southbridge.asl M src/soc/intel/common/block/acpi/acpi/northbridge.asl M src/soc/intel/elkhartlake/acpi/southbridge.asl M src/soc/intel/icelake/acpi/southbridge.asl M src/soc/intel/jasperlake/acpi/southbridge.asl M src/soc/intel/skylake/acpi/pch.asl M src/soc/intel/skylake/acpi/systemagent.asl M src/soc/intel/tigerlake/acpi/southbridge.asl 10 files changed, 9 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/49123/1 diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index 1450983..6a71900 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -114,3 +114,6 @@ Return (MCRS) } + +/* GFX 00:02.0 */ +#include <drivers/intel/gma/acpi/gfx.asl> diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 4d4e4dc..f4d1497 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -17,9 +17,6 @@ #include "xhci.asl" -/* GFX 00:02.0 */ -#include <drivers/intel/gma/acpi/gfx.asl> - /* LPC */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index f091d8f..01c2250 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -16,9 +16,6 @@ #include "gpio.asl" #endif -/* GFX 00:02.0 */ -#include <drivers/intel/gma/acpi/gfx.asl> - /* LPC 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index 5780f4c..89495a9 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -309,3 +309,6 @@ Return (BUF0) } } + +/* GFX 00:02.0 */ +#include <drivers/intel/gma/acpi/gfx.asl> diff --git a/src/soc/intel/elkhartlake/acpi/southbridge.asl b/src/soc/intel/elkhartlake/acpi/southbridge.asl index 02425c4..ccad776 100644 --- a/src/soc/intel/elkhartlake/acpi/southbridge.asl +++ b/src/soc/intel/elkhartlake/acpi/southbridge.asl @@ -14,9 +14,6 @@ /* GPIO controller */ #include "gpio.asl" -/* GFX 00:02.0 */ -#include <drivers/intel/gma/acpi/gfx.asl> - /* ESPI 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl index 925f28f..4abea7c 100644 --- a/src/soc/intel/icelake/acpi/southbridge.asl +++ b/src/soc/intel/icelake/acpi/southbridge.asl @@ -17,9 +17,6 @@ /* GPIO controller */ #include "gpio.asl" -/* GFX 00:02.0 */ -#include <drivers/intel/gma/acpi/gfx.asl> - /* ESPI 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/jasperlake/acpi/southbridge.asl b/src/soc/intel/jasperlake/acpi/southbridge.asl index b97ec58..e623cc3 100644 --- a/src/soc/intel/jasperlake/acpi/southbridge.asl +++ b/src/soc/intel/jasperlake/acpi/southbridge.asl @@ -17,9 +17,6 @@ /* GPIO controller */ #include "gpio.asl" -/* GFX 00:02.0 */ -#include <drivers/intel/gma/acpi/gfx.asl> - /* ESPI 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 02e30f7..6eea5bb 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -65,6 +65,3 @@ #if CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) #include <soc/intel/common/acpi/sgx.asl> #endif - -/* Integrated graphics 0:2.0 */ -#include <drivers/intel/gma/acpi/gfx.asl> diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl index 962d9ef..c81e9f5 100644 --- a/src/soc/intel/skylake/acpi/systemagent.asl +++ b/src/soc/intel/skylake/acpi/systemagent.asl @@ -322,3 +322,6 @@ Return (BUF0) } } + +/* Integrated graphics 0:2.0 */ +#include <drivers/intel/gma/acpi/gfx.asl> diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index 744b7ef..3a53f2c 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -17,9 +17,6 @@ /* GPIO controller */ #include "gpio.asl" -/* GFX 00:02.0 */ -#include <drivers/intel/gma/acpi/gfx.asl> - /* ESPI 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/49123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic63a7ad532fd1faa8e90d44bf7269040fa901757 Gerrit-Change-Number: 49123 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: mb/google/zork/var/shuboz: Decrease I2C3 CLK below 400 kHz
by Patrick Georgi (Code Review) 01 Mar '21

01 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51052 ) Change subject: mb/google/zork/var/shuboz: Decrease I2C3 CLK below 400 kHz ...................................................................... mb/google/zork/var/shuboz: Decrease I2C3 CLK below 400 kHz Modify I2C3 setting to follow I2C specification (lower than 400kHz). Original setting: .rise_time_ns = 184 .fall_time_ns = 42 Change to: .rise_time_ns = 110 .fall_time_ns = 34 BUG=b:181091107 BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: Ibdbb9a7dde524bdbde4789ee7ea005646080d97a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51052 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/mainboard/google/zork/variants/shuboz/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Kane Chen: Looks good to me, but someone else must approve Kangheui Won: Looks good to me, approved diff --git a/src/mainboard/google/zork/variants/shuboz/overridetree.cb b/src/mainboard/google/zork/variants/shuboz/overridetree.cb index 436f0ed..16c18b5 100644 --- a/src/mainboard/google/zork/variants/shuboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/shuboz/overridetree.cb @@ -35,8 +35,8 @@ register "i2c[3]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 184, /* 0 to 1.26v (1.8 * .7) */ - .fall_time_ns = 42, /* 1.26v to 0 */ + .rise_time_ns = 110, /* 0 to 1.26v (1.8 * .7) */ + .fall_time_ns = 34, /* 1.26v to 0 */ .early_init = true, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/51052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdbb9a7dde524bdbde4789ee7ea005646080d97a Gerrit-Change-Number: 51052 Gerrit-PatchSet: 3 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: merged

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coreboot-gerrit March 2021