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Change in coreboot[master]: soc/rockchip/rk3399/sdram: Introduce pctl_start
by Moritz Fischer (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Julius Werner. Moritz Fischer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51129 ) Change subject: soc/rockchip/rk3399/sdram: Introduce pctl_start ...................................................................... soc/rockchip/rk3399/sdram: Introduce pctl_start Adapted from u-boot commit a0aebe8398 ("ram: rk3399: Add pctl start support") Contains fix from u-boot commit 410d7863bc ("ram: rk3399: fix error about get_ddrc0_con reg addr") Change-Id: Idcea403218ba96ec48c889709b73df4e8882d825 Signed-off-by: Moritz Fischer <moritzf(a)google.com> --- M src/soc/rockchip/rk3399/sdram.c 1 file changed, 49 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/51129/1 diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 718cc02..c7982f9 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -94,6 +94,11 @@ u32 pwrup_srefresh_exit[MAX_DRAM_CHANNELS]; +static void *get_ddrc0_con(u32 channel) +{ + return channel ? &rk3399_grf->ddrc1_con0 : &rk3399_grf->ddrc0_con0; +} + static void copy_to_reg(u32 *dest, const u32 *src, u32 n) { int i; @@ -331,6 +336,44 @@ clrsetbits32(&denali_phy[930], 0x1 << 17, reg_value); } +static int pctl_start(u32 channel) +{ + u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy; + u32 *denali_ctl = rk3399_ddr_pctl[channel]->denali_ctl; + u32 *ddrc0_con = get_ddrc0_con(channel); + struct stopwatch sw; + u32 byte, tmp; + + write32(&ddrc0_con, 0x01000000); + + clrsetbits32(&denali_phy[957], 0x3 << 24, 0x2 << 24); + + stopwatch_init_msecs_expire(&sw, 100); + while (!(read32(&denali_ctl[203]) & (1 << 3))) { + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "Failed to init pctl for channel %d\n", + channel); + return -1; + } + } + + write32(&ddrc0_con, 0x01000100); + + for (byte = 0; byte < 4; byte++) { + tmp = 0x820; + write32(&denali_phy[53 + (128 * byte)], (tmp << 16) | tmp); + write32(&denali_phy[54 + (128 * byte)], (tmp << 16) | tmp); + write32(&denali_phy[55 + (128 * byte)], (tmp << 16) | tmp); + write32(&denali_phy[56 + (128 * byte)], (tmp << 16) | tmp); + write32(&denali_phy[57 + (128 * byte)], (tmp << 16) | tmp); + + clrsetbits32(&denali_phy[58 + (128 * byte)], 0xffff, tmp); + } + + clrsetbits32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, pwrup_srefresh_exit[channel]); + return 0; +} + static void phy_io_config(u32 channel, const struct rk3399_sdram_params *params) { u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy; @@ -489,7 +532,6 @@ const u32 *params_ctl = params->pctl_regs.denali_ctl; const u32 *params_phy = params->phy_regs.denali_phy; u32 tmp, tmp1, tmp2; - struct stopwatch sw; /* * work around controller bug: @@ -565,18 +607,6 @@ phy_io_config(channel, params); - /* PHY_DLL_RST_EN */ - clrsetbits32(&denali_phy[957], 0x3 << 24, 0x2 << 24); - - /* FIXME: need to care ERROR bit */ - stopwatch_init_msecs_expire(&sw, 100); - while (!(read32(&denali_ctl[203]) & (1 << 3))) { - if (stopwatch_expired(&sw)) - return -1; - } - - clrsetbits32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, - pwrup_srefresh_exit[channel]); return 0; } @@ -1140,6 +1170,12 @@ board_reset(); } + /* start to trigger initialization */ + if (pctl_start(channel)) { + printk(BIOS_ERR, "Channel %d pctl_start fail\n", channel); + board_reset(); + } + /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ if (dramtype == LPDDR3) udelay(10); -- To view, visit https://review.coreboot.org/c/coreboot/+/51129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcea403218ba96ec48c889709b73df4e8882d825 Gerrit-Change-Number: 51129 Gerrit-PatchSet: 1 Gerrit-Owner: Moritz Fischer <moritzf(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/rockchip/rk3399/sdram: Move pwrup_srefresh_exit to array
by Moritz Fischer (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Julius Werner. Moritz Fischer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51128 ) Change subject: soc/rockchip/rk3399/sdram: Move pwrup_srefresh_exit to array ...................................................................... soc/rockchip/rk3399/sdram: Move pwrup_srefresh_exit to array Move to an array to allow independent (per channel) values in later changes. Adapted from u-boot commit fe42d4a19907 ("ram: rk3399: Move pwrup_srefresh_exit to dram_info") Change-Id: I84fe0bc2dbc9874facfa35534b871ec049cb26bb Signed-off-by: Moritz Fischer <moritzf(a)google.com> --- M src/soc/rockchip/rk3399/sdram.c 1 file changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/51128/1 diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index be1da59..718cc02 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -90,6 +90,9 @@ #define PHY_DRV_ODT_34_3 (0xf) #define MAX_RANKS_PER_CHANNEL 4 +#define MAX_DRAM_CHANNELS 2 + +u32 pwrup_srefresh_exit[MAX_DRAM_CHANNELS]; static void copy_to_reg(u32 *dest, const u32 *src, u32 n) { @@ -486,7 +489,6 @@ const u32 *params_ctl = params->pctl_regs.denali_ctl; const u32 *params_phy = params->phy_regs.denali_phy; u32 tmp, tmp1, tmp2; - u32 pwrup_srefresh_exit; struct stopwatch sw; /* @@ -505,7 +507,7 @@ write32(&denali_phy[911], params->phy_regs.denali_phy[911]); write32(&denali_phy[912], params->phy_regs.denali_phy[912]); - pwrup_srefresh_exit = read32(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT; + pwrup_srefresh_exit[channel] = read32(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT; clrbits32(&denali_ctl[68], PWRUP_SREFRESH_EXIT); /* PHY_DLL_RST_EN */ @@ -574,7 +576,7 @@ } clrsetbits32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, - pwrup_srefresh_exit); + pwrup_srefresh_exit[channel]); return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/51128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84fe0bc2dbc9874facfa35534b871ec049cb26bb Gerrit-Change-Number: 51128 Gerrit-PatchSet: 1 Gerrit-Owner: Moritz Fischer <moritzf(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/rockchip/rk3399/sdram: Add channel to error message
by Moritz Fischer (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Julius Werner. Moritz Fischer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51127 ) Change subject: soc/rockchip/rk3399/sdram: Add channel to error message ...................................................................... soc/rockchip/rk3399/sdram: Add channel to error message When printing error information during DRAM training, be more verbose by printing the channel number. Change-Id: If4109bd0573e3d9f90d699d89350ddbcc48714d3 Signed-off-by: Moritz Fischer <moritzf(a)google.com> --- M src/soc/rockchip/rk3399/sdram.c 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/51127/1 diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 6d58b6a..be1da59 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -939,7 +939,7 @@ if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) { ret = data_training_ca(channel, params); if (ret) { - printk(BIOS_ERR, "CA training failed\n"); + printk(BIOS_ERR, "Channel %d CA training failed\n", channel); return ret; } } @@ -948,7 +948,7 @@ if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) { ret = data_training_wl(channel, params); if (ret) { - printk(BIOS_ERR, "WL training failed\n"); + printk(BIOS_ERR, "Channel %d WL training failed\n", channel); return ret; } } @@ -957,7 +957,7 @@ if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) { ret = data_training_rg(channel, params); if (ret) { - printk(BIOS_ERR, "RG training failed\n"); + printk(BIOS_ERR, "Channel %d RG training failed\n", channel); return ret; } } @@ -966,7 +966,7 @@ if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) { ret = data_training_rl(channel, params); if (ret) { - printk(BIOS_ERR, "RL training failed\n"); + printk(BIOS_ERR, "Channel %d RL training failed\n", channel); return ret; } } @@ -975,7 +975,7 @@ if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) { ret = data_training_wdql(channel, params); if (ret) { - printk(BIOS_ERR, "WDQL training failed\n"); + printk(BIOS_ERR, "Channel %d WDQL training failed\n", channel); return ret; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/51127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4109bd0573e3d9f90d699d89350ddbcc48714d3 Gerrit-Change-Number: 51127 Gerrit-PatchSet: 1 Gerrit-Owner: Moritz Fischer <moritzf(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/rockchip/rk3399/sdram: Simplify error condition
by Moritz Fischer (Code Review) 01 Mar '21

01 Mar '21

Moritz Fischer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51126 ) Change subject: soc/rockchip/rk3399/sdram: Simplify error condition ...................................................................... soc/rockchip/rk3399/sdram: Simplify error condition There is no need for explicit 0 comparison, any return value not equal to 0 is treated as error. Change-Id: I72612af4108a616b6247ee68c8ac2a53242b0853 Signed-off-by: Moritz Fischer <moritzf(a)google.com> --- M src/soc/rockchip/rk3399/sdram.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/51126/1 diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 0fdef71..6d58b6a 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -1133,7 +1133,7 @@ * step may fail, before that, we just reset the * system, and start again. */ - if (pctl_cfg(channel, params) != 0) { + if (pctl_cfg(channel, params)) { printk(BIOS_ERR, "pctl_cfg fail, reset\n"); board_reset(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/51126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72612af4108a616b6247ee68c8ac2a53242b0853 Gerrit-Change-Number: 51126 Gerrit-PatchSet: 1 Gerrit-Owner: Moritz Fischer <moritzf(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpi: Add acpigen_write_{a}pic_* helpers for generating _PRT
by Lance Zhao (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Arthur Heymans. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51107 ) Change subject: acpi: Add acpigen_write_{a}pic_* helpers for generating _PRT ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia666bd0e5db40d7873532dc22bc89be9854b903a Gerrit-Change-Number: 51107 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 01 Mar 2021 02:55:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/shadowmountain: Enable Type-C subsystem
by V Sowmya (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: V Sowmya, Subrata Banik, Aamir Bohra. Hello build bot (Jenkins), Angel Pons, Subrata Banik, Aamir Bohra, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51026 to look at the new patch set (#5). Change subject: mb/intel/shadowmountain: Enable Type-C subsystem ...................................................................... mb/intel/shadowmountain: Enable Type-C subsystem This patch adds the changes to enable the TCSS. BUG=b:175808146 TEST= Boot shadowmountain board, verify the TCSS functionality. Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: Ieaf1170ca718a14d24b773a4a85516e0bbfbb569 --- M src/mainboard/intel/shadowmountain/Kconfig M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb 2 files changed, 49 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/51026/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/51026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaf1170ca718a14d24b773a4a85516e0bbfbb569 Gerrit-Change-Number: 51026 Gerrit-PatchSet: 5 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/smmstore: Print memory-mapped address of store
by Benjamin Doron (Code Review) 01 Mar '21

01 Mar '21

Benjamin Doron has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/49649 ) Change subject: drivers/smmstore: Print memory-mapped address of store ...................................................................... Abandoned The issue this was intended to debug (SPI write protect and EISS) is unrelated -- To view, visit https://review.coreboot.org/c/coreboot/+/49649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice704a6502f4490906b6473345d52ded5202007e Gerrit-Change-Number: 49649 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: src/mediatek/mt8192: use Mediatek mt8192 vendor code(CB:50294)
by Xi Chen (Code Review) 01 Mar '21

01 Mar '21

Xi Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51125 ) Change subject: src/mediatek/mt8192: use Mediatek mt8192 vendor code(CB:50294) ...................................................................... src/mediatek/mt8192: use Mediatek mt8192 vendor code(CB:50294) Mediatek maintains the DRAM initialization code, the coding style is different from coreboot, when CB:50294 is ready, soc/mediatek/mt8192 will not be used. Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: I2b2f41d774c6b85f106867144fb0b29a4a1bdfcf --- M src/soc/mediatek/mt8192/Kconfig M src/soc/mediatek/mt8192/Makefile.inc D src/soc/mediatek/mt8192/dpm.c D src/soc/mediatek/mt8192/dramc_ana_init_config.c D src/soc/mediatek/mt8192/dramc_dig_config.c D src/soc/mediatek/mt8192/dramc_dvfs.c D src/soc/mediatek/mt8192/dramc_param.c D src/soc/mediatek/mt8192/dramc_pi_basic_api.c D src/soc/mediatek/mt8192/dramc_pi_calibration_api.c D src/soc/mediatek/mt8192/dramc_pi_main.c D src/soc/mediatek/mt8192/dramc_power.c D src/soc/mediatek/mt8192/dramc_subsys_config.c D src/soc/mediatek/mt8192/dramc_tracking.c D src/soc/mediatek/mt8192/dramc_utility.c D src/soc/mediatek/mt8192/emi.c D src/soc/mediatek/mt8192/include/soc/dpm.h D src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h D src/soc/mediatek/mt8192/include/soc/dramc_common_mt8192.h D src/soc/mediatek/mt8192/include/soc/dramc_param.h D src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h D src/soc/mediatek/mt8192/include/soc/dramc_power.h D src/soc/mediatek/mt8192/include/soc/dramc_register.h D src/soc/mediatek/mt8192/include/soc/dramc_register_bits_def.h D src/soc/mediatek/mt8192/include/soc/emi.h D src/soc/mediatek/mt8192/memory.c M src/vendorcode/Makefile.inc 26 files changed, 3 insertions(+), 20,062 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/51125/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/51125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b2f41d774c6b85f106867144fb0b29a4a1bdfcf Gerrit-Change-Number: 51125 Gerrit-PatchSet: 1 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendor: mediatek: Add mediatek mt8192 dram initialization codes
by Xi Chen (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Hung-Te Lin, Nico Huber, Martin Roth, Paul Menzel, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Menzel, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50294 to look at the new patch set (#6). Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization codes ...................................................................... vendor: mediatek: Add mediatek mt8192 dram initialization codes Add the DRAM initialization code based on Mediatek reference implementation. Mediatek internally maintains the DRAM initialization code, following different coding style. To prevent maintaining a different branch for coreboot (which may lead to typo or errors which switching between different coding style), we want to directly use the reference implementation as vendor code. Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 --- M src/vendorcode/Makefile.inc A src/vendorcode/mediatek/Kconfig A src/vendorcode/mediatek/Makefile.inc A src/vendorcode/mediatek/mt8192/Makefile.inc A src/vendorcode/mediatek/mt8192/dpm.c A src/vendorcode/mediatek/mt8192/dram_init.c A src/vendorcode/mediatek/mt8192/dramc/ANA_init_config.c A src/vendorcode/mediatek/mt8192/dramc/DIG_NONSHUF_config.c A src/vendorcode/mediatek/mt8192/dramc/DIG_SHUF_config.c A src/vendorcode/mediatek/mt8192/dramc/DRAMC_SUBSYS_config.c A src/vendorcode/mediatek/mt8192/dramc/DRAM_config_collctioin.c A src/vendorcode/mediatek/mt8192/dramc/Hal_io.c A src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c A src/vendorcode/mediatek/mt8192/dramc/Makefile.inc A src/vendorcode/mediatek/mt8192/dramc/dramc_actiming.c A src/vendorcode/mediatek/mt8192/dramc/dramc_dv_freq_related.c A src/vendorcode/mediatek/mt8192/dramc/dramc_dvfs.c A src/vendorcode/mediatek/mt8192/dramc/dramc_lowpower.c A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_calibration_api.c A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c A src/vendorcode/mediatek/mt8192/dramc/dramc_top.c A src/vendorcode/mediatek/mt8192/dramc/dramc_tracking.c A src/vendorcode/mediatek/mt8192/dramc/dramc_utility.c A src/vendorcode/mediatek/mt8192/dramc/emi.c A src/vendorcode/mediatek/mt8192/dramc/sv_c_data_traffic.c A src/vendorcode/mediatek/mt8192/dramc_param.c A src/vendorcode/mediatek/mt8192/driver/Makefile.inc A src/vendorcode/mediatek/mt8192/driver/pmic_wrap.c A src/vendorcode/mediatek/mt8192/driver/timer.c A src/vendorcode/mediatek/mt8192/driver/uart.c A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_AO.h A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_MD32.h A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_NAO.h A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_AO.h A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_NAO.h A src/vendorcode/mediatek/mt8192/include/addressmap.h A src/vendorcode/mediatek/mt8192/include/custom_emi.h A src/vendorcode/mediatek/mt8192/include/ddrphy_nao_reg.h A src/vendorcode/mediatek/mt8192/include/ddrphy_pll_reg.h A src/vendorcode/mediatek/mt8192/include/ddrphy_wo_pll_reg.h A src/vendorcode/mediatek/mt8192/include/dramc_actiming.h A src/vendorcode/mediatek/mt8192/include/dramc_ch0_nao_reg.h A src/vendorcode/mediatek/mt8192/include/dramc_ch0_reg.h A src/vendorcode/mediatek/mt8192/include/dramc_common.h A src/vendorcode/mediatek/mt8192/include/dramc_dv_init.h A src/vendorcode/mediatek/mt8192/include/dramc_int_global.h A src/vendorcode/mediatek/mt8192/include/dramc_int_slt.h A src/vendorcode/mediatek/mt8192/include/dramc_pi_api.h A src/vendorcode/mediatek/mt8192/include/dramc_reg_base_addr.h A src/vendorcode/mediatek/mt8192/include/dramc_register.h A src/vendorcode/mediatek/mt8192/include/dramc_top.h A src/vendorcode/mediatek/mt8192/include/dramc_typedefs.h A src/vendorcode/mediatek/mt8192/include/emi.h A src/vendorcode/mediatek/mt8192/include/emi_hw.h A src/vendorcode/mediatek/mt8192/include/emi_mpu_mt.h A src/vendorcode/mediatek/mt8192/include/emi_mpu_v1.h A src/vendorcode/mediatek/mt8192/include/memory.h A src/vendorcode/mediatek/mt8192/include/pmic_wrap_init.h A src/vendorcode/mediatek/mt8192/include/print.h A src/vendorcode/mediatek/mt8192/include/reg.h A src/vendorcode/mediatek/mt8192/include/soc/dpm.h A src/vendorcode/mediatek/mt8192/include/soc/dramc_common_mt8192.h A src/vendorcode/mediatek/mt8192/include/soc/dramc_param.h A src/vendorcode/mediatek/mt8192/include/soc/emi.h A src/vendorcode/mediatek/mt8192/include/stdint.h A src/vendorcode/mediatek/mt8192/include/sv_c_data_traffic.h A src/vendorcode/mediatek/mt8192/include/sys/types.h A src/vendorcode/mediatek/mt8192/include/uart.h A src/vendorcode/mediatek/mt8192/include/x_hal_io.h A src/vendorcode/mediatek/mt8192/lib/Makefile.inc A src/vendorcode/mediatek/mt8192/lib/print.c A src/vendorcode/mediatek/mt8192/memory.c 73 files changed, 87,960 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/50294/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/50294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 Gerrit-Change-Number: 50294 Gerrit-PatchSet: 6 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Cindy Ching <cindy.ching(a)mediatek.corp-partner.google.com> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Add mediatek mt8192 dram vendor code
by Xi Chen (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Hung-Te Lin, Nico Huber, Martin Roth, Paul Menzel, Yu-Ping Wu. Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50294 ) Change subject: Add mediatek mt8192 dram vendor code ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50294/comment/c49079f0_eebf29e0 PS5, Line 11: > That the code is developed/maintained somewhere else is a perfect argument […] @paul: sorry for confusion, the goal is to "use reference memory initialization code from MTK official firmware", the coding style is different from coreboot, which may lead to bug fix difficulty when applying official patches. Also, will split to two patches. -- To view, visit https://review.coreboot.org/c/coreboot/+/50294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 Gerrit-Change-Number: 50294 Gerrit-PatchSet: 5 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Cindy Ching <cindy.ching(a)mediatek.corp-partner.google.com> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 01 Mar 2021 01:45:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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coreboot-gerrit March 2021