coreboot-gerrit March 2021

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Change in coreboot[master]: sb/intel/lynxpoint/me_9.x.c: Rename to me.c
by Patrick Georgi (Code Review) 01 Mar '21

01 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51034 ) Change subject: sb/intel/lynxpoint/me_9.x.c: Rename to me.c ...................................................................... sb/intel/lynxpoint/me_9.x.c: Rename to me.c This code will eventually support both ME 9.x and ME 10. Change-Id: Idc02ab668a0b0d51c31f33f1266d983e64fb5505 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51034 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/southbridge/intel/lynxpoint/Makefile.inc R src/southbridge/intel/lynxpoint/me.c 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index d0b342b..a8de2fb 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -13,7 +13,7 @@ ramstage-y += sata.c ramstage-y += usb_ehci.c ramstage-y += usb_xhci.c -ramstage-y += me_9.x.c +ramstage-y += me.c ramstage-y += smbus.c ramstage-y += hda_verb.c ramstage-$(CONFIG_INTEL_LYNXPOINT_LP) += serialio.c @@ -30,7 +30,7 @@ ramstage-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c -smm-y += smihandler.c me_9.x.c pch.c +smm-y += smihandler.c me.c pch.c smm-y += pmutil.c usb_ehci.c usb_xhci.c bootblock-y += early_pch.c diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me.c similarity index 100% rename from src/southbridge/intel/lynxpoint/me_9.x.c rename to src/southbridge/intel/lynxpoint/me.c -- To view, visit https://review.coreboot.org/c/coreboot/+/51034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc02ab668a0b0d51c31f33f1266d983e64fb5505 Gerrit-Change-Number: 51034 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/sandybridge: Ensure tXP and tXPDLL do not overflow
by Patrick Georgi (Code Review) 01 Mar '21

01 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49889 ) Change subject: nb/intel/sandybridge: Ensure tXP and tXPDLL do not overflow ...................................................................... nb/intel/sandybridge: Ensure tXP and tXPDLL do not overflow The tXP bitfield is 3 bits wide, and the tXPDLL bitfield is 5 bits wide. Clamp any values that would overflow this field. Bits in TC_DTP already get set when the tXP and/or tXPDLL values are large. Change-Id: Ie7f3e8e01ff7edd2652562080554c0afadde0bb9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49889 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 4 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 6f02998..d6a8aa5 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -170,15 +170,16 @@ /* Other parameters */ const union tc_othp_reg tc_othp = { - .tXPDLL = ctrl->tXPDLL, - .tXP = ctrl->tXP, + .tXPDLL = MIN(ctrl->tXPDLL, 31), + .tXP = MIN(ctrl->tXP, 7), .tAONPD = ctrl->tAONPD, .tCPDED = 2, .tPRPDEN = 1, }; /* - * If tXP and tXPDLL are very high, we need to increase them by one. + * If tXP and tXPDLL are very high, they no longer fit in the bitfields + * of the TC_OTHP register. If so, we set bits in TC_DTP to compensate. * This can only happen on Ivy Bridge, and when overclocking the RAM. */ const union tc_dtp_reg tc_dtp = { -- To view, visit https://review.coreboot.org/c/coreboot/+/49889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7f3e8e01ff7edd2652562080554c0afadde0bb9 Gerrit-Change-Number: 49889 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/broadwell: Use ctdp.asl from Haswell
by Patrick Georgi (Code Review) 01 Mar '21

01 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49947 ) Change subject: soc/intel/broadwell: Use ctdp.asl from Haswell ...................................................................... soc/intel/broadwell: Use ctdp.asl from Haswell Both files are equivalent. Drop Broadwell's ctdp.asl and use Haswell's. Change-Id: Ida17d030d6022af18078321ee76b425095fe9f5c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49947 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- D src/soc/intel/broadwell/acpi/ctdp.asl M src/soc/intel/broadwell/acpi/hostbridge.asl 2 files changed, 1 insertion(+), 219 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/soc/intel/broadwell/acpi/ctdp.asl b/src/soc/intel/broadwell/acpi/ctdp.asl deleted file mode 100644 index 67ceb82..0000000 --- a/src/soc/intel/broadwell/acpi/ctdp.asl +++ /dev/null @@ -1,218 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB.PCI0.MCHC) -{ - Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ - Name (CTCC, 0) /* CTDP Current Selection */ - Name (CTCN, 0) /* CTDP Nominal Select */ - Name (CTCD, 1) /* CTDP Down Select */ - Name (CTCU, 2) /* CTDP Up Select */ - Name (SPL1, 0) /* Saved PL1 value */ - - OperationRegion (MCHB, SystemMemory, CONFIG_FIXED_MCHBAR_MMIO_BASE + 0x5000, 0x1000) - Field (MCHB, DWordAcc, Lock, Preserve) - { - Offset (0x930), /* PACKAGE_POWER_SKU */ - CTDN, 15, /* CTDP Nominal PL1 */ - Offset (0x938), /* PACKAGE_POWER_SKU_UNIT */ - PUNI, 4, /* Power Units */ - , 4, - EUNI, 5, /* Energy Units */ - , 3, - TUNI, 4, /* Time Units */ - Offset (0x958), /* PLATFORM_INFO */ - , 40, - LFM_, 8, /* Maximum Efficiency Ratio (LFM) */ - Offset (0x9a0), /* TURBO_POWER_LIMIT1 */ - PL1V, 15, /* Power Limit 1 Value */ - PL1E, 1, /* Power Limit 1 Enable */ - PL1C, 1, /* Power Limit 1 Clamp */ - PL1T, 7, /* Power Limit 1 Time */ - Offset (0x9a4), /* TURBO_POWER_LIMIT2 */ - PL2V, 15, /* Power Limit 2 Value */ - PL2E, 1, /* Power Limit 2 Enable */ - PL2C, 1, /* Power Limit 2 Clamp */ - PL2T, 7, /* Power Limit 2 Time */ - Offset (0xf3c), /* CONFIG_TDP_NOMINAL */ - TARN, 8, /* CTDP Nominal Turbo Activation Ratio */ - Offset (0xf40), /* CONFIG_TDP_LEVEL1 */ - CTDD, 15, /* CTDP Down PL1 */ - , 1, - TARD, 8, /* CTDP Down Turbo Activation Ratio */ - Offset (0xf48), /* MSR_CONFIG_TDP_LEVEL2 */ - CTDU, 15, /* CTDP Up PL1 */ - , 1, - TARU, 8, /* CTDP Up Turbo Activation Ratio */ - Offset (0xf50), /* CONFIG_TDP_CONTROL */ - CTCS, 2, /* CTDP Select */ - Offset (0xf54), /* TURBO_ACTIVATION_RATIO */ - TARS, 8, /* Turbo Activation Ratio Select */ - } - - /* - * Search CPU0 _PSS looking for control = arg0 and then - * return previous P-state entry number for new _PPC - * - * Format of _PSS: - * Name (_PSS, Package () { - * Package (6) { freq, power, tlat, blat, control, status } - * } - */ - External (\_SB.CP00._PSS) - Method (PSSS, 1, NotSerialized) - { - Local0 = 1 /* Start at P1 */ - Local1 = SizeOf (\_SB.CP00._PSS) - - While (Local0 < Local1) { - /* Store _PSS entry Control value to Local2 */ - Local2 = DeRefOf (Index (DeRefOf (Index (\_SB.CP00._PSS, Local0)), 4)) >> 8 - If (Local2 == Arg0) { - Return (Local0 - 1) - } - Local0++ - } - - Return (0) - } - - /* Calculate PL2 based on chip type */ - Method (CPL2, 1, NotSerialized) - { - /* Haswell ULT PL2 = 25W */ - /* FIXME: update for broadwell */ - Return (25 * 8) - } - - /* Set Config TDP Down */ - Method (STND, 0, Serialized) - { - If (Acquire (CTCM, 100)) { - Return (0) - } - If (CTCD == CTCC) { - Release (CTCM) - Return (0) - } - - Debug = "Set TDP Down" - - /* Set CTC */ - CTCS = CTCD - - /* Set TAR */ - TARS = TARD - - /* Set PPC limit and notify OS */ - PPCM = PSSS (TARD) - PPCN () - - /* Set PL2 */ - PL2V = CPL2 (CTDD) - - /* Set PL1 */ - PL1V = CTDD - - /* Store the new TDP Down setting */ - CTCC = CTCD - - Release (CTCM) - Return (1) - } - - /* Set Config TDP Nominal from Down */ - Method (STDN, 0, Serialized) - { - If (Acquire (CTCM, 100)) { - Return (0) - } - If (CTCN == CTCC) { - Release (CTCM) - Return (0) - } - - Debug = "Set TDP Nominal" - - /* Set PL1 */ - PL1V = CTDN - - /* Set PL2 */ - PL2V = CPL2 (CTDN) - - /* Set PPC limit and notify OS */ - PPCM = PSSS (TARN) - PPCN () - - /* Set TAR */ - TARS = TARN - - /* Set CTC */ - CTCS = CTCN - - /* Store the new TDP Nominal setting */ - CTCC = CTCN - - Release (CTCM) - Return (1) - } - - /* Calculate PL1 value based on requested TDP */ - Method (TDPP, 1, NotSerialized) - { - Return (((PUNI - 1) << 2) * Arg0) - } - - /* Enable Controllable TDP to limit PL1 to requested value */ - Method (CTLE, 1, Serialized) - { - If (Acquire (CTCM, 100)) { - Return (0) - } - - Debug = "Enable PL1 Limit" - - /* Set _PPC to LFM */ - Local0 = PSSS (LFM_) - PPCM = Local0 + 1 - \PPCN () - - /* Set TAR to LFM-1 */ - TARS = LFM_ - 1 - - /* Set PL1 to desired value */ - SPL1 = PL1V - PL1V = TDPP (Arg0) - - /* Set PL1 CLAMP bit */ - PL1C = 1 - - Release (CTCM) - Return (1) - } - - /* Disable Controllable TDP */ - Method (CTLD, 0, Serialized) - { - If (Acquire (CTCM, 100)) { - Return (0) - } - - Debug = "Disable PL1 Limit" - - /* Clear PL1 CLAMP bit */ - PL1C = 0 - - /* Set PL1 to normal value */ - PL1V = SPL1 - - /* Set TAR to 0 */ - TARS = 0 - - /* Set _PPC to 0 */ - PPCM = 0 - \PPCN () - - Release (CTCM) - Return (1) - } -} diff --git a/src/soc/intel/broadwell/acpi/hostbridge.asl b/src/soc/intel/broadwell/acpi/hostbridge.asl index 3ba5046..c0a3c7d 100644 --- a/src/soc/intel/broadwell/acpi/hostbridge.asl +++ b/src/soc/intel/broadwell/acpi/hostbridge.asl @@ -194,7 +194,7 @@ #include "pci_irqs.asl" /* Configurable TDP */ -#include "ctdp.asl" +#include <northbridge/intel/haswell/acpi/ctdp.asl> /* Integrated graphics 0:2.0 */ #include <drivers/intel/gma/acpi/gfx.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/49947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida17d030d6022af18078321ee76b425095fe9f5c Gerrit-Change-Number: 49947 Gerrit-PatchSet: 8 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/: Drop print of MAINBOARD_PART_NUMBER
by Patrick Georgi (Code Review) 01 Mar '21

01 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50718 ) Change subject: mb/: Drop print of MAINBOARD_PART_NUMBER ...................................................................... mb/: Drop print of MAINBOARD_PART_NUMBER Change-Id: Ie3870bc666acaea316f00b205de512cf790e720c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50718 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/mainboard/amd/bilby/mainboard.c M src/mainboard/amd/gardenia/mainboard.c M src/mainboard/amd/inagua/mainboard.c M src/mainboard/amd/majolica/mainboard.c M src/mainboard/amd/mandolin/mainboard.c M src/mainboard/amd/olivehill/mainboard.c M src/mainboard/amd/padmelon/mainboard.c M src/mainboard/amd/parmer/mainboard.c M src/mainboard/amd/persimmon/mainboard.c M src/mainboard/amd/south_station/mainboard.c M src/mainboard/amd/thatcher/mainboard.c M src/mainboard/amd/union_station/mainboard.c M src/mainboard/asrock/e350m1/mainboard.c M src/mainboard/asrock/imb-a180/mainboard.c M src/mainboard/asus/a88xm-e/mainboard.c M src/mainboard/asus/am1i-a/mainboard.c M src/mainboard/asus/f2a85-m/mainboard.c M src/mainboard/bap/ode_e20XX/mainboard.c M src/mainboard/biostar/a68n_5200/mainboard.c M src/mainboard/biostar/am1ml/mainboard.c M src/mainboard/elmex/pcm205400/mainboard.c M src/mainboard/gizmosphere/gizmo/mainboard.c M src/mainboard/gizmosphere/gizmo2/mainboard.c M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/zork/mainboard.c M src/mainboard/hp/abm/mainboard.c M src/mainboard/hp/pavilion_m6_1035dx/mainboard.c M src/mainboard/jetway/nf81-t56n-lf/mainboard.c M src/mainboard/lenovo/g505s/mainboard.c M src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c M src/mainboard/lippert/frontrunner-af/variants/toucan-af/mainboard.c M src/mainboard/msi/ms7721/mainboard.c M src/mainboard/pcengines/apu1/mainboard.c M src/mainboard/pcengines/apu2/mainboard.c D src/mainboard/portwell/m107/mainboard.c 35 files changed, 3 insertions(+), 78 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/mainboard/amd/bilby/mainboard.c b/src/mainboard/amd/bilby/mainboard.c index 7e3c17b..12f801d 100644 --- a/src/mainboard/amd/bilby/mainboard.c +++ b/src/mainboard/amd/bilby/mainboard.c @@ -97,8 +97,6 @@ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - init_tables(); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c index e153f71..e53213ba 100644 --- a/src/mainboard/amd/gardenia/mainboard.c +++ b/src/mainboard/amd/gardenia/mainboard.c @@ -77,9 +77,6 @@ *************************************************/ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " - CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index 48afb3f..1bf74a6 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -36,8 +36,6 @@ **********************************************/ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - /* Inagua mainboard specific setting */ init_gpios(); diff --git a/src/mainboard/amd/majolica/mainboard.c b/src/mainboard/amd/majolica/mainboard.c index 22ec33a..b381840 100644 --- a/src/mainboard/amd/majolica/mainboard.c +++ b/src/mainboard/amd/majolica/mainboard.c @@ -91,8 +91,6 @@ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - init_tables(); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); diff --git a/src/mainboard/amd/mandolin/mainboard.c b/src/mainboard/amd/mandolin/mainboard.c index 915f22e..a66db78 100644 --- a/src/mainboard/amd/mandolin/mainboard.c +++ b/src/mainboard/amd/mandolin/mainboard.c @@ -97,8 +97,6 @@ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - init_tables(); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); diff --git a/src/mainboard/amd/olivehill/mainboard.c b/src/mainboard/amd/olivehill/mainboard.c index 60caf82..221e52a 100644 --- a/src/mainboard/amd/olivehill/mainboard.c +++ b/src/mainboard/amd/olivehill/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <device/device.h> /********************************************** @@ -8,7 +7,6 @@ **********************************************/ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/padmelon/mainboard.c b/src/mainboard/amd/padmelon/mainboard.c index fc5279b..f7d351d 100644 --- a/src/mainboard/amd/padmelon/mainboard.c +++ b/src/mainboard/amd/padmelon/mainboard.c @@ -106,9 +106,6 @@ *************************************************/ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " - CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c index bf00401ec..285b1b9 100644 --- a/src/mainboard/amd/parmer/mainboard.c +++ b/src/mainboard/amd/parmer/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <device/device.h> /************************************************* @@ -8,7 +7,6 @@ *************************************************/ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 9e5e81f..11d2af1 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -108,8 +108,6 @@ **********************************************/ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - /* enable GPP CLK0 thru CLK1 */ /* disable GPP CLK2 thru SLT_GFX_CLK */ misc_write8(0, 0xff); diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index df47222..b25a4b5 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -31,7 +31,6 @@ **********************************************/ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); southstation_led_init(); /* diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c index 7348840..d71f2d5 100644 --- a/src/mainboard/amd/thatcher/mainboard.c +++ b/src/mainboard/amd/thatcher/mainboard.c @@ -12,8 +12,6 @@ { msr_t msr; - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - msr = rdmsr(LS_CFG_MSR); msr.lo &= ~(1 << 28); wrmsr(LS_CFG_MSR, msr); diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index 4b6f9a1..43dde04 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -10,8 +10,6 @@ **********************************************/ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - /* * Initialize ASF registers to an arbitrary address because someone * long ago set things up this way inside the SPD read code. The diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index 231b396..ec6fcc5 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -11,8 +11,6 @@ **********************************************/ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - /* Power off unused clock pins of GPP PCIe devices * GPP CLK0 connected to unpopulated mini PCIe slot * GPP CLK1 connected to ethernet chip diff --git a/src/mainboard/asrock/imb-a180/mainboard.c b/src/mainboard/asrock/imb-a180/mainboard.c index 60caf82..9d5ec2f 100644 --- a/src/mainboard/asrock/imb-a180/mainboard.c +++ b/src/mainboard/asrock/imb-a180/mainboard.c @@ -8,7 +8,6 @@ **********************************************/ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/asus/a88xm-e/mainboard.c b/src/mainboard/asus/a88xm-e/mainboard.c index 2e08188..26bbd0e 100644 --- a/src/mainboard/asus/a88xm-e/mainboard.c +++ b/src/mainboard/asus/a88xm-e/mainboard.c @@ -35,7 +35,6 @@ { msr_t msr; - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); pirq_setup(); msr = rdmsr(LS_CFG_MSR); diff --git a/src/mainboard/asus/am1i-a/mainboard.c b/src/mainboard/asus/am1i-a/mainboard.c index d5ecdd6..e105910 100644 --- a/src/mainboard/asus/am1i-a/mainboard.c +++ b/src/mainboard/asus/am1i-a/mainboard.c @@ -78,8 +78,6 @@ **********************************************/ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/asus/f2a85-m/mainboard.c b/src/mainboard/asus/f2a85-m/mainboard.c index c09b69c..30e99f1 100644 --- a/src/mainboard/asus/f2a85-m/mainboard.c +++ b/src/mainboard/asus/f2a85-m/mainboard.c @@ -12,8 +12,6 @@ { msr_t msr; - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - msr = rdmsr(LS_CFG_MSR); msr.lo &= ~(1 << 28); wrmsr(LS_CFG_MSR, msr); diff --git a/src/mainboard/bap/ode_e20XX/mainboard.c b/src/mainboard/bap/ode_e20XX/mainboard.c index 3515fce..9baf0ea 100644 --- a/src/mainboard/bap/ode_e20XX/mainboard.c +++ b/src/mainboard/bap/ode_e20XX/mainboard.c @@ -93,8 +93,6 @@ **********************************************/ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/biostar/a68n_5200/mainboard.c b/src/mainboard/biostar/a68n_5200/mainboard.c index 60caf82..9d5ec2f 100644 --- a/src/mainboard/biostar/a68n_5200/mainboard.c +++ b/src/mainboard/biostar/a68n_5200/mainboard.c @@ -8,7 +8,6 @@ **********************************************/ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/biostar/am1ml/mainboard.c b/src/mainboard/biostar/am1ml/mainboard.c index e99623e..a7ef85b 100644 --- a/src/mainboard/biostar/am1ml/mainboard.c +++ b/src/mainboard/biostar/am1ml/mainboard.c @@ -82,8 +82,6 @@ **********************************************/ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/elmex/pcm205400/mainboard.c b/src/mainboard/elmex/pcm205400/mainboard.c index 9e5e81f..11d2af1 100644 --- a/src/mainboard/elmex/pcm205400/mainboard.c +++ b/src/mainboard/elmex/pcm205400/mainboard.c @@ -108,8 +108,6 @@ **********************************************/ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - /* enable GPP CLK0 thru CLK1 */ /* disable GPP CLK2 thru SLT_GFX_CLK */ misc_write8(0, 0xff); diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c index f24c9e9..594d735 100644 --- a/src/mainboard/gizmosphere/gizmo/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo/mainboard.c @@ -12,8 +12,6 @@ **********************************************/ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - /* enable GPP CLK0 thru CLK1 */ /* disable GPP CLK2 thru SLT_GFX_CLK */ misc_write8(0, 0xFF); diff --git a/src/mainboard/gizmosphere/gizmo2/mainboard.c b/src/mainboard/gizmosphere/gizmo2/mainboard.c index 2da1dea..a722980 100644 --- a/src/mainboard/gizmosphere/gizmo2/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo2/mainboard.c @@ -92,7 +92,6 @@ **********************************************/ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index b69af78..a4dd0f4 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -150,9 +150,6 @@ *************************************************/ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " - CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index 31d87c0..6b51d52 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -199,8 +199,6 @@ *************************************************/ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - init_tables(); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); diff --git a/src/mainboard/hp/abm/mainboard.c b/src/mainboard/hp/abm/mainboard.c index 88de23a..4c271c5 100644 --- a/src/mainboard/hp/abm/mainboard.c +++ b/src/mainboard/hp/abm/mainboard.c @@ -80,8 +80,6 @@ **********************************************/ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c index 7c1f557..620e329 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c @@ -19,8 +19,6 @@ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH); global_smi_enable(); diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index a8ed85d..25263ea 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -109,8 +109,6 @@ **********************************************/ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - /* enable GPP CLK0 thru CLK3 (interleaved) */ /* disable GPP CLK4 thru SLT_GFX_CLK */ misc_write8(0, 0xff); diff --git a/src/mainboard/lenovo/g505s/mainboard.c b/src/mainboard/lenovo/g505s/mainboard.c index d900c94..bea6102 100644 --- a/src/mainboard/lenovo/g505s/mainboard.c +++ b/src/mainboard/lenovo/g505s/mainboard.c @@ -19,7 +19,6 @@ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH); global_smi_enable(); diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c index e32e125..f87d21d 100644 --- a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c @@ -48,7 +48,6 @@ { volatile u8 *spi_base; /* base addr of Hudson's SPI host controller */ int i; - printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " ENTER %s\n", __func__); /* Init Hudson GPIOs. */ printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE); @@ -108,7 +107,6 @@ */ sema_send_alive(); - printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " EXIT %s\n", __func__); } /********************************************** @@ -116,7 +114,6 @@ **********************************************/ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); dev->ops->init = init; /* enable GPP CLK0 */ diff --git a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/mainboard.c index 901ee02..3a4db85 100644 --- a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/mainboard.c @@ -14,7 +14,6 @@ static void init(struct device *dev) { volatile u8 *spi_base; /* base addr of Hudson's SPI host controller */ - printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " ENTER %s\n", __func__); /* Init Hudson GPIOs. */ printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE); @@ -78,7 +77,6 @@ */ sema_send_alive(); - printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " EXIT %s\n", __func__); } /********************************************** @@ -86,7 +84,6 @@ **********************************************/ static void mainboard_enable(struct device *dev) { - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); dev->ops->init = init; /* enable GPP CLK0 thru CLK1 */ diff --git a/src/mainboard/msi/ms7721/mainboard.c b/src/mainboard/msi/ms7721/mainboard.c index c09b69c..30e99f1 100644 --- a/src/mainboard/msi/ms7721/mainboard.c +++ b/src/mainboard/msi/ms7721/mainboard.c @@ -12,8 +12,6 @@ { msr_t msr; - printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - msr = rdmsr(LS_CFG_MSR); msr.lo &= ~(1 << 28); wrmsr(LS_CFG_MSR, msr); diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index fa9b093..cb5d4fb 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -254,6 +254,7 @@ static void mainboard_enable(struct device *dev) { + /* Maintain this text unchanged for manufacture process. */ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); config_gpio_mux(); @@ -363,6 +364,7 @@ static void mainboard_final(void *chip_info) { + /* Maintain this text unchanged for manufacture process. */ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Final.\n"); /* diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 062d223..56976e5 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -240,6 +240,7 @@ static void mainboard_enable(struct device *dev) { + /* Maintain this text unchanged for manufacture process. */ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); config_gpio_mux(); diff --git a/src/mainboard/portwell/m107/mainboard.c b/src/mainboard/portwell/m107/mainboard.c deleted file mode 100644 index c3412b4..0000000 --- a/src/mainboard/portwell/m107/mainboard.c +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> - -/* - * mainboard_enable is executed as first thing after - * enumerate_buses(). - */ -static void mainboard_enable(struct device *dev) -{ -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/50718 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3870bc666acaea316f00b205de512cf790e720c Gerrit-Change-Number: 50718 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/ocp/deltalake: Fill ECC type in romstage
by Patrick Georgi (Code Review) 01 Mar '21

01 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50179 ) Change subject: mb/ocp/deltalake: Fill ECC type in romstage ...................................................................... mb/ocp/deltalake: Fill ECC type in romstage Fill the ECC type in `struct memory_info` in romstage, and in SoC code. The SMBIOS override is unnecessary, and this is not mainboard-specific. Change-Id: I8370b3ee7d75914b895946b53923598adf87b522 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50179 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Johnny Lin <Johnny_Lin(a)wiwynn.com> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-by: Jonathan Zhang <jonzhang(a)fb.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/smbios.c M src/include/smbios.h M src/mainboard/ocp/deltalake/ramstage.c M src/soc/intel/xeon_sp/cpx/romstage.c 4 files changed, 21 insertions(+), 32 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, but someone else must approve Jonathan Zhang: Looks good to me, approved Johnny Lin: Looks good to me, but someone else must approve diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index bd7f422..33ab1ba 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -443,11 +443,6 @@ return 0x02; /* Unknown */ } -unsigned int __weak smbios_memory_error_correction_type(struct memory_info *meminfo) -{ - return meminfo->ecc_type; -} - unsigned int __weak smbios_processor_external_clock(void) { return 0; /* Unknown */ @@ -1023,7 +1018,7 @@ t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD; t->use = MEMORY_ARRAY_USE_SYSTEM; - t->memory_error_correction = smbios_memory_error_correction_type(meminfo); + t->memory_error_correction = meminfo->ecc_type; /* no error information handle available */ t->memory_error_information_handle = 0xFFFE; diff --git a/src/include/smbios.h b/src/include/smbios.h index 91f031a..78f364e 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -61,7 +61,6 @@ void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision); -unsigned int smbios_memory_error_correction_type(struct memory_info *meminfo); unsigned int smbios_processor_external_clock(void); unsigned int smbios_processor_characteristics(void); struct cpuid_result; diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index dc70eb2..7c79949 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -23,31 +23,6 @@ extern struct fru_info_str fru_strings; static char slot_id_str[SLOT_ID_LEN]; -/* Override SMBIOS type 16 error correction type. */ -unsigned int smbios_memory_error_correction_type(struct memory_info *meminfo) -{ - const struct SystemMemoryMapHob *hob; - - hob = get_system_memory_map(); - assert(hob != NULL); - - switch (hob->RasModesEnabled) { - case CH_INDEPENDENT: - return MEMORY_ARRAY_ECC_SINGLE_BIT; - case FULL_MIRROR_1LM: - case PARTIAL_MIRROR_1LM: - case FULL_MIRROR_2LM: - case PARTIAL_MIRROR_2LM: - return MEMORY_ARRAY_ECC_MULTI_BIT; - case RK_SPARE: - return MEMORY_ARRAY_ECC_SINGLE_BIT; - case CH_LOCKSTEP: - return MEMORY_ARRAY_ECC_SINGLE_BIT; - default: - return MEMORY_ARRAY_ECC_MULTI_BIT; - } -} - /* * Update SMBIOS type 0 ec version. * In deltalake, BMC version is used to represent ec version. diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 6025f2a..c1cb0ca 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -37,6 +37,25 @@ return *memmap_addr; } +static uint8_t get_error_correction_type(const uint8_t RasModesEnabled) +{ + switch (RasModesEnabled) { + case CH_INDEPENDENT: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + case FULL_MIRROR_1LM: + case PARTIAL_MIRROR_1LM: + case FULL_MIRROR_2LM: + case PARTIAL_MIRROR_2LM: + return MEMORY_ARRAY_ECC_MULTI_BIT; + case RK_SPARE: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + case CH_LOCKSTEP: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + default: + return MEMORY_ARRAY_ECC_MULTI_BIT; + } +} + /* Save the DIMM information for SMBIOS table 17 */ void save_dimm_info(void) { @@ -63,6 +82,7 @@ /* According to Dear Customer Letter it's 1.12 TB per processor. */ mem_info->max_capacity_mib = 1.12 * MiB * CONFIG_MAX_SOCKET; mem_info->number_of_devices = CONFIG_DIMM_MAX; + mem_info->ecc_type = get_error_correction_type(hob->RasModesEnabled); dimm_max = ARRAY_SIZE(mem_info->dimm); vdd_voltage = get_ddr_voltage(hob->DdrVoltage); /* For now only implement for one socket and hard-coded for DDR4 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8370b3ee7d75914b895946b53923598adf87b522 Gerrit-Change-Number: 50179 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: memory_info.h: Store SMBIOS error correction type
by Patrick Georgi (Code Review) 01 Mar '21

01 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50178 ) Change subject: memory_info.h: Store SMBIOS error correction type ...................................................................... memory_info.h: Store SMBIOS error correction type There are platforms that support error correction types other than single-bit ECC. Extend meminfo to accomodate additional ECC types. It is assumed that `struct memory_info` is packed to save space. Thus, use `uint8_t` instead of an enum type (which are usually 4 bytes wide). Change-Id: I863f8e34c84841d931dfb8d7067af0f12a437e36 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50178 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/smbios.c M src/include/memory_info.h M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/sandybridge/raminit.c M src/soc/intel/common/block/systemagent/systemagent.c 5 files changed, 15 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, but someone else must approve diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 4c20d52..bd7f422 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -445,8 +445,7 @@ unsigned int __weak smbios_memory_error_correction_type(struct memory_info *meminfo) { - return meminfo->ecc_capable ? - MEMORY_ARRAY_ECC_SINGLE_BIT : MEMORY_ARRAY_ECC_NONE; + return meminfo->ecc_type; } unsigned int __weak smbios_processor_external_clock(void) diff --git a/src/include/memory_info.h b/src/include/memory_info.h index 1ba7329..fed5bbe 100644 --- a/src/include/memory_info.h +++ b/src/include/memory_info.h @@ -96,8 +96,11 @@ } __packed; struct memory_info { - /* controller specific */ - bool ecc_capable; + /* + * SMBIOS error correction type. + * See the smbios.h smbios_memory_array_ecc enum. + */ + uint8_t ecc_type; /* Maximum capacity the DRAM controller/mainboard supports */ uint32_t max_capacity_mib; /* Maximum number of DIMMs the DRAM controller/mainboard supports */ diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 96e6a2a..58ac8a0 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -167,9 +167,9 @@ report_memory_config(); } -static bool nb_supports_ecc(const uint32_t capid0_a) +static uint8_t nb_get_ecc_type(const uint32_t capid0_a) { - return !(capid0_a & CAPID_ECCDIS); + return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT; } static uint16_t nb_slots_per_channel(const uint32_t capid0_a) @@ -256,7 +256,7 @@ const uint16_t channels = nb_number_of_channels(capid0_a); - mem_info->ecc_capable = nb_supports_ecc(capid0_a); + mem_info->ecc_type = nb_get_ecc_type(capid0_a); mem_info->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a); mem_info->number_of_devices = channels * nb_slots_per_channel(capid0_a); } diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 0dcd952..47cd7de 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -53,9 +53,9 @@ memset(&ctrl->info.dimm[channel][0], 0, sizeof(ctrl->info.dimm[0])); } -static bool nb_supports_ecc(const uint32_t capid0_a) +static uint8_t nb_get_ecc_type(const uint32_t capid0_a) { - return !(capid0_a & CAPID_ECCDIS); + return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT; } static uint16_t nb_slots_per_channel(const uint32_t capid0_a) @@ -114,7 +114,7 @@ const uint16_t channels = nb_number_of_channels(capid0_a); - m->ecc_capable = nb_supports_ecc(capid0_a); + m->ecc_type = nb_get_ecc_type(capid0_a); m->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a); m->number_of_devices = channels * nb_slots_per_channel(capid0_a); } diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index ec26fce..7d42fe1 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -48,9 +48,9 @@ return 32768; /* 32 GiB per channel */ } -static bool sa_supports_ecc(const uint32_t capid0_a) +static uint8_t sa_get_ecc_type(const uint32_t capid0_a) { - return !(capid0_a & CAPID_ECCDIS); + return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT; } static size_t sa_slots_per_channel(const uint32_t capid0_a) @@ -73,7 +73,7 @@ const uint32_t capid0_a = pci_read_config32(dev, CAPID0_A); - m->ecc_capable = sa_supports_ecc(capid0_a); + m->ecc_type = sa_get_ecc_type(capid0_a); m->max_capacity_mib = soc_systemagent_max_chan_capacity_mib(CAPID_DDRSZ(capid0_a)) * sa_number_of_channels(capid0_a); m->number_of_devices = sa_slots_per_channel(capid0_a) * -- To view, visit https://review.coreboot.org/c/coreboot/+/50178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I863f8e34c84841d931dfb8d7067af0f12a437e36 Gerrit-Change-Number: 50178 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/acpimmio: Add fch_disable_legacy_dma_io
by Patrick Georgi (Code Review) 01 Mar '21

01 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51075 ) Change subject: soc/amd/common/block/acpimmio: Add fch_disable_legacy_dma_io ...................................................................... soc/amd/common/block/acpimmio: Add fch_disable_legacy_dma_io Add a method to disable decoding the legacy DMA IO ports. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I979445cfa8317334e62e9ebf12256ece9f8058bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/51075 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h 2 files changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index 3a86aaf..cfe8779 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -69,6 +69,12 @@ pm_write32(PM_DECODE_EN, pm_read32(PM_DECODE_EN) | LEGACY_IO_EN); } +void fch_disable_legacy_dma_io(void) +{ + pm_write32(PM_DECODE_EN, pm_read32(PM_DECODE_EN) & + ~(LEGACY_DMA_IO_EN | LEGACY_DMA_IO_80_EN)); +} + void fch_io_enable_legacy_io(void) { pm_io_write32(PM_DECODE_EN, pm_io_read32(PM_DECODE_EN) | LEGACY_IO_EN); diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index a9a6986..7891bfd 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -22,6 +22,8 @@ #define HPET_EN (1 << 6) /* decode HPET MMIO at 0xfed00000 */ #define FCH_IOAPIC_EN (1 << 5) #define SMBUS_ASF_IO_EN (1 << 4) +#define LEGACY_DMA_IO_80_EN (1 << 3) /* pass 0x80-0x83 to legacy DMA IO range */ +#define LEGACY_DMA_IO_EN (1 << 2) #define CF9_IO_EN (1 << 1) #define LEGACY_IO_EN (1 << 0) #define PM_RST_STATUS 0xc0 @@ -78,6 +80,7 @@ void enable_acpimmio_decode_pm04(void); void fch_enable_cf9_io(void); void fch_enable_legacy_io(void); +void fch_disable_legacy_dma_io(void); void fch_io_enable_legacy_io(void); void fch_enable_ioapic_decode(void); void fch_configure_hpet(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/51075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I979445cfa8317334e62e9ebf12256ece9f8058bf Gerrit-Change-Number: 51075 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/sasukette: Configure I2C times for touchpad/code...
by Patrick Georgi (Code Review) 01 Mar '21

01 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51112 ) Change subject: mb/google/dedede/var/sasukette: Configure I2C times for touchpad/codec/AMP ...................................................................... mb/google/dedede/var/sasukette: Configure I2C times for touchpad/codec/AMP Configure I2C high / low time in device tree to ensure I2C CLK runs accurately at I2C_SPEED_FAST (400 kHz). Measured I2C frequency just as below after tuning: touchpad:372 kHz audio codec RT5682:386.8 kHz speaker AMP L:387.5 kHz speaker AMP R:388.9 kHz BUG=b:181342340 BRANCH=dedede TEST=Build and check after tuning I2C clock is under 400kHz Signed-off-by: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Change-Id: I05d78c088190e349281a34b2aeed39ae8d867dc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51112 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/variants/sasukette/overridetree.cb 1 file changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb index 2b310ce..fe7a2dd 100644 --- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb @@ -21,6 +21,12 @@ }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 185, + .scl_hcnt = 95, + .sda_hold = 40, + } }, .i2c[1] = { .speed = I2C_SPEED_FAST, @@ -33,6 +39,12 @@ }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 185, + .scl_hcnt = 95, + .sda_hold = 40, + } }, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/51112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05d78c088190e349281a34b2aeed39ae8d867dc2 Gerrit-Change-Number: 51112 Gerrit-PatchSet: 3 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jessie Xu <xuyanan(a)huaqin.corp-partner.google.com> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-CC: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/storo: Enable ELAN touchscreen
by Patrick Georgi (Code Review) 01 Mar '21

01 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50981 ) Change subject: mb/google/dedede/var/storo: Enable ELAN touchscreen ...................................................................... mb/google/dedede/var/storo: Enable ELAN touchscreen Add ELAN touchscreen into devicetree for storo. BUG=b:177389448 BRANCH=dedede TEST=built storo firmware and verified touchscreen function Change-Id: I0d9e5005928c6fda3d1f0ce8bd9ae135e4a04867 Signed-off-by: Zanxi Chen <chenzanxi(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50981 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/variants/storo/overridetree.cb 1 file changed, 16 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Tao Xia: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb index a92dbdb..e4624e5 100644 --- a/src/mainboard/google/dedede/variants/storo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb @@ -47,5 +47,21 @@ device i2c 15 on end end end #I2C 0 + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9008"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "7" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end # I2C 2 end end -- To view, visit https://review.coreboot.org/c/coreboot/+/50981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d9e5005928c6fda3d1f0ce8bd9ae135e4a04867 Gerrit-Change-Number: 50981 Gerrit-PatchSet: 4 Gerrit-Owner: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: vendor: mediatek: Add mediatek mt8192 dram initialization codes
by Xi Chen (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Nico Huber, Martin Roth, Paul Menzel, Yu-Ping Wu. Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50294 ) Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization codes ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: ps8: remove trailing whitespace/tabs. -- To view, visit https://review.coreboot.org/c/coreboot/+/50294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 Gerrit-Change-Number: 50294 Gerrit-PatchSet: 8 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Cindy Ching <cindy.ching(a)mediatek.corp-partner.google.com> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 01 Mar 2021 08:06:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2021