Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50179 )
Change subject: mb/ocp/deltalake: Fill ECC type in romstage
......................................................................
mb/ocp/deltalake: Fill ECC type in romstage
Fill the ECC type in `struct memory_info` in romstage, and in SoC code.
The SMBIOS override is unnecessary, and this is not mainboard-specific.
Change-Id: I8370b3ee7d75914b895946b53923598adf87b522
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50179
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Johnny Lin <Johnny_Lin(a)wiwynn.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Reviewed-by: Jonathan Zhang <jonzhang(a)fb.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/arch/x86/smbios.c
M src/include/smbios.h
M src/mainboard/ocp/deltalake/ramstage.c
M src/soc/intel/xeon_sp/cpx/romstage.c
4 files changed, 21 insertions(+), 32 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Patrick Rudolph: Looks good to me, but someone else must approve
Jonathan Zhang: Looks good to me, approved
Johnny Lin: Looks good to me, but someone else must approve
diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
index bd7f422..33ab1ba 100644
--- a/src/arch/x86/smbios.c
+++ b/src/arch/x86/smbios.c
@@ -443,11 +443,6 @@
return 0x02; /* Unknown */
}
-unsigned int __weak smbios_memory_error_correction_type(struct memory_info *meminfo)
-{
- return meminfo->ecc_type;
-}
-
unsigned int __weak smbios_processor_external_clock(void)
{
return 0; /* Unknown */
@@ -1023,7 +1018,7 @@
t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD;
t->use = MEMORY_ARRAY_USE_SYSTEM;
- t->memory_error_correction = smbios_memory_error_correction_type(meminfo);
+ t->memory_error_correction = meminfo->ecc_type;
/* no error information handle available */
t->memory_error_information_handle = 0xFFFE;
diff --git a/src/include/smbios.h b/src/include/smbios.h
index 91f031a..78f364e 100644
--- a/src/include/smbios.h
+++ b/src/include/smbios.h
@@ -61,7 +61,6 @@
void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision);
-unsigned int smbios_memory_error_correction_type(struct memory_info *meminfo);
unsigned int smbios_processor_external_clock(void);
unsigned int smbios_processor_characteristics(void);
struct cpuid_result;
diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c
index dc70eb2..7c79949 100644
--- a/src/mainboard/ocp/deltalake/ramstage.c
+++ b/src/mainboard/ocp/deltalake/ramstage.c
@@ -23,31 +23,6 @@
extern struct fru_info_str fru_strings;
static char slot_id_str[SLOT_ID_LEN];
-/* Override SMBIOS type 16 error correction type. */
-unsigned int smbios_memory_error_correction_type(struct memory_info *meminfo)
-{
- const struct SystemMemoryMapHob *hob;
-
- hob = get_system_memory_map();
- assert(hob != NULL);
-
- switch (hob->RasModesEnabled) {
- case CH_INDEPENDENT:
- return MEMORY_ARRAY_ECC_SINGLE_BIT;
- case FULL_MIRROR_1LM:
- case PARTIAL_MIRROR_1LM:
- case FULL_MIRROR_2LM:
- case PARTIAL_MIRROR_2LM:
- return MEMORY_ARRAY_ECC_MULTI_BIT;
- case RK_SPARE:
- return MEMORY_ARRAY_ECC_SINGLE_BIT;
- case CH_LOCKSTEP:
- return MEMORY_ARRAY_ECC_SINGLE_BIT;
- default:
- return MEMORY_ARRAY_ECC_MULTI_BIT;
- }
-}
-
/*
* Update SMBIOS type 0 ec version.
* In deltalake, BMC version is used to represent ec version.
diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c
index 6025f2a..c1cb0ca 100644
--- a/src/soc/intel/xeon_sp/cpx/romstage.c
+++ b/src/soc/intel/xeon_sp/cpx/romstage.c
@@ -37,6 +37,25 @@
return *memmap_addr;
}
+static uint8_t get_error_correction_type(const uint8_t RasModesEnabled)
+{
+ switch (RasModesEnabled) {
+ case CH_INDEPENDENT:
+ return MEMORY_ARRAY_ECC_SINGLE_BIT;
+ case FULL_MIRROR_1LM:
+ case PARTIAL_MIRROR_1LM:
+ case FULL_MIRROR_2LM:
+ case PARTIAL_MIRROR_2LM:
+ return MEMORY_ARRAY_ECC_MULTI_BIT;
+ case RK_SPARE:
+ return MEMORY_ARRAY_ECC_SINGLE_BIT;
+ case CH_LOCKSTEP:
+ return MEMORY_ARRAY_ECC_SINGLE_BIT;
+ default:
+ return MEMORY_ARRAY_ECC_MULTI_BIT;
+ }
+}
+
/* Save the DIMM information for SMBIOS table 17 */
void save_dimm_info(void)
{
@@ -63,6 +82,7 @@
/* According to Dear Customer Letter it's 1.12 TB per processor. */
mem_info->max_capacity_mib = 1.12 * MiB * CONFIG_MAX_SOCKET;
mem_info->number_of_devices = CONFIG_DIMM_MAX;
+ mem_info->ecc_type = get_error_correction_type(hob->RasModesEnabled);
dimm_max = ARRAY_SIZE(mem_info->dimm);
vdd_voltage = get_ddr_voltage(hob->DdrVoltage);
/* For now only implement for one socket and hard-coded for DDR4 */
--
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Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50294 )
Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization codes
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
ps8: remove trailing whitespace/tabs.
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Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Menzel, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/50294
to look at the new patch set (#8).
Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization codes
......................................................................
vendor: mediatek: Add mediatek mt8192 dram initialization codes
Add the DRAM initialization code based on Mediatek reference implementation.
Mediatek internally maintains the DRAM initialization code, following
different coding style.
To prevent maintaining a different branch for coreboot
(which may lead to typo or errors which switching between different coding
style), we want to directly use the reference implementation as vendor code.
Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com>
Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4
---
M src/vendorcode/Makefile.inc
A src/vendorcode/mediatek/Kconfig
A src/vendorcode/mediatek/Makefile.inc
A src/vendorcode/mediatek/mt8192/Makefile.inc
A src/vendorcode/mediatek/mt8192/dpm.c
A src/vendorcode/mediatek/mt8192/dram_init.c
A src/vendorcode/mediatek/mt8192/dramc/ANA_init_config.c
A src/vendorcode/mediatek/mt8192/dramc/DIG_NONSHUF_config.c
A src/vendorcode/mediatek/mt8192/dramc/DIG_SHUF_config.c
A src/vendorcode/mediatek/mt8192/dramc/DRAMC_SUBSYS_config.c
A src/vendorcode/mediatek/mt8192/dramc/DRAM_config_collctioin.c
A src/vendorcode/mediatek/mt8192/dramc/Hal_io.c
A src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c
A src/vendorcode/mediatek/mt8192/dramc/Makefile.inc
A src/vendorcode/mediatek/mt8192/dramc/dramc_actiming.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_dv_freq_related.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_dvfs.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_lowpower.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_calibration_api.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_top.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_tracking.c
A src/vendorcode/mediatek/mt8192/dramc/dramc_utility.c
A src/vendorcode/mediatek/mt8192/dramc/emi.c
A src/vendorcode/mediatek/mt8192/dramc_param.c
A src/vendorcode/mediatek/mt8192/driver/Makefile.inc
A src/vendorcode/mediatek/mt8192/driver/pmic_wrap.c
A src/vendorcode/mediatek/mt8192/driver/timer.c
A src/vendorcode/mediatek/mt8192/driver/uart.c
A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_AO.h
A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_MD32.h
A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_NAO.h
A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_AO.h
A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_NAO.h
A src/vendorcode/mediatek/mt8192/include/addressmap.h
A src/vendorcode/mediatek/mt8192/include/custom_emi.h
A src/vendorcode/mediatek/mt8192/include/ddrphy_nao_reg.h
A src/vendorcode/mediatek/mt8192/include/ddrphy_pll_reg.h
A src/vendorcode/mediatek/mt8192/include/ddrphy_wo_pll_reg.h
A src/vendorcode/mediatek/mt8192/include/dramc_actiming.h
A src/vendorcode/mediatek/mt8192/include/dramc_ch0_nao_reg.h
A src/vendorcode/mediatek/mt8192/include/dramc_ch0_reg.h
A src/vendorcode/mediatek/mt8192/include/dramc_common.h
A src/vendorcode/mediatek/mt8192/include/dramc_dv_init.h
A src/vendorcode/mediatek/mt8192/include/dramc_int_global.h
A src/vendorcode/mediatek/mt8192/include/dramc_int_slt.h
A src/vendorcode/mediatek/mt8192/include/dramc_pi_api.h
A src/vendorcode/mediatek/mt8192/include/dramc_reg_base_addr.h
A src/vendorcode/mediatek/mt8192/include/dramc_register.h
A src/vendorcode/mediatek/mt8192/include/dramc_top.h
A src/vendorcode/mediatek/mt8192/include/dramc_typedefs.h
A src/vendorcode/mediatek/mt8192/include/emi.h
A src/vendorcode/mediatek/mt8192/include/emi_hw.h
A src/vendorcode/mediatek/mt8192/include/emi_mpu_mt.h
A src/vendorcode/mediatek/mt8192/include/emi_mpu_v1.h
A src/vendorcode/mediatek/mt8192/include/memory.h
A src/vendorcode/mediatek/mt8192/include/pmic_wrap_init.h
A src/vendorcode/mediatek/mt8192/include/print.h
A src/vendorcode/mediatek/mt8192/include/reg.h
A src/vendorcode/mediatek/mt8192/include/soc/dpm.h
A src/vendorcode/mediatek/mt8192/include/soc/dramc_common_mt8192.h
A src/vendorcode/mediatek/mt8192/include/soc/dramc_param.h
A src/vendorcode/mediatek/mt8192/include/soc/emi.h
A src/vendorcode/mediatek/mt8192/include/stdint.h
A src/vendorcode/mediatek/mt8192/include/sv_c_data_traffic.h
A src/vendorcode/mediatek/mt8192/include/sys/types.h
A src/vendorcode/mediatek/mt8192/include/uart.h
A src/vendorcode/mediatek/mt8192/include/x_hal_io.h
A src/vendorcode/mediatek/mt8192/lib/Makefile.inc
A src/vendorcode/mediatek/mt8192/lib/print.c
A src/vendorcode/mediatek/mt8192/memory.c
72 files changed, 87,958 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/50294/8
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Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50294 )
Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization codes
......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50294/comment/24d166a1_4fdeb48d
PS5, Line 11:
> However, in case Mediatek maintains a public Git repository, we could also integrated that as a submodule. I assume they don't do that?
No, there is no such public git repo yet. I have also told Xi/MTK about that approach before but I think they want to start with vendor code first.
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