coreboot-gerrit March 2021

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Change in coreboot[master]: mb/google/zork/var/shuboz: Decrease I2C3 CLK below 400 kHz
by Patrick Georgi (Code Review) 01 Mar '21

01 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51052 ) Change subject: mb/google/zork/var/shuboz: Decrease I2C3 CLK below 400 kHz ...................................................................... mb/google/zork/var/shuboz: Decrease I2C3 CLK below 400 kHz Modify I2C3 setting to follow I2C specification (lower than 400kHz). Original setting: .rise_time_ns = 184 .fall_time_ns = 42 Change to: .rise_time_ns = 110 .fall_time_ns = 34 BUG=b:181091107 BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: Ibdbb9a7dde524bdbde4789ee7ea005646080d97a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51052 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/mainboard/google/zork/variants/shuboz/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Kane Chen: Looks good to me, but someone else must approve Kangheui Won: Looks good to me, approved diff --git a/src/mainboard/google/zork/variants/shuboz/overridetree.cb b/src/mainboard/google/zork/variants/shuboz/overridetree.cb index 436f0ed..16c18b5 100644 --- a/src/mainboard/google/zork/variants/shuboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/shuboz/overridetree.cb @@ -35,8 +35,8 @@ register "i2c[3]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 184, /* 0 to 1.26v (1.8 * .7) */ - .fall_time_ns = 42, /* 1.26v to 0 */ + .rise_time_ns = 110, /* 0 to 1.26v (1.8 * .7) */ + .fall_time_ns = 34, /* 1.26v to 0 */ .early_init = true, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/51052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdbb9a7dde524bdbde4789ee7ea005646080d97a Gerrit-Change-Number: 51052 Gerrit-PatchSet: 3 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/sandybridge: Clean up `dram_timing` function
by Angel Pons (Code Review) 01 Mar '21

01 Mar '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45501 ) Change subject: nb/intel/sandybridge: Clean up `dram_timing` function ...................................................................... nb/intel/sandybridge: Clean up `dram_timing` function Compute timings first, then display them. Drop unneeded comments and a double empty line before the start of the function. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I121cf9c4db76ec0ced36caf764b1a1a51e47b552 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_native.c 1 file changed, 11 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/45501/1 diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index a469910..64a381d 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -302,7 +302,6 @@ ctrl->CAS = val; } - static void dram_timing(ramctr_timing *ctrl) { /* @@ -424,42 +423,15 @@ else ctrl->CWL = get_CWL(ctrl->tCK); - printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); - - /* Find tRCD */ ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD); - ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP); - - /* Find tRAS */ ctrl->tRAS = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS); - - /* Find tWR */ ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR); - - /* Find tFAW */ ctrl->tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW); - - /* Find tRRD */ ctrl->tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD); - - /* Find tRTP */ ctrl->tRTP = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP); - - /* Find tWTR */ ctrl->tWTR = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR); - - /* Refresh-to-Active or Refresh-to-Refresh (tRFC) */ ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); ctrl->tREFI = get_REFI(ctrl->FRQ, ctrl->base_freq); ctrl->tMOD = get_MOD(ctrl->FRQ, ctrl->base_freq); @@ -469,6 +441,17 @@ ctrl->tXPDLL = get_XPDLL(ctrl->FRQ, ctrl->base_freq); ctrl->tXP = get_XP(ctrl->FRQ, ctrl->base_freq); ctrl->tAONPD = get_AONPD(ctrl->FRQ, ctrl->base_freq); + + printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); + printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD); + printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP); + printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS); + printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR); + printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW); + printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD); + printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP); + printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR); + printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); } static void dram_freq(ramctr_timing *ctrl) -- To view, visit https://review.coreboot.org/c/coreboot/+/45501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I121cf9c4db76ec0ced36caf764b1a1a51e47b552 Gerrit-Change-Number: 45501 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: tests: Add lib/memmove-test test case
by Patrick Georgi (Code Review) 01 Mar '21

01 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50902 ) Change subject: tests: Add lib/memmove-test test case ...................................................................... tests: Add lib/memmove-test test case Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: Ic9b68eb0fa85bbc3f66d57cdcb329073b26bea57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50902 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org> --- M tests/lib/Makefile.inc A tests/lib/memmove-test.c 2 files changed, 253 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Fagerburg: Looks good to me, approved diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index d31608c..0f978e7 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -19,6 +19,7 @@ tests-y += memchr-test tests-y += memcpy-test tests-y += malloc-test +tests-y += memmove-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -95,3 +96,5 @@ malloc-test-srcs += tests/lib/malloc-test.c malloc-test-srcs += tests/stubs/console.c +memmove-test-srcs += tests/lib/memmove-test.c + diff --git a/tests/lib/memmove-test.c b/tests/lib/memmove-test.c new file mode 100644 index 0000000..a1d33cf --- /dev/null +++ b/tests/lib/memmove-test.c @@ -0,0 +1,250 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define memmove cb_memmove +#include "../lib/memmove.c" +#undef memmove + +#include <stdlib.h> +#include <tests/test.h> +#include <commonlib/helpers.h> +#include <types.h> + +#define MEMMOVE_BUFFER_SZ (4 * KiB) + +/* Prototype of memmove() from string.h was changed to cb_memmove(). + It has to be defined again. */ +void *memmove(void *dst, const void *src, size_t n); + +struct test_memmove_data { + u8 *buffer_from; + u8 *buffer_to; + u8 *helper_buffer; +}; + +int setup_test(void **state) +{ + struct test_memmove_data *s = malloc(sizeof(struct test_memmove_data)); + + if (!s) + return -1; + + s->buffer_from = malloc(MEMMOVE_BUFFER_SZ); + s->buffer_to = malloc(MEMMOVE_BUFFER_SZ); + s->helper_buffer = malloc(MEMMOVE_BUFFER_SZ); + + if (!s->buffer_from || !s->buffer_to || !s->helper_buffer) { + free(s->buffer_from); + free(s->buffer_to); + free(s->helper_buffer); + free(s); + return -1; + } + + /* Fill buffers with different values (other than zero) to make them distinguishable. + The helper buffer is often used as a backup of destination buffer so it has the + same value. */ + memset(s->buffer_from, 0xAB, MEMMOVE_BUFFER_SZ); + memset(s->buffer_to, 0xBC, MEMMOVE_BUFFER_SZ); + memset(s->helper_buffer, 0xBC, MEMMOVE_BUFFER_SZ); + + *state = s; + + return 0; +} + +int teardown_test(void **state) +{ + struct test_memmove_data *s = *state; + + free(s->buffer_from); + free(s->buffer_to); + free(s->helper_buffer); + free(s); + + return 0; +} + +/* Fill buffer with values from provided range [start; end] in circular way. */ +static void fill_buffer_data_range(u8 *buffer, size_t sz, u8 start_value, u8 end_value) +{ + for (size_t i = 0; i < sz; ++i) + buffer[i] = (start_value + i) % (end_value - start_value + 1); +} + +static void test_memmove_full_buffer_copy(void **state) +{ + struct test_memmove_data *s = *state; + void *res_cb; + + fill_buffer_data_range(s->buffer_from, MEMMOVE_BUFFER_SZ, 0, 255); + + res_cb = cb_memmove(s->buffer_to, s->buffer_from, MEMMOVE_BUFFER_SZ); + + assert_ptr_equal(s->buffer_to, res_cb); + assert_memory_equal(s->buffer_from, s->buffer_to, MEMMOVE_BUFFER_SZ); +} + +static void test_memmove_zero_size(void **state) +{ + struct test_memmove_data *s = *state; + void *res_cb; + + fill_buffer_data_range(s->buffer_from, MEMMOVE_BUFFER_SZ, 'A', 'Z'); + + /* Expect no change in destination buffer. */ + res_cb = cb_memmove(s->buffer_to, s->buffer_from, 0); + assert_ptr_equal(res_cb, s->buffer_to); + assert_memory_equal(s->buffer_to, s->helper_buffer, MEMMOVE_BUFFER_SZ); +} + +static void test_memmove_buffer_part(void **state) +{ + struct test_memmove_data *s = *state; + void *res_cb; + const size_t offset = MEMMOVE_BUFFER_SZ / 4; + const size_t sz = MEMMOVE_BUFFER_SZ / 3; + + /* Self-test for correct data ranges */ + assert_true(offset + sz <= MEMMOVE_BUFFER_SZ); + + fill_buffer_data_range(s->buffer_from, MEMMOVE_BUFFER_SZ, '0', '9'); + + /* Expect only *sz* bytes of buffer to be copied. Helper buffer is used as template. */ + res_cb = cb_memmove(s->buffer_to + offset, s->buffer_from, sz); + assert_ptr_equal(s->buffer_to + offset, res_cb); + assert_memory_equal(s->buffer_to, s->helper_buffer, offset); + assert_memory_equal(s->buffer_to + offset, s->buffer_from, sz); + assert_memory_equal(s->buffer_to + offset + sz, s->helper_buffer + offset + sz, + MEMMOVE_BUFFER_SZ - (offset + sz)); +} + +static void test_memmove_buffer_part_unaligned(void **state) +{ + struct test_memmove_data *s = *state; + void *res_cb; + const size_t dst_offset = MEMMOVE_BUFFER_SZ / 8 + 3; + const size_t src_offset = MEMMOVE_BUFFER_SZ / 4 - 3; + const size_t sz = MEMMOVE_BUFFER_SZ / 4 + 7; + + /* Self-test for correct data ranges */ + assert_true(dst_offset + sz <= MEMMOVE_BUFFER_SZ); + assert_true(src_offset + sz <= MEMMOVE_BUFFER_SZ); + + fill_buffer_data_range(s->buffer_from, MEMMOVE_BUFFER_SZ, 0x13, 0xB7); + + res_cb = cb_memmove(s->buffer_to + dst_offset, s->buffer_from + src_offset, sz); + assert_ptr_equal(s->buffer_to + dst_offset, res_cb); + assert_memory_equal(s->buffer_to, s->helper_buffer, dst_offset); + assert_memory_equal(s->buffer_to + dst_offset, s->buffer_from + src_offset, sz); + assert_memory_equal(s->buffer_to + dst_offset + sz, s->helper_buffer + dst_offset + sz, + MEMMOVE_BUFFER_SZ - (dst_offset + sz)); +} + +static void test_memmove_copy_to_itself(void **state) +{ + struct test_memmove_data *s = *state; + void *res_cb; + + fill_buffer_data_range(s->buffer_to, MEMMOVE_BUFFER_SZ, 'G', 'X'); + memmove(s->buffer_to, s->helper_buffer, MEMMOVE_BUFFER_SZ); + + /* Expect no change in source/destination buffer. */ + res_cb = cb_memmove(s->buffer_to, s->buffer_to, MEMMOVE_BUFFER_SZ); + assert_ptr_equal(res_cb, s->buffer_to); + assert_memory_equal(s->buffer_to, s->helper_buffer, MEMMOVE_BUFFER_SZ); +} + +static void test_memmove_self_higher_to_lower(void **state) +{ + struct test_memmove_data *s = *state; + void *res_cb; + const size_t offset = MEMMOVE_BUFFER_SZ / 8; + const size_t sz = MEMMOVE_BUFFER_SZ - offset; + + fill_buffer_data_range(s->buffer_to, MEMMOVE_BUFFER_SZ, 'd', 'v'); + memmove(s->helper_buffer, s->buffer_to, MEMMOVE_BUFFER_SZ); + + /* Expect only *sz* bytes to be overwritten and *offset* bytes to be left at the end. */ + res_cb = cb_memmove(s->buffer_to, s->buffer_to + offset, sz); + assert_ptr_equal(res_cb, s->buffer_to); + assert_memory_equal(s->buffer_to, s->helper_buffer + offset, sz); + assert_memory_equal(s->buffer_to + sz, s->helper_buffer + sz, offset); +} + +static void test_memmove_self_higher_to_lower_unaligned(void **state) +{ + struct test_memmove_data *s = *state; + void *res_cb; + const size_t offset = MEMMOVE_BUFFER_SZ / 6 + 7; + const size_t sz = MEMMOVE_BUFFER_SZ - offset; + + fill_buffer_data_range(s->buffer_to, MEMMOVE_BUFFER_SZ, 'd', 'v'); + memmove(s->helper_buffer, s->buffer_to, MEMMOVE_BUFFER_SZ); + + /* Expect only *sz* bytes to be overwritten and *offset* bytes to be left at the end. */ + res_cb = cb_memmove(s->buffer_to, s->buffer_to + offset, sz); + assert_ptr_equal(res_cb, s->buffer_to); + assert_memory_equal(s->buffer_to, s->helper_buffer + offset, sz); + assert_memory_equal(s->buffer_to + sz, s->helper_buffer + sz, offset); +} + +static void test_memmove_self_lower_to_higher(void **state) +{ + struct test_memmove_data *s = *state; + void *res_cb; + const size_t offset = MEMMOVE_BUFFER_SZ / 4; + const size_t sz = MEMMOVE_BUFFER_SZ - offset; + + fill_buffer_data_range(s->buffer_to, MEMMOVE_BUFFER_SZ, 'd', 'v'); + memmove(s->helper_buffer, s->buffer_to, MEMMOVE_BUFFER_SZ); + + /* Expect only *sz* bytes to be overwritten and *offset* bytes to be left at the end. */ + res_cb = cb_memmove(s->buffer_to + offset, s->buffer_to, sz); + assert_ptr_equal(res_cb, s->buffer_to + offset); + assert_memory_equal(s->buffer_to + offset, s->helper_buffer, sz); + assert_memory_equal(s->buffer_to, s->helper_buffer, offset); +} + +static void test_memmove_self_lower_to_higher_unaligned(void **state) +{ + struct test_memmove_data *s = *state; + void *res_cb; + const size_t offset = MEMMOVE_BUFFER_SZ / 4 - 17; + const size_t sz = MEMMOVE_BUFFER_SZ - offset; + + fill_buffer_data_range(s->buffer_to, MEMMOVE_BUFFER_SZ, 'd', 'v'); + memmove(s->helper_buffer, s->buffer_to, MEMMOVE_BUFFER_SZ); + + /* Expect only *sz* bytes to be overwritten and *offset* bytes to be left at the end. */ + res_cb = cb_memmove(s->buffer_to + offset, s->buffer_to, sz); + assert_ptr_equal(res_cb, s->buffer_to + offset); + assert_memory_equal(s->buffer_to + offset, s->helper_buffer, sz); + assert_memory_equal(s->buffer_to, s->helper_buffer, offset); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test_setup_teardown(test_memmove_full_buffer_copy, + setup_test, teardown_test), + cmocka_unit_test_setup_teardown(test_memmove_zero_size, + setup_test, teardown_test), + cmocka_unit_test_setup_teardown(test_memmove_buffer_part, + setup_test, teardown_test), + cmocka_unit_test_setup_teardown(test_memmove_buffer_part_unaligned, + setup_test, teardown_test), + cmocka_unit_test_setup_teardown(test_memmove_copy_to_itself, + setup_test, teardown_test), + cmocka_unit_test_setup_teardown(test_memmove_self_higher_to_lower, + setup_test, teardown_test), + cmocka_unit_test_setup_teardown(test_memmove_self_higher_to_lower_unaligned, + setup_test, teardown_test), + cmocka_unit_test_setup_teardown(test_memmove_self_lower_to_higher, + setup_test, teardown_test), + cmocka_unit_test_setup_teardown(test_memmove_self_lower_to_higher_unaligned, + setup_test, teardown_test), + }; + + return cmocka_run_group_tests(tests, NULL, NULL); +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/50902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9b68eb0fa85bbc3f66d57cdcb329073b26bea57 Gerrit-Change-Number: 50902 Gerrit-PatchSet: 5 Gerrit-Owner: jacz(a)semihalf.com Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: sb/intel/bd82x6x: Turn ME PCI register structs into unions
by Patrick Georgi (Code Review) 01 Mar '21

01 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49993 ) Change subject: sb/intel/bd82x6x: Turn ME PCI register structs into unions ...................................................................... sb/intel/bd82x6x: Turn ME PCI register structs into unions This allows dropping the `pci_read_dword_ptr` and `pci_write_dword_ptr` wrappers. Change-Id: I7a6916e535fbba9f05451d5302261418f950be83 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49993 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/southbridge/intel/bd82x6x/early_me.c M src/southbridge/intel/bd82x6x/early_me_mrc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/me_common.c M src/southbridge/intel/bd82x6x/me_smm.c M src/southbridge/intel/bd82x6x/me_status.c 8 files changed, 105 insertions(+), 121 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index 51c19d1..a47991c 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -24,24 +24,18 @@ [ME_HFS_ACK_CONTINUE] = "Continue to boot" }; -static inline void pci_read_dword_ptr(void *ptr, int offset) -{ - u32 dword = pci_read_config32(PCH_ME_DEV, offset); - memcpy(ptr, &dword, sizeof(dword)); -} - void intel_early_me_status(void) { - struct me_hfs hfs; - struct me_gmes gmes; + union me_hfs hfs; + union me_gmes gmes; u32 id = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); if ((id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000)) { printk(BIOS_DEBUG, "Missing Intel ME PCI device.\n"); } else { - pci_read_dword_ptr(&hfs, PCI_ME_HFS); - pci_read_dword_ptr(&gmes, PCI_ME_GMES); + hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); + gmes.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_GMES); intel_me_status(&hfs, &gmes); } @@ -50,14 +44,14 @@ int intel_early_me_init(void) { int count; - struct me_uma uma; - struct me_hfs hfs; + union me_uma uma; + union me_hfs hfs; printk(BIOS_INFO, "Intel ME early init\n"); /* Wait for ME UMA SIZE VALID bit to be set */ for (count = ME_RETRY; count > 0; --count) { - pci_read_dword_ptr(&uma, PCI_ME_UMA); + uma.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA); if (uma.valid) break; udelay(ME_DELAY); @@ -68,7 +62,7 @@ } /* Check for valid firmware */ - pci_read_dword_ptr(&hfs, PCI_ME_HFS); + hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); if (hfs.fpt_bad) { printk(BIOS_WARNING, "WARNING: ME has bad firmware\n"); return -1; @@ -80,9 +74,9 @@ int intel_early_me_uma_size(void) { - struct me_uma uma; + union me_uma uma; - pci_read_dword_ptr(&uma, PCI_ME_UMA); + uma.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA); if (uma.valid) { printk(BIOS_DEBUG, "ME: Requested %uMB UMA\n", uma.size); return uma.size; @@ -98,7 +92,7 @@ u32 mebase_l, mebase_h; u32 millisec; u32 hfs, me_fws2; - struct me_did did = { + union me_did did = { .init_done = ME_INIT_DONE, .status = status }; diff --git a/src/southbridge/intel/bd82x6x/early_me_mrc.c b/src/southbridge/intel/bd82x6x/early_me_mrc.c index 180e466..9d46897 100644 --- a/src/southbridge/intel/bd82x6x/early_me_mrc.c +++ b/src/southbridge/intel/bd82x6x/early_me_mrc.c @@ -22,31 +22,18 @@ [ME_HFS_ACK_CONTINUE] = "Continue to boot" }; -static inline void pci_read_dword_ptr(void *ptr, int offset) -{ - u32 dword = pci_read_config32(PCH_ME_DEV, offset); - memcpy(ptr, &dword, sizeof(dword)); -} - -static inline void pci_write_dword_ptr(void *ptr, int offset) -{ - u32 dword = 0; - memcpy(&dword, ptr, sizeof(dword)); - pci_write_config32(PCH_ME_DEV, offset, dword); -} - void intel_early_me_status(void) { - struct me_hfs hfs; - struct me_gmes gmes; + union me_hfs hfs; + union me_gmes gmes; u32 id = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); if ((id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000)) { printk(BIOS_DEBUG, "Missing Intel ME PCI device.\n"); } else { - pci_read_dword_ptr(&hfs, PCI_ME_HFS); - pci_read_dword_ptr(&gmes, PCI_ME_GMES); + hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); + gmes.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_GMES); intel_me_status(&hfs, &gmes); } @@ -55,14 +42,14 @@ int intel_early_me_init(void) { int count; - struct me_uma uma; - struct me_hfs hfs; + union me_uma uma; + union me_hfs hfs; printk(BIOS_INFO, "Intel ME early init\n"); /* Wait for ME UMA SIZE VALID bit to be set */ for (count = ME_RETRY; count > 0; --count) { - pci_read_dword_ptr(&uma, PCI_ME_UMA); + uma.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA); if (uma.valid) break; udelay(ME_DELAY); @@ -73,7 +60,7 @@ } /* Check for valid firmware */ - pci_read_dword_ptr(&hfs, PCI_ME_HFS); + hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); if (hfs.fpt_bad) { printk(BIOS_WARNING, "WARNING: ME has bad firmware\n"); return -1; @@ -85,9 +72,9 @@ int intel_early_me_uma_size(void) { - struct me_uma uma; + union me_uma uma; - pci_read_dword_ptr(&uma, PCI_ME_UMA); + uma.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA); if (uma.valid) { printk(BIOS_DEBUG, "ME: Requested %uMB UMA\n", uma.size); return uma.size; @@ -102,8 +89,8 @@ u8 reset; int count; u32 mebase_l, mebase_h; - struct me_hfs hfs; - struct me_did did = { + union me_hfs hfs; + union me_did did = { .init_done = ME_INIT_DONE, .status = status }; @@ -117,11 +104,11 @@ printk(BIOS_DEBUG, "ME: Sending Init Done with status: %d, " "UMA base: 0x%04x\n", status, did.uma_base); - pci_write_dword_ptr(&did, PCI_ME_H_GS); + pci_write_config32(PCH_ME_DEV, PCI_ME_H_GS, did.raw); /* Must wait for ME acknowledgement */ for (count = ME_RETRY; count > 0; --count) { - pci_read_dword_ptr(&hfs, PCI_ME_HFS); + hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); if (hfs.bios_msg_ack) break; udelay(ME_DELAY); diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index cb26362..cda2540 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -31,15 +31,15 @@ static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; - struct me_hfs hfs; - struct me_gmes gmes; + union me_hfs hfs; + union me_gmes gmes; /* S3 wake skips all MKHI messages */ if (acpi_is_wakeup_s3()) return ME_S3WAKE_BIOS_PATH; - pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); - pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES); + hfs.raw = pci_read_config32(dev, PCI_ME_HFS); + gmes.raw = pci_read_config32(dev, PCI_ME_GMES); /* Check and dump status */ intel_me_status(&hfs, &gmes); @@ -180,7 +180,7 @@ me_bios_path path = intel_me_path(dev); u8 me_state = 0, me_state_prev = 0; bool need_reset = false; - struct me_hfs hfs; + union me_hfs hfs; /* Do initial setup and determine the BIOS path */ printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_get_bios_path_string(path)); @@ -236,7 +236,7 @@ case ME_DISABLE_BIOS_PATH: /* Bring ME out of Soft Temporary Disable mode, if needed */ - pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); + hfs.raw = pci_read_config32(dev, PCI_ME_HFS); if (hfs.operation_mode == ME_HFS_MODE_DIS && me_state == CMOS_ME_STATE_NORMAL && (CMOS_ME_STATE(me_state_prev) == CMOS_ME_STATE_DISABLED diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 7e1a3bc..0cb6496 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -47,30 +47,36 @@ #define ME_HFS_ACK_GBL_RESET 6 #define ME_HFS_ACK_CONTINUE 7 -struct me_hfs { - u32 working_state: 4; - u32 mfg_mode: 1; - u32 fpt_bad: 1; - u32 operation_state: 3; - u32 fw_init_complete: 1; - u32 ft_bup_ld_flr: 1; - u32 update_in_progress: 1; - u32 error_code: 4; - u32 operation_mode: 4; - u32 reserved: 4; - u32 boot_options_present: 1; - u32 ack_data: 3; - u32 bios_msg_ack: 4; +union me_hfs { + struct { + u32 working_state: 4; + u32 mfg_mode: 1; + u32 fpt_bad: 1; + u32 operation_state: 3; + u32 fw_init_complete: 1; + u32 ft_bup_ld_flr: 1; + u32 update_in_progress: 1; + u32 error_code: 4; + u32 operation_mode: 4; + u32 reserved: 4; + u32 boot_options_present: 1; + u32 ack_data: 3; + u32 bios_msg_ack: 4; + }; + u32 raw; } __packed; #define PCI_ME_UMA 0x44 -struct me_uma { - u32 size: 6; - u32 reserved_1: 10; - u32 valid: 1; - u32 reserved_0: 14; - u32 set_to_one: 1; +union me_uma { + struct { + u32 size: 6; + u32 reserved_1: 10; + u32 valid: 1; + u32 reserved_0: 14; + u32 set_to_one: 1; + }; + u32 raw; } __packed; #define PCI_ME_H_GS 0x4c @@ -79,11 +85,14 @@ #define ME_INIT_STATUS_NOMEM 1 #define ME_INIT_STATUS_ERROR 2 -struct me_did { - u32 uma_base: 16; - u32 reserved: 8; - u32 status: 4; - u32 init_done: 4; +union me_did { + struct { + u32 uma_base: 16; + u32 reserved: 8; + u32 status: 4; + u32 init_done: 4; + }; + u32 raw; } __packed; #define PCI_ME_GMES 0x48 @@ -95,21 +104,24 @@ #define ME_GMES_PHASE_UNKNOWN 5 #define ME_GMES_PHASE_HOST 6 -struct me_gmes { - u32 bist_in_prog : 1; - u32 icc_prog_sts : 2; - u32 invoke_mebx : 1; - u32 cpu_replaced_sts : 1; - u32 mbp_rdy : 1; - u32 mfs_failure : 1; - u32 warm_rst_req_for_df : 1; - u32 cpu_replaced_valid : 1; - u32 reserved_1 : 2; - u32 fw_upd_ipu : 1; - u32 reserved_2 : 4; - u32 current_state: 8; - u32 current_pmevent: 4; - u32 progress_code: 4; +union me_gmes { + struct { + u32 bist_in_prog : 1; + u32 icc_prog_sts : 2; + u32 invoke_mebx : 1; + u32 cpu_replaced_sts : 1; + u32 mbp_rdy : 1; + u32 mfs_failure : 1; + u32 warm_rst_req_for_df : 1; + u32 cpu_replaced_valid : 1; + u32 reserved_1 : 2; + u32 fw_upd_ipu : 1; + u32 reserved_2 : 4; + u32 current_state: 8; + u32 current_pmevent: 4; + u32 progress_code: 4; + }; + u32 raw; } __packed; #define PCI_ME_HERES 0xbc @@ -117,11 +129,14 @@ #define PCI_ME_EXT_SHA256 0x02 #define PCI_ME_HER(x) (0xc0+(4*(x))) -struct me_heres { - u32 extend_reg_algorithm: 4; - u32 reserved: 26; - u32 extend_feature_present: 1; - u32 extend_reg_valid: 1; +union me_heres { + struct { + u32 extend_reg_algorithm: 4; + u32 reserved: 26; + u32 extend_feature_present: 1; + u32 extend_reg_valid: 1; + }; + u32 raw; } __packed; /* @@ -243,7 +258,6 @@ void mei_write_dword_ptr(void *ptr, int offset); #ifndef __SIMPLE_DEVICE__ -void pci_read_dword_ptr(struct device *dev, void *ptr, int offset); bool enter_soft_temp_disable(void); void enter_soft_temp_disable_wait(void); void exit_soft_temp_disable(struct device *dev); @@ -268,7 +282,7 @@ void intel_me_hide(struct device *dev); /* Defined in me_status.c for both romstage and ramstage */ -void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes); +void intel_me_status(union me_hfs *hfs, union me_gmes *gmes); void intel_early_me_status(void); int intel_early_me_init(void); diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index a0516b8..abca881 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -49,15 +49,15 @@ static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; - struct me_hfs hfs; - struct me_gmes gmes; + union me_hfs hfs; + union me_gmes gmes; /* S3 wake skips all MKHI messages */ if (acpi_is_wakeup_s3()) return ME_S3WAKE_BIOS_PATH; - pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); - pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES); + hfs.raw = pci_read_config32(dev, PCI_ME_HFS); + gmes.raw = pci_read_config32(dev, PCI_ME_GMES); /* Check and dump status */ intel_me_status(&hfs, &gmes); @@ -178,7 +178,7 @@ me_bios_payload mbp_data; u8 me_state = 0, me_state_prev = 0; bool need_reset = false; - struct me_hfs hfs; + union me_hfs hfs; /* Do initial setup and determine the BIOS path */ printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_get_bios_path_string(path)); @@ -235,7 +235,7 @@ case ME_DISABLE_BIOS_PATH: /* Bring ME out of Soft Temporary Disable mode, if needed */ - pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); + hfs.raw = pci_read_config32(dev, PCI_ME_HFS); if (hfs.operation_mode == ME_HFS_MODE_DIS && me_state == CMOS_ME_STATE_NORMAL && (CMOS_ME_STATE(me_state_prev) == CMOS_ME_STATE_DISABLED diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index e229956..1c6899d 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -88,15 +88,6 @@ mei_dump(ptr, dword, offset, "WRITE"); } -#ifndef __SIMPLE_DEVICE__ -void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) -{ - u32 dword = pci_read_config32(dev, offset); - memcpy(ptr, &dword, sizeof(dword)); - mei_dump(ptr, dword, offset, "PCI READ"); -} -#endif - void read_host_csr(struct mei_csr *csr) { mei_read_dword_ptr(csr, MEI_H_CSR); @@ -368,11 +359,11 @@ /* Read the Extend register hash of ME firmware */ int intel_me_extend_valid(struct device *dev) { - struct me_heres status; + union me_heres status; u32 extend[8] = {0}; int i, count = 0; - pci_read_dword_ptr(dev, &status, PCI_ME_HERES); + status.raw = pci_read_config32(dev, PCI_ME_HERES); if (!status.extend_feature_present) { printk(BIOS_ERR, "ME: Extend Feature not present\n"); return -1; @@ -469,7 +460,7 @@ void exit_soft_temp_disable_wait(struct device *dev) { - struct me_hfs hfs; + union me_hfs hfs; struct stopwatch sw; stopwatch_init_msecs_expire(&sw, ME_ENABLE_TIMEOUT); @@ -480,7 +471,7 @@ */ do { mdelay(50); - pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); + hfs.raw = pci_read_config32(dev, PCI_ME_HFS); if (hfs.fw_init_complete) break; } while (!stopwatch_expired(&sw)); diff --git a/src/southbridge/intel/bd82x6x/me_smm.c b/src/southbridge/intel/bd82x6x/me_smm.c index 11f55c2..e1eb900 100644 --- a/src/southbridge/intel/bd82x6x/me_smm.c +++ b/src/southbridge/intel/bd82x6x/me_smm.c @@ -64,8 +64,7 @@ void intel_me_finalize_smm(void) { - struct me_hfs hfs; - u32 reg32; + union me_hfs hfs; update_mei_base_address(); @@ -74,8 +73,7 @@ return; /* Make sure ME is in a mode that expects EOP */ - reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); - memcpy(&hfs, &reg32, sizeof(u32)); + hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); /* Abort and leave device alone if not normal mode */ if (hfs.fpt_bad || diff --git a/src/southbridge/intel/bd82x6x/me_status.c b/src/southbridge/intel/bd82x6x/me_status.c index 52a68ce..b12d052 100644 --- a/src/southbridge/intel/bd82x6x/me_status.c +++ b/src/southbridge/intel/bd82x6x/me_status.c @@ -122,7 +122,7 @@ [0x10] = "Required VSCC values for flash parts do not match", }; -void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes) +void intel_me_status(union me_hfs *hfs, union me_gmes *gmes) { if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL < BIOS_DEBUG) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/49993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a6916e535fbba9f05451d5302261418f950be83 Gerrit-Change-Number: 49993 Gerrit-PatchSet: 7 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: amd_blobs: Update cezanne PSP Secure OS
by Patrick Georgi (Code Review) 01 Mar '21

01 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51109 ) Change subject: amd_blobs: Update cezanne PSP Secure OS ...................................................................... amd_blobs: Update cezanne PSP Secure OS Avoid a Secure OS Abort. This prevents coreboot timing out on C2P mailbox commands and allows HDT unlocking. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I358530a1ba959ee1896e26a47853c9918ee124b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51109 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M 3rdparty/amd_blobs 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 54778b5..302c9f6 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 54778b5117c6b012460abe9d26659ebf739a3370 +Subproject commit 302c9f61488b2117f5315e4094ec044cc8ceb0ea -- To view, visit https://review.coreboot.org/c/coreboot/+/51109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I358530a1ba959ee1896e26a47853c9918ee124b4 Gerrit-Change-Number: 51109 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: Add PSP whitelist debug unlock support
by Patrick Georgi (Code Review) 01 Mar '21

01 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51078 ) Change subject: soc/amd/cezanne: Add PSP whitelist debug unlock support ...................................................................... soc/amd/cezanne: Add PSP whitelist debug unlock support Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ibe3136682d2a9d248d5c6f26957e69013e4847ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/51078 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/cezanne/fw.cfg 3 files changed, 24 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index f8c38d0..4a308df 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -235,6 +235,21 @@ help Select this item to enable secure debug options in PSP. +config HAVE_PSP_WHITELIST_FILE + bool "Include a debug whitelist file in PSP build" + default n + help + Support secured unlock prior to reset using a whitelisted + serial number. This feature requires a signed whitelist image + and bootloader from AMD. + + If unsure, answer 'n' + +config PSP_WHITELIST_FILE + string "Debug whitelist file path" + depends on HAVE_PSP_WHITELIST_FILE + default "3rdparty/amd_blobs/cezanne/PSP/wtl-czn.sbin" + endmenu endif # SOC_AMD_CEZANNE diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index d631c63..35e7009 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -85,6 +85,11 @@ PSP_SOFTFUSE_BITS += 29 endif +# type = 0x3a +ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) +PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) +endif + # # BIOS Directory Table items - proper ordering is managed by amdfwtool # @@ -134,6 +139,8 @@ OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) +OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) + # Add all the files listed in the config file POUND_SIGN=$(call strip_quotes, "\#") DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /*/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) @@ -149,6 +156,7 @@ --load-s0i3 \ --combo-capable \ $(OPT_TOKEN_UNLOCK) \ + $(OPT_WHITELIST_FILE) \ $(OPT_EFS_SPI_READ_MODE) \ $(OPT_EFS_SPI_SPEED) \ $(OPT_EFS_SPI_MICRON_FLAG) \ diff --git a/src/soc/amd/cezanne/fw.cfg b/src/soc/amd/cezanne/fw.cfg index 277707d..9757d72 100644 --- a/src/soc/amd/cezanne/fw.cfg +++ b/src/soc/amd/cezanne/fw.cfg @@ -6,6 +6,7 @@ # PSP AMD_PUBKEY_FILE TypeId0x00_CezannePublicKey.tkn PSPBTLDR_FILE TypeId0x01_PspBootLoader_CZN.sbin +PSPBTLDR_WL_FILE TypeId0x01_PspBootLoader_WL_CZN.sbin PSPSECUREOS_FILE TypeId0x02_PspOS_CZN.sbin PSPRCVR_FILE TypeId0x03_PspRecoveryBootLoader_CZN.sbin PSP_SMUFW1_SUB0_FILE TypeId0x08_SmuFirmware_CZN.csbin -- To view, visit https://review.coreboot.org/c/coreboot/+/51078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe3136682d2a9d248d5c6f26957e69013e4847ac Gerrit-Change-Number: 51078 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: amd_blobs: Add cezanne whitelist bootloader
by Patrick Georgi (Code Review) 01 Mar '21

01 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51102 ) Change subject: amd_blobs: Add cezanne whitelist bootloader ...................................................................... amd_blobs: Add cezanne whitelist bootloader Advance the pointer to pick up the PSP whitelist bootloader. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I45da509ee6f782cbe64e7099f3945129282060b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51102 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M 3rdparty/amd_blobs 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index b127449..54778b5 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit b12744905dd20c77154db99a379543f61a3e3e7f +Subproject commit 54778b5117c6b012460abe9d26659ebf739a3370 -- To view, visit https://review.coreboot.org/c/coreboot/+/51102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45da509ee6f782cbe64e7099f3945129282060b4 Gerrit-Change-Number: 51102 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/haswell: Fix DPR size handling
by Patrick Georgi (Code Review) 01 Mar '21

01 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51104 ) Change subject: nb/intel/haswell: Fix DPR size handling ...................................................................... nb/intel/haswell: Fix DPR size handling DPR register's size field is given in whole MiB, so correct where it is used to ensure the correct size multiple (KiB vs. MiB) is used with it. Fixes: 5d7c3a4f0 ("nb/intel/haswell/northbridge.c: Correct DPR handling") Change-Id: I3ca388907c61f1e47eab44ae8bc26e0f611fe1e3 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51104 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/intel/haswell/northbridge.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index df9cc18..b19e7bd 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -298,12 +298,12 @@ /* 0xc0000 -> TSEG - DPR */ base_k = 0xc0000 >> 10; size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k; - size_k -= dpr.size >> 10; + size_k -= dpr.size * MiB / KiB; ram_resource(dev, index++, base_k, size_k); /* TSEG - DPR -> BGSM */ resource = new_resource(dev, index++); - resource->base = mc_values[TSEG_REG] - dpr.size; + resource->base = mc_values[TSEG_REG] - dpr.size * MiB; resource->size = mc_values[BGSM_REG] - resource->base; resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; -- To view, visit https://review.coreboot.org/c/coreboot/+/51104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ca388907c61f1e47eab44ae8bc26e0f611fe1e3 Gerrit-Change-Number: 51104 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: acpi: Move PCI functions to separate file
by Patrick Georgi (Code Review) 01 Mar '21

01 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51106 ) Change subject: acpi: Move PCI functions to separate file ...................................................................... acpi: Move PCI functions to separate file Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Idc96b99da9f9037267c0bec2c839014b13ceb8cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/51106 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/acpi/Makefile.inc M src/acpi/acpigen.c A src/acpi/acpigen_pci.c M src/acpi/device.c M src/drivers/intel/dptf/dptf.c M src/drivers/intel/mipi_camera/camera.c M src/drivers/usb/pci_xhci/pci_xhci.c M src/drivers/wifi/generic/acpi.c M src/include/acpi/acpigen.h A src/include/acpi/acpigen_pci.h M src/soc/amd/picasso/pcie_gpp.c 11 files changed, 46 insertions(+), 21 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Lance Zhao: Looks good to me, approved diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc index 86f29e4..b8e4422 100644 --- a/src/acpi/Makefile.inc +++ b/src/acpi/Makefile.inc @@ -6,6 +6,7 @@ ramstage-y += acpigen.c ramstage-y += acpigen_dptf.c ramstage-y += acpigen_dsm.c +ramstage-$(CONFIG_PCI) += acpigen_pci.c ramstage-y += acpigen_ps2_keybd.c ramstage-y += acpigen_usb.c ramstage-y += device.c diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 4d9395f..b3e112d 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -18,8 +18,6 @@ #include <assert.h> #include <console/console.h> #include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_type.h> #include <device/soundwire.h> #include <types.h> @@ -2033,23 +2031,6 @@ acpigen_write_name_qword("_ADR", adr); } -void acpigen_write_ADR_pci_devfn(pci_devfn_t devfn) -{ - /* - * _ADR for PCI Bus is encoded as follows: - * [63:32] - unused - * [31:16] - device # - * [15:0] - function # - */ - acpigen_write_ADR(PCI_SLOT(devfn) << 16 | PCI_FUNC(devfn)); -} - -void acpigen_write_ADR_pci_device(const struct device *dev) -{ - assert(dev->path.type == DEVICE_PATH_PCI); - acpigen_write_ADR_pci_devfn(dev->path.pci.devfn); -} - /** * acpigen_write_ADR_soundwire_device() - SoundWire ACPI Device Address Encoding. * @address: SoundWire device address properties. diff --git a/src/acpi/acpigen_pci.c b/src/acpi/acpigen_pci.c new file mode 100644 index 0000000..66f8dcd --- /dev/null +++ b/src/acpi/acpigen_pci.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> +#include <acpi/acpigen_pci.h> +#include <assert.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_type.h> +#include <types.h> + +void acpigen_write_ADR_pci_devfn(pci_devfn_t devfn) +{ + /* + * _ADR for PCI Bus is encoded as follows: + * [63:32] - unused + * [31:16] - device # + * [15:0] - function # + */ + acpigen_write_ADR(PCI_SLOT(devfn) << 16 | PCI_FUNC(devfn)); +} + +void acpigen_write_ADR_pci_device(const struct device *dev) +{ + assert(dev->path.type == DEVICE_PATH_PCI); + acpigen_write_ADR_pci_devfn(dev->path.pci.devfn); +} diff --git a/src/acpi/device.c b/src/acpi/device.c index 5de31b7..5d4d9be 100644 --- a/src/acpi/device.c +++ b/src/acpi/device.c @@ -5,6 +5,7 @@ #include <acpi/acpi.h> #include <acpi/acpi_device.h> #include <acpi/acpigen.h> +#include <acpi/acpigen_pci.h> #include <device/device.h> #include <device/path.h> #include <stdlib.h> diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index 0f1cc9c..1713e72 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpigen.h> +#include <acpi/acpigen_pci.h> #include <console/console.h> #include <device/device.h> #include "chip.h" diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index 7dfd650..65eba16 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -4,6 +4,7 @@ #include <acpi/acpi.h> #include <acpi/acpi_device.h> #include <acpi/acpigen.h> +#include <acpi/acpigen_pci.h> #include <console/console.h> #include <device/i2c_simple.h> #include <device/device.h> diff --git a/src/drivers/usb/pci_xhci/pci_xhci.c b/src/drivers/usb/pci_xhci/pci_xhci.c index 6a56ca2..821cb5f 100644 --- a/src/drivers/usb/pci_xhci/pci_xhci.c +++ b/src/drivers/usb/pci_xhci/pci_xhci.c @@ -2,6 +2,7 @@ #include "pci_xhci.h" #include <acpi/acpigen.h> +#include <acpi/acpigen_pci.h> #include <console/console.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index 4440b81..3e3b5c1 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -2,6 +2,7 @@ #include <acpi/acpi_device.h> #include <acpi/acpigen.h> +#include <acpi/acpigen_pci.h> #include <console/console.h> #include <device/pci_ids.h> #include <sar.h> diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index 7b1141c..f7974eb 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -394,8 +394,6 @@ void acpigen_write_upc(enum acpi_upc_type type); void acpigen_write_pld(const struct acpi_pld *pld); void acpigen_write_ADR(uint64_t adr); -void acpigen_write_ADR_pci_devfn(pci_devfn_t devfn); -void acpigen_write_ADR_pci_device(const struct device *dev); struct soundwire_address; void acpigen_write_ADR_soundwire_device(const struct soundwire_address *address); void acpigen_write_create_byte_field(uint8_t op, size_t byte_offset, const char *name); diff --git a/src/include/acpi/acpigen_pci.h b/src/include/acpi/acpigen_pci.h new file mode 100644 index 0000000..f050575 --- /dev/null +++ b/src/include/acpi/acpigen_pci.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef ACPIGEN_PCI_H +#define ACPIGEN_PCI_H + +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_type.h> + +void acpigen_write_ADR_pci_devfn(pci_devfn_t devfn); +void acpigen_write_ADR_pci_device(const struct device *dev); + +#endif /* ACPIGEN_PCI_H */ diff --git a/src/soc/amd/picasso/pcie_gpp.c b/src/soc/amd/picasso/pcie_gpp.c index 00b32a0..baa9fa3 100644 --- a/src/soc/amd/picasso/pcie_gpp.c +++ b/src/soc/amd/picasso/pcie_gpp.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <acpi/acpigen.h> +#include <acpi/acpigen_pci.h> #include <arch/ioapic.h> #include <assert.h> #include <amdblocks/amd_pci_util.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/51106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc96b99da9f9037267c0bec2c839014b13ceb8cc Gerrit-Change-Number: 51106 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/gpio: Add gpio_routes_ioapic_irq function
by Patrick Georgi (Code Review) 01 Mar '21

01 Mar '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49407 ) Change subject: soc/intel/common/gpio: Add gpio_routes_ioapic_irq function ...................................................................... soc/intel/common/gpio: Add gpio_routes_ioapic_irq function This function returns true if any GPIO pad is programmed to route the given IRQ to the IO-APIC. It does so by keeping track of which pads are routed to IOxAPIC and looking this up in the new function. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Iceda89cb111caa15056c204b143b4a17d59e523e Reviewed-on: https://review.coreboot.org/c/coreboot/+/49407 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio.h 2 files changed, 30 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 28e78fb..fcce8d7 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -210,6 +210,24 @@ pcr_or32(comm->port, en_reg, en_value); } +/* 120 GSIs is the default for IOxAPIC */ +static uint32_t gpio_ioapic_irqs_used[120 / (sizeof(uint32_t) * BITS_PER_BYTE) + 1]; +static void set_ioapic_used(uint32_t irq) +{ + size_t word_offset = irq / 32; + size_t bit_offset = irq % 32; + assert (word_offset < ARRAY_SIZE(gpio_ioapic_irqs_used)); + gpio_ioapic_irqs_used[word_offset] |= BIT(bit_offset); +} + +bool gpio_routes_ioapic_irq(uint32_t irq) +{ + size_t word_offset = irq / 32; + size_t bit_offset = irq % 32; + assert (word_offset < ARRAY_SIZE(gpio_ioapic_irqs_used)); + return (gpio_ioapic_irqs_used[word_offset] & BIT(bit_offset)) != 0; +} + static void gpio_configure_itss(const struct pad_config *cfg, uint16_t port, uint16_t pad_cfg_offset) { @@ -217,9 +235,6 @@ if (ENV_SMM) return; - if (!CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG)) - return; - int irq; /* Set up ITSS polarity if pad is routed to APIC. @@ -242,8 +257,12 @@ cfg->pad); return; } - itss_set_irq_polarity(irq, !!(cfg->pad_config[0] & - PAD_CFG0_RX_POL_INVERT)); + + if (CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG)) + itss_set_irq_polarity(irq, !!(cfg->pad_config[0] & + PAD_CFG0_RX_POL_INVERT)); + + set_ioapic_used(irq); } /* Number of DWx config registers can be different for different SOCs */ diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index 4c29a0c..45ae1da 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -229,5 +229,11 @@ */ void block_gpio_enable(struct device *dev); +/* + * Returns true if any GPIO that uses the specified IRQ is also programmed to + * route IRQs to IOAPIC. + */ +bool gpio_routes_ioapic_irq(unsigned int irq); + #endif #endif /* _SOC_INTELBLOCKS_GPIO_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/49407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iceda89cb111caa15056c204b143b4a17d59e523e Gerrit-Change-Number: 49407 Gerrit-PatchSet: 11 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit March 2021