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I'd like you to reexamine a change. Please visit
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Change subject: sb/intel/lynxpoint: Finalize ME in ramstage
......................................................................
sb/intel/lynxpoint: Finalize ME in ramstage
Performing ME finalization in SMM does not seem to be required.
Tested on Asrock B85M Pro4, ME still gets finalized successfully.
Change-Id: I9fde40a54f3fb8da2fba46c531443fdd2e067077
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/southbridge/intel/lynxpoint/Makefile.inc
M src/southbridge/intel/lynxpoint/me.c
M src/southbridge/intel/lynxpoint/me.h
M src/southbridge/intel/lynxpoint/smihandler.c
4 files changed, 15 insertions(+), 47 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/51036/2
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Hello build bot (Jenkins), Nico Huber, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/51035
to look at the new patch set (#2).
Change subject: sb/intel/lynxpoint: Retype `mei_base_address` pointer
......................................................................
sb/intel/lynxpoint: Retype `mei_base_address` pointer
Also introduce uintptr_t cast and use PCI_BASE_ADDRESS_MEM_ATTR_MASK.
Change-Id: I32fdcc6b1ffde1b0701218a3bd0a61ab827081b5
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/southbridge/intel/lynxpoint/me.c
1 file changed, 9 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/51035/2
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50828 )
Change subject: mb/google/volteer: Fix FPMCU pwr/rst gpio handling
......................................................................
Patch Set 9: Code-Review+2
(1 comment)
Patchset:
PS9:
Duncan's word is good enough for me 😊
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Change subject: soc/intel/tigerlake: Re-use existing define in CrashLog implementation
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> There is already one named SOC_INTEL_COMMON_BLOCK_CRASHLOG inside […]
I just added a config file to build-test Crashlog on TGL: CB:51155
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Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51155 )
Change subject: configs/config.google_volteer.build_test_purposes: Add file
......................................................................
configs/config.google_volteer.build_test_purposes: Add file
This is meant to build-test Crashlog and various debug options.
Change-Id: Ie9bbfa538e38a4d835c1f8b0d45feb2f0fe803f8
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
A configs/config.google_volteer.build_test_purposes
1 file changed, 32 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/51155/1
diff --git a/configs/config.google_volteer.build_test_purposes b/configs/config.google_volteer.build_test_purposes
new file mode 100644
index 0000000..7b0d47f
--- /dev/null
+++ b/configs/config.google_volteer.build_test_purposes
@@ -0,0 +1,32 @@
+# Not meant for actual use, but rather to build-test individual options.
+# If keeping this combination of options buildable becomes too hard in
+# the future, then this config can be split into several smaller chunks.
+# Exercises, among other things:
+# + Debug options
+# + Crashlog
+# + Flashconsole
+CONFIG_VENDOR_GOOGLE=y
+CONFIG_CONSOLE_POST=y
+CONFIG_BOARD_GOOGLE_VOLTEER2=y
+CONFIG_USE_LEGACY_8254_TIMER=y
+CONFIG_INTEL_TME=y
+CONFIG_SOC_INTEL_CRASHLOG=y
+CONFIG_NO_GFX_INIT=y
+CONFIG_DISPLAY_HOBS=y
+CONFIG_DISPLAY_UPD_DATA=y
+CONFIG_CONSOLE_SPI_FLASH=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+CONFIG_DISPLAY_MTRRS=y
+CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
+CONFIG_DISPLAY_FSP_HEADER=y
+CONFIG_VERIFY_HOBS=y
+CONFIG_FATAL_ASSERTS=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_DEBUG_CBFS=y
+CONFIG_DEBUG_SMBUS=y
+CONFIG_DEBUG_SMI=y
+CONFIG_DEBUG_PERIODIC_SMI=y
+CONFIG_DEBUG_MALLOC=y
+CONFIG_DEBUG_CONSOLE_INIT=y
+CONFIG_DEBUG_SPI_FLASH=y
+CONFIG_DEBUG_BOOT_STATE=y
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Change subject: mb/google/volteer: Fix FPMCU pwr/rst gpio handling
......................................................................
Patch Set 9: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50828/comment/c2d75066_22d9cbff
PS8, Line 10: 2. Disable power and assert reset in ramstage gpio
> Duncan, any chance to test this yet?
I had tested the previous version, just tested this iteration and it still works.
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