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Hello build bot (Jenkins), Furquan Shaikh, Henry Sun, Evan Green,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/dedede/var/drawcia: Re-tune override GPIO table
......................................................................
mb/google/dedede/var/drawcia: Re-tune override GPIO table
There is going to be an upcoming board version for Drawlat/man and
Drawcia. Hence apply the override GPIO table without pad termination for
board versions 6 or 8 alone.
BUG=None
BRANCH=dedede
TEST=Build and boot to OS in Drawcia.
Change-Id: I320de9a0c37ac033f3efda74eeb8f36e34667fd4
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/mainboard/google/dedede/variants/drawcia/gpio.c
1 file changed, 10 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/51153/4
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50966 )
Change subject: Documentation/coding_style: Issues not mentioned and cleanup patches
......................................................................
Patch Set 1:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50966/comment/3f9511f3_d5c748b3
PS1, Line 7: Issues not mentioned and cleanup patches
> Nit: It’d be great if you made this a statement.
I already had trouble coming up with a good subject that fits 72 characters as it is. Feel free to make a concrete suggestion but this was the most expressive I could find.
File Documentation/coding_style.md:
https://review.coreboot.org/c/coreboot/+/50966/comment/47f4468d_e983fed4
PS1, Line 22: improvement. By default the style choices of the original author should
> IMHO, another valid reason to clean up code style is when deduplicating stuff. […]
Sure, I would not consider that a "cleanup patch" in this sense because deduplicating is an actual code change, not just a style change. Of course when you're deduplicating multiple different versions into one, you get to make the style choices for the new combined version.
Do you think I need to add any specific text here to make that clearer? I would consider that implied already but happy to take suggestions.
https://review.coreboot.org/c/coreboot/+/50966/comment/7a67299d_53ab472f
PS1, Line 27: bulk-applied to change existing code.)
> New contributors should read this, though.
Yeah... I mean, I agree that there's plenty room for improvement in this document (the text is ancient, copied from a different project and pretty rambling in many places, after all... I think a simple, to the point "this is how you're supposed to do things" style with the explanations hidden in collapsible sections might be more readable). But I don't think "abandon this document and write a new one" can be a solution. We need to have a single coding style doc that reviewers can point to. We should fix the issues in this one rather than having a confusing mess of different documents side by side.
https://review.coreboot.org/c/coreboot/+/50966/comment/14db7857_7bf17d92
PS1, Line 24: `clang-format`. These tools can be useful to find
: potential issues or simplify formatting in new submissions, but they
: were not designed to directly match this guide and they should not be
: bulk-applied to change existing code.
> There are ideas to enforce clang-format across the tree (the crossgcc version to keep everybody on t […]
Well, I think you know how I feel about that, and as far as I'm aware there has been no agreement to make clang-format mandatory yet. I don't think anyone can seriously say that changes like https://review.coreboot.org/c/coreboot/+/50853/1/src/soc/rockchip/rk3399/sd… actually make the code better, and I have personally not seen this particular style issue (continuation line indentation) being much quibbled about either. It's just something that many authors like to do on their own to make their code easier to read for themselves and others, and I don't see why we should force them not to.
Anyway, I'm just trying to explain the current situation here right now. This file can always be updated again when and if there's a new consensus on clang-format.
https://review.coreboot.org/c/coreboot/+/50966/comment/62d8aadd_9adc7379
PS1, Line 27: bulk-applied to change existing code.)
> Please mention that checkpath.pl and clang-format can report false-positives.
Yes, that was basically what I'm trying to say here. Clarified a bit in new version.
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Change subject: Documentation/coding_style: Issues not mentioned and cleanup patches
......................................................................
Documentation/coding_style: Issues not mentioned and cleanup patches
This patch adds a bit of a "preamble" to the coding style to provide
guideance on how it should be applied and how style questions that
aren't mentioned should be handled.
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Change-Id: I88efd5f1006bd1fd82cea14ea65422d9958dc197
---
M Documentation/contributing/coding_style.md
1 file changed, 18 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/50966/2
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Change subject: mb/amd/majolica: Add eSPI support
......................................................................
Patch Set 9:
(4 comments)
File src/mainboard/amd/majolica/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49966/comment/cbaa786a_4f00078d
PS8, Line 7: ESPI_IO_MODE_SINGLE
> UEFI is using quad
Done
https://review.coreboot.org/c/coreboot/+/49966/comment/e48f9010_09632db3
PS8, Line 8: ESPI_OP_FREQ_33_MHZ
> UEFI is using 16 MHz
Done
https://review.coreboot.org/c/coreboot/+/49966/comment/bb48a700_c689bf19
PS8, Line 11: ,
> should be 1
Done
https://review.coreboot.org/c/coreboot/+/49966/comment/43b6923b_bac05d06
PS8, Line 12: 0
> 1 as well
Done
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Change subject: mb/amd/majolica: Add eSPI support
......................................................................
mb/amd/majolica: Add eSPI support
Change-Id: I3e82a51173f561df560c36528a9b7ec26cf489b5
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
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---
M src/mainboard/amd/majolica/Kconfig
M src/mainboard/amd/majolica/devicetree.cb
2 files changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/49966/9
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Change subject: elog: Support logging CSE Lite info in elog
......................................................................
Patch Set 5:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50472/comment/b6f7afb3_54114c04
PS5, Line 23: ...
: 3 | 2021-01-17 08:01:57 | CSE Info | Lite | 13.50.0.1269 | 13.50.0.1269
: | YES | 0x5 | 0x0 | RW
What does the rest of the eventlog look like? I think we log things like boot count and system boot info much later in ramstage. Is this info printed before System Boot in the log?
File src/soc/intel/alderlake/me.c:
https://review.coreboot.org/c/coreboot/+/50472/comment/33c09322_15c62505
PS5, Line 136: ((hfsts1.fields.spi_protection_mode == 0) &&
: (hfsts6.fields.fpf_soc_lock == 1))
Can you please update this to use `cse_mfg_mode` as well?
File src/soc/intel/cannonlake/me.c:
https://review.coreboot.org/c/coreboot/+/50472/comment/9461116e_bff16d54
PS5, Line 131: hfsts1.fields.mfg_mode
Same here and for other SoCs.
File src/soc/intel/common/block/cse/cse_lite.c:
https://review.coreboot.org/c/coreboot/+/50472/comment/c446c1b3_021b83ab
PS5, Line 14:
nit: use space here and on line 15 below for consistency with other #defines in this file.
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Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization codes
......................................................................
Patch Set 13:
(8 comments)
File src/vendorcode/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/50294/comment/576ff967_a896bd99
PS13, Line 7: # subdirs-y += mediatek
Why is this still commented out?
File src/vendorcode/mediatek/Kconfig:
https://review.coreboot.org/c/coreboot/+/50294/comment/6ef94bea_acca8c4e
PS13, Line 9: config MT8192_DRAM_DVFS
Please try to design this from the start so it will make sense when more SoCs are added (i.e. the MT8192-specific options should go into the mt8192 subdirectory Kconfig). If we expect to also have the same options for future SoCs, they should be prefixed MEDIATEK, not MT8192.
File src/vendorcode/mediatek/mt8192/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/50294/comment/f45b0d31_18ac1abf
PS13, Line 1: ifeq ($(CONFIG_SOC_MEDIATEK_MT8192),y)
This could just be `subdirs-$(CONFIG_SOC_MEDIATEK_MT8192) +=` in the Makefile one level higher.
File src/vendorcode/mediatek/mt8192/dramc/ANA_init_config.c:
PS13:
Even vendorcode files always need to have an SPDX header (it would be great if MediaTek could just put these in whatever upstream they're maintaining). You can choose to make it BSD or whatever else you want that's compatible with the GPL, of course.
File src/vendorcode/mediatek/mt8192/dramc/emi.c:
https://review.coreboot.org/c/coreboot/+/50294/comment/9f2aa138_4302fb2b
PS13, Line 5: Without
: * the prior written permission of MediaTek inc. and/or its licensors, any
: * reproduction, modification, use or disclosure of MediaTek Software, and
: * information contained herein, in whole or in part, shall be strictly
: * prohibited.
This doesn't work. It still needs to be open-source code.
File src/vendorcode/mediatek/mt8192/driver/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/50294/comment/1e2273fd_b1a8f231
PS13, Line 5: romstage-y += uart.c
Doesn't coreboot have all these already? Please avoid duplicating drivers between vendorcode and coreboot, everything should be in either one or the other. The vendorcode can call out back to coreboot for these (you can make extra wrapper APIs for them if you want to isolate them a bit more).
File src/vendorcode/mediatek/mt8192/include/stdint.h:
PS13:
Why is this file duplicated here? (Not to mention the fact that this is clearly an original coreboot GPL file where you just stripped off the license header, which is... you know... don't ever do that, please.) Unless I'm missing something in your Makefiles, you're just adding the vendorcode headers to the include path that already contains existing coreboot headers. So the normal version of this file should already be available.
File src/vendorcode/mediatek/mt8192/lib/print.c:
https://review.coreboot.org/c/coreboot/+/50294/comment/30bc222c_6d9db841
PS13, Line 101: static int vprint(const char *fmt, va_list ap)
This too is something we really don't want to have a duplicate of in the codebase.
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Change subject: lib/cbfs.c: Fix return value of failure to measure
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Or do it get it wrong? Is the TPM doing nothing or is there a cbfs error?
This error case is most likely a TPM communication issue or something like that, it's not really related to the CBFS file. So if you can't extend the real file hash here, chances are you probably can't extend anything else either. You can only ignore it or die().
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51076 )
Change subject: soc/amd/cezanne: Disable legacy DMA IO ports
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Patch Set 2: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/51076/comment/02148920_1225e3c1
PS2, Line 10: ports.
> Ports 0x80-0x83 were not being router to the DMA controller either. […]
ok
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50857 )
Change subject: sb/intel/common: Refactor _PRT generation to support GSI-based tables
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Patch Set 7:
(1 comment)
File src/southbridge/intel/common/acpi_pirq_gen.c:
https://review.coreboot.org/c/coreboot/+/50857/comment/2ea3b3d9_ee15d5bf
PS3, Line 33: pirq - PIRQ_A
> Yeah, looking at the latest patches.. like you said, it is a little cleaner.. […]
Good suggestions, I took 'em and ran with it 😄
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