coreboot-gerrit March 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: src/mediatek/mt8192: use Mediatek mt8192 vendor code (CB:50294)
by Xi Chen (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Hung-Te Lin, Martin Roth, Paul Menzel. Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51125 to look at the new patch set (#5). Change subject: src/mediatek/mt8192: use Mediatek mt8192 vendor code (CB:50294) ...................................................................... src/mediatek/mt8192: use Mediatek mt8192 vendor code (CB:50294) Mediatek maintains the DRAM initialization code, the coding style is different from coreboot, when CB:50294 is ready, soc/mediatek/mt8192 will not be used. Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: I2b2f41d774c6b85f106867144fb0b29a4a1bdfcf --- R src/soc/mediatek/common/dpm.c A src/soc/mediatek/common/dram_init.c R src/soc/mediatek/common/dramc_param.c R src/soc/mediatek/common/include/soc/dpm.h R src/soc/mediatek/common/include/soc/dramc_param.h A src/soc/mediatek/common/include/soc/emi.h R src/soc/mediatek/common/memory.c M src/soc/mediatek/mt8192/Kconfig M src/soc/mediatek/mt8192/Makefile.inc D src/soc/mediatek/mt8192/dramc_ana_init_config.c D src/soc/mediatek/mt8192/dramc_dig_config.c D src/soc/mediatek/mt8192/dramc_dvfs.c D src/soc/mediatek/mt8192/dramc_pi_basic_api.c D src/soc/mediatek/mt8192/dramc_pi_calibration_api.c D src/soc/mediatek/mt8192/dramc_pi_main.c D src/soc/mediatek/mt8192/dramc_power.c D src/soc/mediatek/mt8192/dramc_subsys_config.c D src/soc/mediatek/mt8192/dramc_tracking.c D src/soc/mediatek/mt8192/dramc_utility.c D src/soc/mediatek/mt8192/emi.c D src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h D src/soc/mediatek/mt8192/include/soc/dramc_common_mt8192.h D src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h D src/soc/mediatek/mt8192/include/soc/dramc_power.h D src/soc/mediatek/mt8192/include/soc/dramc_register.h D src/soc/mediatek/mt8192/include/soc/dramc_register_bits_def.h A src/soc/mediatek/mt8192/include/soc/dramc_soc.h D src/soc/mediatek/mt8192/include/soc/emi.h M src/vendorcode/Makefile.inc 29 files changed, 171 insertions(+), 19,568 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/51125/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/51125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b2f41d774c6b85f106867144fb0b29a4a1bdfcf Gerrit-Change-Number: 51125 Gerrit-PatchSet: 5 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vendor: mediatek: Add mediatek mt8192 dram initialization codes
by Xi Chen (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Xi Chen, Hung-Te Lin, Nico Huber, Martin Roth, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Menzel, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50294 to look at the new patch set (#14). Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization codes ...................................................................... vendor: mediatek: Add mediatek mt8192 dram initialization codes Add the DRAM initialization code based on Mediatek reference implementation. Mediatek internally maintains the DRAM initialization code, following different coding style. To prevent maintaining a different branch for coreboot (which may lead to typo or errors which switching between different coding style), we want to directly use the reference implementation as vendor code. Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 --- A src/vendorcode/mediatek/Kconfig A src/vendorcode/mediatek/Makefile.inc A src/vendorcode/mediatek/mt8192/Makefile.inc A src/vendorcode/mediatek/mt8192/dramc/ANA_init_config.c A src/vendorcode/mediatek/mt8192/dramc/DIG_NONSHUF_config.c A src/vendorcode/mediatek/mt8192/dramc/DIG_SHUF_config.c A src/vendorcode/mediatek/mt8192/dramc/DRAMC_SUBSYS_config.c A src/vendorcode/mediatek/mt8192/dramc/DRAM_config_collctioin.c A src/vendorcode/mediatek/mt8192/dramc/Hal_io.c A src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c A src/vendorcode/mediatek/mt8192/dramc/Makefile.inc A src/vendorcode/mediatek/mt8192/dramc/dramc_actiming.c A src/vendorcode/mediatek/mt8192/dramc/dramc_dv_freq_related.c A src/vendorcode/mediatek/mt8192/dramc/dramc_dvfs.c A src/vendorcode/mediatek/mt8192/dramc/dramc_lowpower.c A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_calibration_api.c A src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c A src/vendorcode/mediatek/mt8192/dramc/dramc_top.c A src/vendorcode/mediatek/mt8192/dramc/dramc_tracking.c A src/vendorcode/mediatek/mt8192/dramc/dramc_utility.c A src/vendorcode/mediatek/mt8192/dramc/emi.c A src/vendorcode/mediatek/mt8192/driver/Makefile.inc A src/vendorcode/mediatek/mt8192/driver/pmic_wrap.c A src/vendorcode/mediatek/mt8192/driver/timer.c A src/vendorcode/mediatek/mt8192/driver/uart.c A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_AO.h A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_MD32.h A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DDRPHY_NAO.h A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_AO.h A src/vendorcode/mediatek/mt8192/include/Margaux_Register_DRAMC_NAO.h A src/vendorcode/mediatek/mt8192/include/addressmap.h A src/vendorcode/mediatek/mt8192/include/custom_emi.h A src/vendorcode/mediatek/mt8192/include/ddrphy_nao_reg.h A src/vendorcode/mediatek/mt8192/include/ddrphy_pll_reg.h A src/vendorcode/mediatek/mt8192/include/ddrphy_wo_pll_reg.h A src/vendorcode/mediatek/mt8192/include/dramc_actiming.h A src/vendorcode/mediatek/mt8192/include/dramc_ch0_nao_reg.h A src/vendorcode/mediatek/mt8192/include/dramc_ch0_reg.h A src/vendorcode/mediatek/mt8192/include/dramc_common.h A src/vendorcode/mediatek/mt8192/include/dramc_dv_init.h A src/vendorcode/mediatek/mt8192/include/dramc_int_global.h A src/vendorcode/mediatek/mt8192/include/dramc_int_slt.h A src/vendorcode/mediatek/mt8192/include/dramc_pi_api.h A src/vendorcode/mediatek/mt8192/include/dramc_reg_base_addr.h A src/vendorcode/mediatek/mt8192/include/dramc_register.h A src/vendorcode/mediatek/mt8192/include/dramc_top.h A src/vendorcode/mediatek/mt8192/include/dramc_typedefs.h A src/vendorcode/mediatek/mt8192/include/emi.h A src/vendorcode/mediatek/mt8192/include/emi_hw.h A src/vendorcode/mediatek/mt8192/include/emi_mpu_mt.h A src/vendorcode/mediatek/mt8192/include/emi_mpu_v1.h A src/vendorcode/mediatek/mt8192/include/memory.h A src/vendorcode/mediatek/mt8192/include/pmic_wrap_init.h A src/vendorcode/mediatek/mt8192/include/print.h A src/vendorcode/mediatek/mt8192/include/reg.h A src/vendorcode/mediatek/mt8192/include/stdint.h A src/vendorcode/mediatek/mt8192/include/sv_c_data_traffic.h A src/vendorcode/mediatek/mt8192/include/sys/types.h A src/vendorcode/mediatek/mt8192/include/uart.h A src/vendorcode/mediatek/mt8192/include/x_hal_io.h A src/vendorcode/mediatek/mt8192/lib/Makefile.inc A src/vendorcode/mediatek/mt8192/lib/print.c 63 files changed, 87,259 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/50294/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/50294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 Gerrit-Change-Number: 50294 Gerrit-PatchSet: 14 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Cindy Ching <cindy.ching(a)mediatek.corp-partner.google.com> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-CC: Yidi Lin <yidi.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entry
by Cliff Huang (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Bora Guvendik, Anil Kumar K, Furquan Shaikh, Wonkyu Kim, Angel Pons, Bernardo Perez Priego, Srinidhi N Kaushik, Patrick Rudolph. Hello Bora Guvendik, Anil Kumar K, build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Selma Bensaid, Bernardo Perez Priego, Srinidhi N Kaushik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50897 to look at the new patch set (#8). Change subject: soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entry ...................................................................... soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entry FSP has added the Cnvi BT Core enabling in addition to the existing CnviMode. This change adds the flag at the soc config side (i.e. soc_intel_tigerlake_config for devicetree). Also, there is no longer PCI host interface for BT. Therefore, BT core should not use the pci port status to turn on/off. TEST: BT enumeration is checked using 'lsusb -d 8087:0026' from OS to make sure BT is turned on. Change-Id: I71c512fe884060e23ee26e7334c575c4c517b78d Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 14 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/50897/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/50897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71c512fe884060e23ee26e7334c575c4c517b78d Gerrit-Change-Number: 50897 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/mediatek/mt8192: use Mediatek mt8192 vendor code (CB:50294)
by Xi Chen (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Hung-Te Lin, Martin Roth, Paul Menzel. Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51125 ) Change subject: src/mediatek/mt8192: use Mediatek mt8192 vendor code (CB:50294) ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/51125/comment/fce267af_c8f57f95 PS3, Line 7: src/mediatek/mt8192: use Mediatek mt8192 vendor code(CB:50294) > Please add a space before the (. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/51125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b2f41d774c6b85f106867144fb0b29a4a1bdfcf Gerrit-Change-Number: 51125 Gerrit-PatchSet: 4 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Mar 2021 02:32:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entry
by build bot (Jenkins) (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Bora Guvendik, Anil Kumar K, Furquan Shaikh, Wonkyu Kim, Angel Pons, Bernardo Perez Priego, Srinidhi N Kaushik, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50897 ) Change subject: soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entry ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/tigerlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/50897/comment/e8fec46a_fe64e05c PS7, Line 357: if (params->CnviBtCore) { braces {} are not necessary for any arm of this statement -- To view, visit https://review.coreboot.org/c/coreboot/+/50897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71c512fe884060e23ee26e7334c575c4c517b78d Gerrit-Change-Number: 50897 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 02 Mar 2021 02:31:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entry
by Cliff Huang (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Bora Guvendik, Anil Kumar K, Furquan Shaikh, Wonkyu Kim, Angel Pons, Bernardo Perez Priego, Srinidhi N Kaushik, Patrick Rudolph. Hello Bora Guvendik, Anil Kumar K, build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Selma Bensaid, Bernardo Perez Priego, Srinidhi N Kaushik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50897 to look at the new patch set (#7). Change subject: soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entry ...................................................................... soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entry FSP has added the Cnvi BT Core enabling in addition to the existing CnviMode. This change adds the flag at the soc config side (i.e. soc_intel_tigerlake_config for devicetree). Also, there is no longer PCI host interface for BT. Therefore, BT core should not use the pci port status to turn on/off. TEST: BT enumeration is checked using 'lsusb -d 8087:0026' from OS to make sure BT is turned on. Change-Id: I71c512fe884060e23ee26e7334c575c4c517b78d Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 15 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/50897/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/50897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71c512fe884060e23ee26e7334c575c4c517b78d Gerrit-Change-Number: 50897 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/mediatek/mt8192: use Mediatek mt8192 vendor code (CB:50294)
by Xi Chen (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Xi Chen, Hung-Te Lin, Martin Roth. Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51125 to look at the new patch set (#4). Change subject: src/mediatek/mt8192: use Mediatek mt8192 vendor code (CB:50294) ...................................................................... src/mediatek/mt8192: use Mediatek mt8192 vendor code (CB:50294) Mediatek maintains the DRAM initialization code, the coding style is different from coreboot, when CB:50294 is ready, soc/mediatek/mt8192 will not be used. Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: I2b2f41d774c6b85f106867144fb0b29a4a1bdfcf --- R src/soc/mediatek/common/dpm.c A src/soc/mediatek/common/dram_init.c R src/soc/mediatek/common/dramc_param.c R src/soc/mediatek/common/include/soc/dpm.h R src/soc/mediatek/common/include/soc/dramc_param.h A src/soc/mediatek/common/include/soc/emi.h R src/soc/mediatek/common/memory.c M src/soc/mediatek/mt8192/Kconfig M src/soc/mediatek/mt8192/Makefile.inc D src/soc/mediatek/mt8192/dramc_ana_init_config.c D src/soc/mediatek/mt8192/dramc_dig_config.c D src/soc/mediatek/mt8192/dramc_dvfs.c D src/soc/mediatek/mt8192/dramc_pi_basic_api.c D src/soc/mediatek/mt8192/dramc_pi_calibration_api.c D src/soc/mediatek/mt8192/dramc_pi_main.c D src/soc/mediatek/mt8192/dramc_power.c D src/soc/mediatek/mt8192/dramc_subsys_config.c D src/soc/mediatek/mt8192/dramc_tracking.c D src/soc/mediatek/mt8192/dramc_utility.c D src/soc/mediatek/mt8192/emi.c D src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h D src/soc/mediatek/mt8192/include/soc/dramc_common_mt8192.h D src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h D src/soc/mediatek/mt8192/include/soc/dramc_power.h D src/soc/mediatek/mt8192/include/soc/dramc_register.h D src/soc/mediatek/mt8192/include/soc/dramc_register_bits_def.h A src/soc/mediatek/mt8192/include/soc/dramc_soc.h D src/soc/mediatek/mt8192/include/soc/emi.h 28 files changed, 170 insertions(+), 19,568 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/51125/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/51125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b2f41d774c6b85f106867144fb0b29a4a1bdfcf Gerrit-Change-Number: 51125 Gerrit-PatchSet: 4 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Documentation: Codify some guidelines for headers and chain-including
by Julius Werner (Code Review) 01 Mar '21

01 Mar '21

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50247 ) Change subject: Documentation: Codify some guidelines for headers and chain-including ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Sorry, more serious: Before I agree to any rule about any sorting, I need to see any argument _for_ it. Maybe you know the answer: Is there an effective benefit in alphabetical order? Well, I think it helps read the list of headers and check whether a specific header is already in there. I don't really feel like it's a hassle either, I just do it automatically when I write a new file. (If you're just touching an existing file and someone asks you to alphabetize headers that weren't before that's a different thing, of course, you should generally not be made responsible to clean up style in stuff you didn't write originally.) Would you be okay if I just made it say that other orders are okay if they're intentional (e.g. something like "They should generally be sorted in alphabetical order, but authors are free to group them in thematical blocks when desired. In rare cases technical constraints may mandate an order, which should be clearly documented with comments.")? I think people generally just dislike when they're shuffled completely randomly, or when they used to be alphabetized but then someone else came along and just added a few lines onto the end for no reason. If you group your headers with some intentional order in your file that's not strictly alphabetical but makes sense, I don't think anybody should have a problem with that. -- To view, visit https://review.coreboot.org/c/coreboot/+/50247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbcde306a814f52b3a41b58c7a33bdd99b0187e0 Gerrit-Change-Number: 50247 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Mar 2021 02:11:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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Change in coreboot[master]: security/tpm/tss/vendor/cr50: Introduce vendor sub-command to reset EC
by Karthik Ramasubramanian (Code Review) 01 Mar '21

01 Mar '21

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51164 ) Change subject: security/tpm/tss/vendor/cr50: Introduce vendor sub-command to reset EC ...................................................................... security/tpm/tss/vendor/cr50: Introduce vendor sub-command to reset EC Add marshaling and unmarshaling support for cr50 vendor sub-command to reset EC and a interface function to exchange the same. BUG=b:181051734 TEST=Build and boot to OS in drawlat. Ensure that when the command is issued, EC reset is triggered. Change-Id: I46063678511d27fea5eabbd12fc3af0b1df68143 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/security/tpm/tss/tcg-2.0/tss_marshaling.c M src/security/tpm/tss/vendor/cr50/cr50.c M src/security/tpm/tss/vendor/cr50/cr50.h 3 files changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/51164/1 diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index 3efd5ad..f21fe3d 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -333,6 +333,9 @@ case TPM2_CR50_SUB_CMD_GET_BOOT_MODE: rc |= obuf_write_be16(ob, *sub_command); break; + case TPM2_CR50_SUB_CMD_RESET_EC: + rc |= obuf_write_be16(ob, *sub_command); + break; default: /* Unsupported subcommand. */ printk(BIOS_WARNING, "Unsupported cr50 subcommand: 0x%04x\n", @@ -560,6 +563,8 @@ return ibuf_read_be8(ib, &vcr->tpm_mode); case TPM2_CR50_SUB_CMD_GET_BOOT_MODE: return ibuf_read_be8(ib, &vcr->boot_mode); + case TPM2_CR50_SUB_CMD_RESET_EC: + break; default: printk(BIOS_ERR, "%s:%d - unsupported vendor command %#04x!\n", diff --git a/src/security/tpm/tss/vendor/cr50/cr50.c b/src/security/tpm/tss/vendor/cr50/cr50.c index a5b8057..8bc530d 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.c +++ b/src/security/tpm/tss/vendor/cr50/cr50.c @@ -148,3 +148,27 @@ return TPM_SUCCESS; } + +uint32_t tlcl_cr50_reset_ec(void) +{ + struct tpm2_response *response; + uint16_t mode_command = TPM2_CR50_SUB_CMD_RESET_EC; + + printk(BIOS_DEBUG, "Issuing EC reset\n"); + + response = tpm_process_command(TPM2_CR50_VENDOR_COMMAND, &mode_command); + + if (!response) + return TPM_E_IOERROR; + + if (response->hdr.tpm_code == VENDOR_RC_NO_SUCH_COMMAND || + response->hdr.tpm_code == VENDOR_RC_NO_SUCH_SUBCOMMAND) + /* Explicitly inform caller when command is not supported */ + return TPM_E_NO_SUCH_COMMAND; + + if (response->hdr.tpm_code) + /* Unexpected return code from Cr50 */ + return TPM_E_IOERROR; + + return TPM_SUCCESS; +} diff --git a/src/security/tpm/tss/vendor/cr50/cr50.h b/src/security/tpm/tss/vendor/cr50/cr50.h index 7730ecc..b739794 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.h +++ b/src/security/tpm/tss/vendor/cr50/cr50.h @@ -15,6 +15,7 @@ #define TPM2_CR50_SUB_CMD_GET_REC_BTN (29) #define TPM2_CR50_SUB_CMD_TPM_MODE (40) #define TPM2_CR50_SUB_CMD_GET_BOOT_MODE (52) +#define TPM2_CR50_SUB_CMD_RESET_EC (53) /* Cr50 vendor-specific error codes. */ #define VENDOR_RC_ERR 0x00000500 @@ -95,4 +96,14 @@ */ uint32_t tlcl_cr50_immediate_reset(uint16_t timeout_ms); +/** + * CR50 specific TPM command sequence to issue an EC reset. + * + * Returns TPM_SUCCESS if EC reset is supported. + * Returns TPM_E_* for errors. + * Issue a halt() after triggering EC reset because cr50 leaves 50 ms after receiving + * the command to reset the EC. + */ +uint32_t tlcl_cr50_reset_ec(void); + #endif /* CR50_TSS_STRUCTURES_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/51164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46063678511d27fea5eabbd12fc3af0b1df68143 Gerrit-Change-Number: 51164 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Re-tune override GPIO table
by Karthik Ramasubramanian (Code Review) 01 Mar '21

01 Mar '21

Attention is currently required from: Furquan Shaikh, Henry Sun, Evan Green. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51153 ) Change subject: mb/google/dedede/var/drawcia: Re-tune override GPIO table ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/dedede/variants/drawcia/gpio.c: https://review.coreboot.org/c/coreboot/+/51153/comment/223297be_50c9afac PS3, Line 28: board_version == 6 || board_version == 8 > That makes sense. So my suggestion is still to change "== 8" to ">= 8". Done -- To view, visit https://review.coreboot.org/c/coreboot/+/51153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I320de9a0c37ac033f3efda74eeb8f36e34667fd4 Gerrit-Change-Number: 51153 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Evan Green <evgreen(a)chromium.org> Gerrit-Comment-Date: Tue, 02 Mar 2021 01:57:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Evan Green <evgreen(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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